Patents Issued in December 30, 2010
  • Publication number: 20100329016
    Abstract: The performance of a semiconductor device including a nonvolatile memory is enhanced. Each of nonvolatile memory cells arranged over a silicon substrate includes: a first n-well; a second n-well formed in a place different from the place thereof; a selection transistor formed in the first n-well; and an electric charge storage portion having a floating gate electrode and a storage portion p-well. The floating gate electrode is so placed that it overlaps with part of the first n-well and the second n-well. The storage portion p-well is placed in the first n-well so that it partly overlaps with the floating gate electrode. In this nonvolatile memory cell, memory information is erased by applying positive voltage to the second n-well to discharge electrons in the floating gate electrode to the second n-well.
    Type: Application
    Filed: June 18, 2010
    Publication date: December 30, 2010
    Inventor: Yasuhiro TANIGUCHI
  • Publication number: 20100329017
    Abstract: According to one embodiment, a semiconductor device includes a first voltage generator, a second voltage generator, a first MOS transistor, and a controller. The first voltage generator outputs a first voltage to a first node. The second voltage generator outputs a second voltage to a second node. The first MOS transistor is capable of short-circuiting the first node and second node. The controller performs a control operation to short-circuit the first node and second node by turning on the first MOS transistor. The controller controls a period in which the first MOS transistor is kept in an on state based on time.
    Type: Application
    Filed: June 24, 2010
    Publication date: December 30, 2010
    Inventors: Takeshi NAKANO, Mikio Ogawa
  • Publication number: 20100329018
    Abstract: A nonvolatile memory device is operated by receiving a dual plane read command for simultaneously reading first and second planes, each comprising memory cells, receiving an MSB read address for reading data stored in the memory cells, checking whether an MSB program operation has been performed on each of the first and second planes, and performing the read operation on the first and second planes according to a result of the check and outputting the read data.
    Type: Application
    Filed: June 30, 2010
    Publication date: December 30, 2010
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventor: Byoung In JOO
  • Publication number: 20100329019
    Abstract: When data is read from a memory cell of a top array block to a bit line, a switching device is closed so that the data is stored in the form of electrical charges at a bit line of a bottom array block. The switching device at a top array side is opened to drive a sense amplifier, and thus, the data read from the memory cell and retained at the bit line of the bottom array block is output to the outside. While the data is output in the above-described manner, a potential of the bit line of the top array block can be precharged to start a next read operation.
    Type: Application
    Filed: September 2, 2010
    Publication date: December 30, 2010
    Applicant: Panasonic Corporation
    Inventor: Toshio MUKUNOKI
  • Publication number: 20100329020
    Abstract: A method of programming a nonvolatile memory device includes an initial data setting step of inputting data for program inhibition to a first latch of a page buffer to which memory cells to be programmed with a second threshold voltage distribution are coupled, a first program and verification step of performing program and verification operations, a first data setting step of, when a program pulse is supplied more than N times (where N is a natural number), inputting data for performing a program operation to the first latch of the page buffer to which the memory cells to be programmed with the second threshold voltage distribution are coupled, and a second program and verification step of performing program and verification operations.
    Type: Application
    Filed: June 8, 2010
    Publication date: December 30, 2010
    Inventors: Jung Chul HAN, Seong Je Park
  • Publication number: 20100329021
    Abstract: A method of programming a nonvolatile memory device includes inputting program data to page buffers; performing a program operation and a program verification operation until threshold voltages of memory cells included in a selected page reach a target level according to the program data; when the threshold voltages of the memory cells reach the target level, performing an over-program verification operation to determine over-programmed memory cells in the memory cells; and making a determination of whether error checking and correction (ECC) processing for the over-programmed memory cells is feasible.
    Type: Application
    Filed: June 29, 2010
    Publication date: December 30, 2010
    Inventor: Hee Youl Lee
  • Publication number: 20100329022
    Abstract: A method of programming a nonvolatile memory device comprises performing a first program operation on first memory cells and second memory cells so that threshold voltages of the first and second memory cells have a first reference level lower than a first target level, the first memory cells having the first target level as a first target level, and the second memory cells having a second target level higher than the first target level as a second target level; performing a second program operation on the second memory cells so that the threshold voltages of the second memory cells have a second reference level lower than the second target level; and performing a third program operation on the first and second memory cells to have the respective target levels.
    Type: Application
    Filed: June 30, 2010
    Publication date: December 30, 2010
    Inventors: Seung Hwan Baik, Ju Yeab Lee
  • Publication number: 20100329023
    Abstract: Some embodiments include apparatus and methods having a sense amplifier unit, a supply node to receive a supply voltage, and a line coupled to a memory cell of a device. The sense amplifier unit includes a circuit path coupled between the supply node and the line to carry a current having a value based on a value of information stored in the memory cell. Additional embodiments are disclosed.
    Type: Application
    Filed: June 25, 2009
    Publication date: December 30, 2010
    Applicant: Atmel Corporation
    Inventors: Jimmy Fort, Thierry Soude, Nicolas Zammit
  • Publication number: 20100329024
    Abstract: A memory that employs separate Dynamic reference (Dref) areas to provide a threshold voltage reference signal. The memory includes the separate Dref areas, a data area positioned between the Dref areas, a reference array, and one or more sense amplifiers. The data area is arranged to provide an output signal, the reference cell and the separate Dref areas are arranged to provide the threshold voltage reference signal, and the sense amplifiers are arranged to receive the output signal and the threshold voltage reference signal.
    Type: Application
    Filed: June 29, 2009
    Publication date: December 30, 2010
    Applicant: Spansion LLC
    Inventors: Kenta Kato, Masahiro Niimi, Koji Shimbayashi
  • Publication number: 20100329025
    Abstract: The present invention provides a readout circuit including: a memory cell array that includes a readout target memory cell that is a data readout target; a reference memory cell having the same configuration as this memory cell; a first constant current source and a second constant current source which have the same characteristics; and a reference current source that generates, as a reference current for determining the logic level of the readout target memory cell, a current obtained by adding one constant current, out of a first constant current flowing through the first constant current source or a second constant current flowing through the second constant current source, with a reference memory cell current flowing in the reference memory cell, and by subtracting the other constant current, out of the first constant current or the second constant current, from the added current.
    Type: Application
    Filed: June 23, 2010
    Publication date: December 30, 2010
    Applicant: OKI SEMICONDUCTOR CO., LTD.
    Inventor: Nobukazu Murata
  • Publication number: 20100329026
    Abstract: According to one embodiment, a semiconductor memory device includes memory cells, first and second selection transistors, a source line, a temperature monitor, and a source line voltage controller. The memory cells are connected in series between a source of the first selection transistor and a drain of the second selection transistor. The temperature monitor monitors a temperature of the semiconductor substrate. The source line voltage controller applies a voltage to the source line, in a read operation, in such a manner that a potential difference between the source line and the semiconductor substrate increases according to a rise in the temperature monitored by the temperature monitor and that a reverse bias is applied between the source of the second selection transistor and the semiconductor substrate.
    Type: Application
    Filed: June 24, 2010
    Publication date: December 30, 2010
    Inventors: Mitsutoshi NAKAMURA, Takeshi Shimane, Michiru Hogyoku, Katsuaki Isobe, Naoyuki Shigyo
  • Publication number: 20100329027
    Abstract: A nonvolatile memory device includes a control unit configured to output operation signals, including an operation command signal, a source address, a destination address, and a data signal, to each of a number of memory chips in order to operate the memory chips, a command decoder configured to decode the command signal and generate operation command information, a source address controller configured to generate source address information based on the source address, a destination address controller configured to generate destination address information based on the destination address, a chip controller configured to generate a command enable signal based on the operation command information, the source address information, and the destination address information, and a data controller configured to operate a memory cell array in response to the data signal and the command enable signal.
    Type: Application
    Filed: April 20, 2010
    Publication date: December 30, 2010
    Inventor: Won Kyung KANG
  • Publication number: 20100329028
    Abstract: A method of performing a program verification operation in a nonvolatile memory device includes storing program data, programmed into a selected memory cell of a memory cell block, in a page buffer which is coupled to a bit line of the memory cell block via a sense node, controlling a voltage level of the sense node in response to a value of the program data, changing the voltage level of the sense node in response to a program state of the selected memory cell coupled to the bit line, and performing a program verification operation on the selected memory cell by sensing the voltage level of the sense node.
    Type: Application
    Filed: April 21, 2010
    Publication date: December 30, 2010
    Inventors: Kyu Hee LIM, Seong Je Park
  • Publication number: 20100329029
    Abstract: A page buffer includes a sense latch, a data latch and a page buffer controller. The sense latch is connected to a bit line, and is configured to set stored data in response to a sense latch control signal, and to change the stored data in response to a signal applied to the bit line in a data verification operation. The data latch is configured to store multi-bit data to be programmed in a program operation, and to set stored data in response to a data latch control signal in the data verification operation. The page buffer controller is configured to control the bit line in accordance with the multi-bit data stored in the data latch in the program operation, and to output the sense latch control signal and the data latch control signal in accordance with the multi-bit data stored in the data latch in response to a control signal in the data verification operation.
    Type: Application
    Filed: June 2, 2010
    Publication date: December 30, 2010
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sung-Won Yun, Oh-Suk Kwon
  • Publication number: 20100329030
    Abstract: In a nonvolatile memory device, a cache program operation for the next data is performed in a first latch, and a verification program operation for the current data is performed using a second latch. Thus, data collision can be avoided and execution time can be reduced.
    Type: Application
    Filed: June 29, 2010
    Publication date: December 30, 2010
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventors: Byoung Sung YOU, Jin Su PARK, Seong Je PARK
  • Publication number: 20100329031
    Abstract: A method of operating a nonvolatile memory device includes precharging bit lines coupled to strings, supplying a first verification voltage to a selected word line and supplying a pass voltage to word lines other than the selected word line, supplying a first sense pulse to switching elements coupled between the bit lines and sense nodes and detecting memory cells, each having a threshold voltage higher than the first verification voltage, supplying a second verification voltage higher than the first verification voltage to the selected word line and supplying the pass voltage to the word lines other than the selected word line, and supplying a second sense pulse to the switching elements and detecting memory cells, each having a threshold voltage higher than the second verification voltage.
    Type: Application
    Filed: June 29, 2010
    Publication date: December 30, 2010
    Inventor: Eun Joung Lee
  • Publication number: 20100329032
    Abstract: A nonvolatile memory device has memory cells coupled to bit lines and word lines and page buffers each coupled to one or more of the bit lines. Program and verification operations are performed on a first logical page from among first and second logical pages included in memory cells selected for a program operation. Data are loaded which will be programmed into the second logical page into first to third latches of a selected page buffer, coupled to the selected memory cells, from among the page buffers. A data setting operation is performed. The second logical page is programmed so that a distribution of threshold voltages of the selected memory cells has one of first to fourth threshold voltage distributions according to states of the data of the first to third latches and performing verification operations for the first to fourth threshold voltage distributions.
    Type: Application
    Filed: June 29, 2010
    Publication date: December 30, 2010
    Applicant: Hynix Semiconductor Inc.
    Inventor: Sang Oh LIM
  • Publication number: 20100329033
    Abstract: In general, according to one embodiment, a nonvolatile semiconductor memory device includes: a memory cell array including memory cells; and a control unit to control a signal applied to the memory cells. Each of the memory cells are settable to: first, second and third states having first, second and third threshold voltage distributions (VD1, VD2 and VD3, VD1<VD3<VD2), respectively. In an operation of setting a second memory cell to the second state and setting a third memory cell to the third state, the control unit: sets the memory cells to the first state; sets the second memory cell to a state having a threshold voltage distribution between VD2 and VD3; performs a weak writing to increase a threshold voltage distribution of the memory cells; and sets the third memory cell to the third state.
    Type: Application
    Filed: June 28, 2010
    Publication date: December 30, 2010
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Takeshi KAMIGAICHI
  • Publication number: 20100329034
    Abstract: One or more groups of charge-storing memory cells are selected from a plurality of regular charge-storing memory cells of a storage device. The selected memory cells are initialized with initial binary data, by charging them with corresponding amounts of electric charge, or the selected memory cells are simply used as is containing user data. Then, while the selected memory cells undergo a self discharge process, collective changes in the binary states of the selected memory cells are used to estimate discharge-determining conditions such as elapsed time, wear rate or wear level of the memory cells. The adverse effects of the erratic behavior of individual charge-storing memory cells on such estimations is mitigated by using a large group of charge-storing memory cells, and the effect of temperature on the aforesaid estimations is reduced by using two or more large groups of charge-storing memory cells.
    Type: Application
    Filed: June 30, 2009
    Publication date: December 30, 2010
    Inventor: DONALD RAY BRYANT-RICH
  • Publication number: 20100329035
    Abstract: A discharge circuit of a nonvolatile semiconductor memory device includes a memory array region including a plurality of floating gate type MOS memory cell transistors each including a source, a drain and a control gate which are formed in a P-well, where the P-well is formed in an N-well of a P-type semiconductor substrate. The discharge circuit further includes a plurality of terminals formed in the memory array region, and respectively connected to the control gate, the P-well and the N-well, a plurality of constant current transistors respectively connected to the plurality of terminals, and a plurality of switching transistors respectively connected to the plurality of constant current transistors. The respective constant current transistors and switching transistors are turned on at a same timing during a discharge operation.
    Type: Application
    Filed: June 16, 2010
    Publication date: December 30, 2010
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Yuichiro Nakagaki
  • Publication number: 20100329036
    Abstract: In a nonvolatile memory device and operating method thereof, data programmed into a second memory cell is sensed and a first memory cell adjacent the second memory cell is read in accordance with the data sensed from the second memory cell.
    Type: Application
    Filed: June 29, 2010
    Publication date: December 30, 2010
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventor: Jin Su PARK
  • Publication number: 20100329037
    Abstract: A circuit for supplying well voltages in a nonvolatile memory device includes an erase voltage supply unit for supplying an erase voltage to a well in response to an erase enable signal, a discharge unit for discharging the erase voltage, supplied to the well, in response to a discharge control signal, and a negative voltage supply unit for supplying a negative voltage to the well in response to a negative voltage output enable signal.
    Type: Application
    Filed: June 30, 2010
    Publication date: December 30, 2010
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventor: Gyo Soo CHU
  • Publication number: 20100329038
    Abstract: Methods of operating memory devices include storing data of a first type in a first set of logical erase blocks and storing data of a second type in a second set of logical erase blocks. The logical erase blocks of the first set of logical erase blocks each have a first size the logical erase blocks of the second set of logical erase blocks each have a second size different than the first size.
    Type: Application
    Filed: September 3, 2010
    Publication date: December 30, 2010
    Inventor: Frankie F. Roohparvar
  • Publication number: 20100329039
    Abstract: A data buffer control circuit and a semiconductor memory apparatus including the same are presented. The data buffer control circuit may include an internal command signal generator and a buffer enable signal generator. The internal command signal generator is configured to generate an internal command signal that is activated if delayed command signals are conditioned in a predetermined state of level combination. The buffer enable signal generator is configured to generate a buffer enable signal, which enables a data buffer receiving data in a writing mode, from the internal command signal in sync with a falling edge of an internal clock signal.
    Type: Application
    Filed: December 28, 2009
    Publication date: December 30, 2010
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventor: Bok Rim KO
  • Publication number: 20100329040
    Abstract: A data alignment circuit of a semiconductor memory apparatus includes: a data strobe clock phase control block configured to control a phase of a data strobe clock signal in response to a strobe delay code and generate a delayed strobe clock signal; a plurality of data phase control blocks configured to control phases of input data in response to data delay codes and generate delayed data; a plurality of data alignment blocks configured to latch the delayed data in response to the delayed strobe clock signal and generate latched data and aligned data; and a delay code generation block configured to perform an operation of determining phases of the latched data and generate the strobe delay code and the data delay codes.
    Type: Application
    Filed: December 29, 2009
    Publication date: December 30, 2010
    Applicants: HYNIX SEMICONDUCTOR INC., INDUSTRY-UNIVERSITY COOPERATION FOUNDATION, HANYANG UNIVERSITY
    Inventors: Chun Seok JEONG, Kee Teok PARK, Chang Sik YOO, Jang Woo LEE, Hong Jung KIM
  • Publication number: 20100329041
    Abstract: A semiconductor memory device includes a memory cell array, a controller, and a data input/output (I/O) unit. The memory cell array includes a plurality of memory cells and is configured to store data. The controller is configured to enable a write clock signal in response to an active command when a write latency of the semiconductor device is less than a reference write latency and disable the write clock signal during a disabling period in which read data is output from the semiconductor device. The data I/O unit is configured to receive data in response to the write clock signal and output the data to the memory cell array.
    Type: Application
    Filed: June 10, 2010
    Publication date: December 30, 2010
    Inventors: Young-Soo SOHN, Kwang-IL Park, Kyoung-Ho Kim, Seung-Jun Bae
  • Publication number: 20100329042
    Abstract: A memory chip includes a memory circuit unit configured to include memory cells for storing data, a data input and output (I/O) buffer unit configured to include a plurality of data I/O buffer circuits, wherein one of the data I/O buffer circuits is operated by default in order to input and output data to and from the memory chip, a plurality of driver control units configured to generate a plurality of driver addition signals to enable corresponding ones of the data I/O buffer circuits depending on whether a power supply voltage has been received, and a controller configured to generate I/O enable signals for controlling an operation of the data I/O buffer unit.
    Type: Application
    Filed: June 29, 2010
    Publication date: December 30, 2010
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventor: Jin Yong Seong
  • Publication number: 20100329043
    Abstract: Embodiments relate to a two-transistor (2T) floating-body cell (FBC) for embedded-DRAM applications. Further embodiments pertain to a floating-body/gate cell (FBGC), which yields reduction in power dissipation, in addition to better signal margin, longer data retention, and higher memory density.
    Type: Application
    Filed: October 1, 2008
    Publication date: December 30, 2010
    Applicant: University of Florida Research Foundation, Inc.
    Inventors: Jerry G. Fossum, Leo Mathew, Michael Sadd, Vishal P. Trivedi
  • Publication number: 20100329044
    Abstract: A data store and method of storing data is disclosed that comprises: an input for receiving a data value; at least one storage cell comprising: a feedback loop for storing the data value; an output for outputting the stored data value; the feedback loop receiving a higher voltage and a lower voltage as power supply, the data store further comprising: a voltage supply for powering the data store, the voltage supply outputting a high voltage level and a low voltage level; write assist circuitry arranged between the voltage supply and the at least one storage cell, the write assist circuitry being responsive to a pulse signal to provide a discharge path between the high voltage level and a lower voltage level and thereby generate a reduced internal voltage level from the high voltage level for a period dependent on a width of the pulse signal, the reduced internal voltage level being lower than the high voltage level, such that when powered the feedback loop receives the reduced internal voltage level as the hig
    Type: Application
    Filed: June 29, 2009
    Publication date: December 30, 2010
    Applicant: ARM Limited
    Inventor: Gus Yeung
  • Publication number: 20100329045
    Abstract: A method and system are provided for adjusting a write timing in a memory device. For instance, the method can include receiving a data signal, a write clock signal, and a reference signal. The method can also include detecting a phase shift in the reference signal over time. The phase shift of the reference signal can be used to adjust a phase difference between the data signal and the write clock signal, where the memory device recovers data from the data signal based on an adjusted write timing of the data signal and the write clock signal.
    Type: Application
    Filed: June 24, 2009
    Publication date: December 30, 2010
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Ming-Ju Edward LEE, Shadi M. Barakat, Warren Fritz Kruger, Xiaoling Xu, Toan Duc Pham, Aaron John Nygren
  • Publication number: 20100329046
    Abstract: Some embodiments include apparatus and methods having a memory cell included in a device, a control line configured to receive a control signal to access the memory cell, and a first line configured to transfer information to and from the memory cell. The control signal has a first level during a first time interval and a second level during a second time interval of a memory operation. The apparatus and methods also include a module configured to reduce difference between a value of a voltage on the second line and a value of a voltage on a node of the device during a first time portion of the second time interval. Additional apparatus and methods are disclosed.
    Type: Application
    Filed: June 25, 2009
    Publication date: December 30, 2010
    Inventors: Brian W. Huber, Jason M. Brown
  • Publication number: 20100329047
    Abstract: A nonvolatile memory device, including an X decoder coupling global lines to respective word lines to which memory cells are coupled, a voltage supply unit comprising voltage selection circuits corresponding to the respective global lines and configured to generate operating voltages, wherein each of the voltage selection circuits latches control signals, each determined according to a corresponding line enable signal and a corresponding voltage control signal, and selects and supplies one of the operating voltages in response to the control signals, and a control unit supplying a number of the line enable signals and a number of the voltage control signals to the voltage supply unit.
    Type: Application
    Filed: June 8, 2010
    Publication date: December 30, 2010
    Inventor: Jee Yul KIM
  • Publication number: 20100329048
    Abstract: A precharge signal generator having a latch signal generator, an internal signal generator, and a pulse generator is presented. The latch signal generator is configured to generate a latch signal that is activated in response to an auto-precharge command and inactivated in response to an active pulse. The internal signal generator is configured to generate an internal signal activated when a delayed active signal and the latch signal are all activated. The pulse generator is configured to generate a precharge signal including a pulse that is activated in a period for which the internal signal is being active.
    Type: Application
    Filed: December 28, 2009
    Publication date: December 30, 2010
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventor: Youk Hee KIM
  • Publication number: 20100329049
    Abstract: A semiconductor memory device includes a latency controller which provides a power-saving effect. The latency controller includes a first-in first-out (FIFO) register. After a read command is applied, when a precharge command or power-down command is applied, the latency controller outputs a latency signal corresponding to the applied read command and blocks application of sampling and transmission clock signals to the FIFO register.
    Type: Application
    Filed: June 22, 2010
    Publication date: December 30, 2010
    Inventors: YOUNG-SOO SOHN, Jeong-Don Lim, Kwang-Il Park
  • Publication number: 20100329050
    Abstract: A semiconductor memory device having read and write operations includes a discrimination signal generating unit for generating a discrimination signal during the write operation; and a selective delay unit for receiving and selectively delaying a command-group signal in response to the discrimination signal.
    Type: Application
    Filed: September 7, 2010
    Publication date: December 30, 2010
    Inventors: Kyung-Whan KIM, Seok-Cheol Yoon
  • Publication number: 20100329051
    Abstract: A circuit for synchronizing row and column access operations in a semiconductor memory having an array of bit line pairs, word lines, memory cells, sense amplifiers, and a sense amplifier power supply circuit for powering the sense amplifiers, the circuit comprising, a first delay circuit for delaying a word line timing pulse by a first predetermined period, a first logic circuit for logically combining the word line timing pulse and the delayed word line timing pulse to produce a sense amplifier enable signal, for enabling a sense amplifier power supply circuit, a second delay circuit for delaying the word line timing pulse by a second predetermined period, and a second logic circuit for logically combining the word line timing pulse and the second delayed word line timing pulse to produce a column select enable signal, for enabling selected ones of a plurality of column access devices wherein the second predetermined time period is selected so that ones of a plurality of column access devices are activated
    Type: Application
    Filed: September 9, 2010
    Publication date: December 30, 2010
    Applicant: MOSAID TECHNOLOGIES INCORPORATED
    Inventor: Paul DEMONE
  • Publication number: 20100329052
    Abstract: Method for detecting word line defect includes activating a first word line for reading a first data pre-stored in the memory cell, suspending the first word line for a predetermined period and then writing a second data complementary to the first data into the memory cell, activating again the first word line for reading a third data from the memory cell, and comparing the second and the third data for determining if an electrical coupling path exists between the first word line and a second word line.
    Type: Application
    Filed: August 18, 2009
    Publication date: December 30, 2010
    Inventors: Wei-Jen Chen, Ho-Yin Chen, Lien-Sheng Yang, Shu-Jen Wu
  • Publication number: 20100329053
    Abstract: Provided is a semiconductor memory device. The semiconductor memory includes a main area and a redundancy area. The main area includes a plurality of memory blocks sharing a write bit line and a read bit line. The redundancy area includes a plurality of redundancy memory blocks sharing a redundancy write bit line and a redundancy read bit line. The redundancy area is provided to replace a component in the main area having a defect.
    Type: Application
    Filed: June 14, 2010
    Publication date: December 30, 2010
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Joonmin Park, Beakhyung Cho, Kwangjin Lee, Hye-Jin Kim
  • Publication number: 20100329054
    Abstract: A memory circuit includes an operational memory and a monitor circuit comprising a circuit element in the operational memory and/or a circuit element substantially identical to a corresponding circuit element in the operational memory. The monitor circuit is operative to measure at least one functional characteristic of the operational memory. A control circuit coupled to the monitor circuit is operative to generate a control signal which varies as a function of the measured characteristic of the operational memory. The memory circuit further includes a programmable voltage source coupled to the operational memory which is operative to generate at least a voltage and/or a current supplied to at least a portion of the operational memory which varies as a function of the control signal.
    Type: Application
    Filed: June 30, 2009
    Publication date: December 30, 2010
    Inventors: Kouros Azimi, Roger A. Fratti, Danny Martin George, Richard J. McPartland
  • Publication number: 20100329055
    Abstract: A circuit having a first circuit configured to receive an input voltage and generate a first voltage that generates a first current flowing through a resistive device and a second voltage that generates a second current; a node electrically coupled to the resistive device and having a third voltage that generates a third current; and a second circuit configured to generate a fourth voltage having a logic state indicating a logic state of the resistive device.
    Type: Application
    Filed: June 28, 2010
    Publication date: December 30, 2010
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuoyuan HSU, Po-Hung CHEN, Jiann-Tseng HUANG, Subramani KENGERI
  • Publication number: 20100329056
    Abstract: A sense amplifier resistant to malfunctions associated with offsets in inverter pairs is presented. The sense amplifier includes inverter pairs and a controller. Any one input terminal of the inverter pairs is electrically connected to a bit line and the other one input terminal is electrically connected to a /bit line. The controller is configured to precharge the bit line and the /bit line to a level corresponding to an offset of the inverter pairs in response to a first control signal. The controller senses a voltage difference of the bit line and the /bit line using the inverter pairs by connecting output terminals of the inverter pairs to the bit line pairs in response to a second control signal.
    Type: Application
    Filed: December 29, 2009
    Publication date: December 30, 2010
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventor: Jin Yeong MOON
  • Publication number: 20100329057
    Abstract: In a method of discharging bit-lines for a non-volatile semiconductor memory device performing a read-while-write operation. The method include discharging a global write bit-line to a ground voltage based on a write command within a first period. the method also includes maintaining the discharged voltage of the global write bit-line in the ground voltage during a second period.
    Type: Application
    Filed: April 21, 2010
    Publication date: December 30, 2010
    Inventors: Yong-Jun Lee, Byung-Gil Choi, Du-Eung Kim
  • Publication number: 20100329058
    Abstract: A processor includes a cache memory. The cache memory includes an array of cells, word lines and bit lines. A control module enables a word line of the word lines to access a first cell in the enabled word line. The control module disables the word line and maintains the word line in a disabled state to access a second cell in the word line.
    Type: Application
    Filed: August 25, 2010
    Publication date: December 30, 2010
    Inventors: Sehat Sutardja, Jason T. Su, Hong-Yi Chen, Jason Sheu, Jensen Tjeng
  • Publication number: 20100329059
    Abstract: Some embodiments include apparatus and methods having a sense amplifier unit, a supply node to receive a supply voltage, and a line coupled to a memory cell of a device. The sense amplifier unit includes a circuit path coupled between the supply node and the line to carry a current having a value based on a value of information stored in the memory cell; and a second circuit including a second circuit path coupled between the supply node and the line to charge the line during the memory operation. Additional embodiments are disclosed.
    Type: Application
    Filed: June 25, 2009
    Publication date: December 30, 2010
    Applicant: Atmel Corporation
    Inventor: Jimmy Fort
  • Publication number: 20100329060
    Abstract: A counter control signal generator comprises a first pulse signal generator configured to generate a first pulse signal including a pulse generated when a self-refresh period is terminated, a second pulse signal generator configured to generate a second pulse signal including a pulse generated in sync with a cyclic signal generated during a refresh period, and a signal generator configured to generate a counter control signal counting an address of a memory cell, corresponding to a memory cell on which a refresh operation is conducted, in response to the first and second pulse signals.
    Type: Application
    Filed: December 30, 2009
    Publication date: December 30, 2010
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventor: Mi Hyun HWANG
  • Publication number: 20100329061
    Abstract: A fuse circuit is disclosed, which comprises at least one electrical fuse element having a resistance that changes after being stressed in an electromigration mode, a switching device serially coupled with the electrical fuse element in a predetermined path between a fuse programming power supply (VDDQ) and a low voltage power supply (GND) for selectively allowing a programming current passing through the electrical fuse element during a programming operation, and at least one peripheral circuit coupled to the VDDQ, wherein the peripheral circuit is active and draws current from the VDDQ during a fuse programming operation.
    Type: Application
    Filed: September 14, 2010
    Publication date: December 30, 2010
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shine Chung, Fu-Lung Hsueh, Fu-Chieh Hsu
  • Publication number: 20100329062
    Abstract: In one embodiment, an integrated circuit includes a logic circuit and a memory circuit that includes multiple bit lines and bit line precharge circuits. The memory circuit may include level shifters for control signals generated from logic circuit inputs, and particularly there may be one or more level shifters that generate precharge enable signals to control the bit line precharge circuits. The level shifters for the bit line precharge circuits may also be controlled, during periods of time that the memory circuit is idle, by an input control signal (FloatBL herein). If the FloatBL signal is asserted, the bit line precharge circuits may be disabled to float the bit lines. In some embodiments, the FloatBL signal may also disable bit line bit line hold circuits on the bit lines. In some embodiments, when the memory circuit is exiting an idle state, the bit line precharge circuits may be enabled in a staggered fashion.
    Type: Application
    Filed: June 26, 2009
    Publication date: December 30, 2010
    Inventors: Brian J. Campbell, Greg M. Hess, Hang Huang
  • Publication number: 20100329063
    Abstract: A memory device that includes multiple blocks of static random access memory (SRAM), which each have a standby mode and an active operating mode, is described. During the active operating mode, a selection circuit couples a higher voltage from a first power-signal line and a power-supply circuit to a given block of SRAM, and during the standby mode the selection circuit couples a lower voltage from a second power-signal line to the given block of SRAM. Note that a regulator circuit regulates the lower voltage on the second power-signal line by selectively opening or closing a first switch between the first power-signal line and the second power-signal line. Furthermore, a recycling circuit selectively opens a second switch between the first switch and the first power-signal line when the block of SRAM transitions from the active operating mode to the standby mode, thereby transferring charge from the block of SRAM to other blocks of SRAM.
    Type: Application
    Filed: June 30, 2009
    Publication date: December 30, 2010
    Applicant: SUN MICROSYSTEMS, INC.
    Inventors: Hoyeol Cho, Heechoul Park, Jungyong Lee
  • Publication number: 20100329064
    Abstract: Power-backup capabilities are provided by implementing a variety of different methods, systems and devices. According to one such implementation, a data storage device stores data in response to data accesses under the control of a memory control circuit. A solid-state memory circuit and a volatile caching memory circuit provide the memory control circuit with access to a set of common data. A power-reservoir circuit includes two or more capacitor cells that respectively hold charge to provide operating power to the data storage device to permit transfer of the data from the volatile memory circuit to the solid-state memory circuit in the event of a power loss. A detection circuit is connected to a center tap between the capacitor cells and uses the tap to detect characteristics of the cells relative to one another, and to provide an output that can be used to characterize the cells' electrical characteristics relative to one another.
    Type: Application
    Filed: June 26, 2009
    Publication date: December 30, 2010
    Inventor: Dean Clark Wilson
  • Publication number: 20100329065
    Abstract: Power-backup capabilities are provided by implementing a variety of different methods, systems and devices. According to one such implementation, an energy storage circuit is powered using a variable voltage controlled to limit the current draw from a power supply, to charge the energy storage circuit for providing backup power to a solid state drive (SSD) type of data storage arrangement. Certain applications involve controlling the power draw from the power supply, in response to feedback and/or power drawn from other circuits, as may be applicable to an initial startup of the energy storage circuit and/or the initial startup of a larger system in which the energy storage circuit is employed.
    Type: Application
    Filed: December 7, 2009
    Publication date: December 30, 2010
    Inventors: Darren Edward Johnston, Dean Clark Wilson