Patents Issued in February 8, 2011
  • Patent number: 7883924
    Abstract: For producing a photovoltaic module (1), the front electrode layer (3), the semi-conductor layer (4) and the back electrode layer (5) are patterned by separating lines (6, 7, 8) to form series-connected cells (C1, C2, . . . Cn, Cn+1) with a laser (14) emitting infrared radiation. During patterning of the semiconductor layer (4) and the back electrode layer (5) the power of the laser (14) is so reduced that the front electrode layer (3) is not damaged.
    Type: Grant
    Filed: January 21, 2009
    Date of Patent: February 8, 2011
    Assignee: Schott Solar GmbH
    Inventors: Peter Lechner, Walter Psyk
  • Patent number: 7883925
    Abstract: An image sensor can include a plurality of photodiodes and a plurality of transistors formed in a semiconductor substrate; a first interlayer insulating layer formed over the semiconductor substrate; a plurality of metal lines formed over the first interlayer insulating layer, electrically connected with the photodiodes and the transistors; a plurality of interlayer insulating layers including an upper interlayer insulating layer and a lower interlayer insulating layer formed over the semiconductor substrate including the metal lines, wherein refractive indexes of the upper interlayer insulating layer and the lower interlayer insulating layer are different from each other; a plurality of color filters formed over the plurality of interlayer insulating layers and which correspond to the photodiodes, respectively; a planarization layer formed over the semiconductor substrate including the color filters; and a plurality of microlenses formed over the planarization layer and which corresponds to the color filters
    Type: Grant
    Filed: November 29, 2007
    Date of Patent: February 8, 2011
    Assignee: Dongbu HiTek Co., Ltd.
    Inventor: Jung-Bae Kim
  • Patent number: 7883926
    Abstract: Image sensor devices and methods for fabricating the same are provided. An exemplary embodiment of an image sensor device comprises a support substrate. A passivation structure is formed over the support substrate. An interconnect structure is formed over the passivation structure. A first semiconductor layer is formed over the interconnect structure, having a first and second surfaces, wherein the first and second surfaces are opposing surfaces. At least one light-sensing device is formed over/in the first semiconductor layer from a first surface thereof. A color filter layer is formed over the first semiconductor layer from a second surface thereof. At least one micro lens is formed over the color filter layer.
    Type: Grant
    Filed: February 23, 2010
    Date of Patent: February 8, 2011
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Gwo-Yuh Shiau, Ming-Chyi Liu, Yuan-Chih Hsieh, Shih-Chi Fu, Chia-Shiung Tsai
  • Patent number: 7883927
    Abstract: Methods and systems for sorting nanostructures, such as nanodot or nanotubes, are described. The sorting of the nanostructures removes remnants of the nanotube fabrication from the mixture or bundle of material. The sorting includes suspending the mixture in a plasma, which separated the nanostructures and remnant material. A motive force, such as gas flow or laser, is applied to the suspended nanostructures and remnants such that the larger material moves out of the plasma while the smaller material remains trapped in the plasma.
    Type: Grant
    Filed: August 31, 2005
    Date of Patent: February 8, 2011
    Assignee: Micron Technology, Inc.
    Inventor: Krupakar M. Subramanian
  • Patent number: 7883928
    Abstract: An image sensor and fabricating method thereof are provided. The image sensor can include a color filter on a semiconductor substrate, a microlens on the color filter layer, and a carbon-doped low temperature oxide layer on the microlens.
    Type: Grant
    Filed: September 20, 2007
    Date of Patent: February 8, 2011
    Assignee: Dongbu Hitek Co., Ltd.
    Inventor: Cheon Man Shim
  • Patent number: 7883929
    Abstract: Integrated circuit nonvolatile memory devices are manufactured by forming a variable resistance layer on an integrated circuit substrate. The variable resistance layer includes grains that define grain boundaries between the grains. Conductive filaments are formed along at least some of the grain boundaries. Electrodes are formed on the variable resistance layer. The conductive filaments may be formed by implanting conductive ions into at least some of the grain boundaries. Moreover, the variable resistance layer may be a variable resistance oxide of a metal, and the conductive filaments may be the metal. Related devices are also disclosed.
    Type: Grant
    Filed: February 21, 2008
    Date of Patent: February 8, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Byung-Yong Choi, Choong-Ho Lee, Kyu-Charn Park
  • Patent number: 7883930
    Abstract: A phase change memory including at least a storage cell which includes a first electrode, an electrically conductive portion provided on the first electrode and having at least two electrically conductive bodies with approximately the same shape provided on the first electrode, the electrically conductive bodies being spaced by a high resistance film with a high resistance, a recording layer provided on the electrically conductive portion and having phase change material which can change between a first phase state with a first specific resistance and a second phase state with a second specific resistance different from the first specific resistance, and a second electrode provided on the recording layer.
    Type: Grant
    Filed: August 1, 2008
    Date of Patent: February 8, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takayuki Tsukamoto, Katsuyuki Naito, Sumio Ashida
  • Patent number: 7883931
    Abstract: In some embodiments, a memory cell includes a transistor gate spaced from a channel region by gate dielectric; a source region on one side of the channel region; and a drain region on an opposing side of the channel region from the source region. The channel region has phase change material adjacent the drain region. In some embodiments, the phase change material may be adjacent both the source region and the drain region. Some embodiments include methods of programming a memory cell that has phase change material adjacent a drain region. An inversion layer is formed within the channel region adjacent the gate dielectric, with the inversion layer having a pinch-off region within the phase change material adjacent the drain region. Hot carriers (for instance, electrons) within the pinch-off region are utilized to change a phase within the phase change material.
    Type: Grant
    Filed: February 6, 2008
    Date of Patent: February 8, 2011
    Assignee: Micron Technology, Inc.
    Inventor: Jun Liu
  • Patent number: 7883932
    Abstract: Molecular devices and methods of manufacturing the molecular device are provided. The molecular device may include a lower electrode on a substrate and a self-assembled monolayer on the lower electrode. After an upper electrode is formed on the self-assembled monolayer, the self-assembled monolayer may be removed to form a gap between the lower electrode and the upper electrode. A functional molecule having a functional group may be injected into the gap.
    Type: Grant
    Filed: February 12, 2008
    Date of Patent: February 8, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-Won Kim, Dong-Gun Park, Sung-Young Lee, Yang-Kyu Choi, Lee-Eun Yu
  • Patent number: 7883933
    Abstract: In one embodiment of the invention, a method of fabricating a SAM device comprises the steps of: (a) providing a substrate having a top surface and a first metal electrode disposed on the top surface, (b) annealing the first metal electrode, (c) forming a SAM layer on a major surface of the first electrode, the SAM layer having a free surface such that the SAM is disposed between the free surface and the major surface of the first electrode, and (d) forming a second metal electrode on the free surface of the molecular layer. Forming step (d) includes the step of (d1) depositing the second metal electrode in at least two distinct depositions separated by an interruption period of time when essentially no deposition of the second metal takes place. SAM FETs fabricated using this method are also described.
    Type: Grant
    Filed: September 16, 2009
    Date of Patent: February 8, 2011
    Assignee: Alcatel-Lucent USA Inc.
    Inventor: Nikolai Borisovich Zhitenev
  • Patent number: 7883934
    Abstract: A method for fabricating a device using an oxide semiconductor, including a process of forming the oxide semiconductor on a substrate and a process of changing the conductivity of the oxide semiconductor by irradiating a predetermined region thereof with an energy ray.
    Type: Grant
    Filed: February 19, 2010
    Date of Patent: February 8, 2011
    Assignee: Canon Kabushiki Kaisha
    Inventors: Nobuyuki Kaji, Hisato Yabuta
  • Patent number: 7883935
    Abstract: Aimed at improving adhesiveness between upper and lower interconnects in semiconductor devices, a semiconductor device of the present invention includes a second dielectric multi-layered film formed on a substrate, and containing a lower interconnect; a first dielectric multi-layered film formed on the second dielectric multi-layered film, and having a recess; an MOx film formed on the inner wall of the recess, and containing a metal M and oxygen as major components; an M film formed on the MOx film, and containing the M as a major component; and an electric conductor formed on the M film so as to fill the recess, and containing Cu as a major component, wherein the surficial portion of the interconnect fallen straight under the bottom of the recess has an oxygen concentration of 1% or smaller.
    Type: Grant
    Filed: April 12, 2010
    Date of Patent: February 8, 2011
    Assignee: Renesas Electronics Corporation
    Inventor: Akira Furuya
  • Patent number: 7883936
    Abstract: In a method and system for fabricating a semiconductor device (100) having a package-on-package structure, a base laminate substrate (BLS) (110) is formed to include a base center portion (112) and a peripheral portion (114) separated by a barrier element (120). The barrier element (120) forms a peripheral wall (118) to surround the base center portion (112). A frame shaped top laminate substrate (TLS) (130) is disposed over the peripheral portion (114) of the BLS (110). The TLS (130) has an open top center portion (132) matching the base center portion (112) surrounded by the peripheral wall (118) to form a cavity (140). A plurality of conductive bumps (150) each disposed between a top contact pad (134) of the TLS and a base contact pad (116) of the peripheral portion (114) of the BLS (110) are formed to provide electrical and mechanical coupling therebetween. The barrier element (120) forms a seal between the cavity (140) and the plurality of conductive bumps (150).
    Type: Grant
    Filed: November 16, 2009
    Date of Patent: February 8, 2011
    Assignee: Texas Instruments Incorporated
    Inventors: Prema Palaniappan, Masood Murtuza, Satyendra S Chauhan
  • Patent number: 7883937
    Abstract: The present invention is directed to a method and electronic computer package that is formed by placing an integrated circuit, having a plurality of bonding pads with solder bumps deposited thereon, in contact with the substrate so that one of the plurality of solder bumps is in superimposition with respect to one of the contacts and one of the plurality of bonding pads, with a volume being defined between region of the substrate in superimposition with the integrated circuit. A portion of the volume is filled with a quantity of underfill. A fluid flow barrier is formed on the substrate and defines a perimeter of the volume, defining a flow restricted region. The fluid flow barrier has dimensions sufficient to control the quantity of underfill egressing from the flow restricted region.
    Type: Grant
    Filed: April 30, 2007
    Date of Patent: February 8, 2011
    Assignee: Altera Corporation
    Inventors: Teck-Gyu Kang, Yuan Li, Yuanlin Xie
  • Patent number: 7883938
    Abstract: A method of manufacturing a plurality of stacked die semiconductor packages, including: attaching a second silicon wafer to a first silicon wafer, wherein the second silicon wafer has a plurality of open vias; attaching a third silicon wafer to the second silicon wafer, wherein the third silicon wafer has a plurality of open vias, and the open vias of the second and third silicon wafers are aligned with one another; etching a bonding material that attaches the wafers from the aligned open vias; filling the aligned open vias with a conductor; forming conductive bumps at open ends of the aligned open vias; back grinding the first silicon wafer; separating the stacked semiconductor dies from each other; attaching the bump end of the stacked semiconductor dies onto a substrate; encapsulating the stacked semiconductor dies and substrate; and singulating the encapsulated assembly.
    Type: Grant
    Filed: May 21, 2008
    Date of Patent: February 8, 2011
    Assignee: United Test and Assembly Center Ltd.
    Inventors: Ravi Kanth Kolan, Anthony Sun Yi Sheng, Liu Hao, Toh Chin Hock
  • Patent number: 7883939
    Abstract: A method for manufacturing a thin but robust stack of electrically connected thin film semiconductor elements includes the steps of forming a first element to be stacked: forming a separation layer and a semiconductor element layer over a substrate, forming a wiring connected to the semiconductor element layer, forming a protective material over the semiconductor layer and the wiring, forming a conductive region electrically connected to the wiring in the protective layer, and separating the semiconductor element layer from the substrate along the separation layer. A second element is formed according to the aforementioned process, and the first element is stacked thereon, before separating the second element from its substrate. The first element is bonded to the protective layer of the second element so that the semiconductor element layers of the first and the second element are electrically connected to each other through the protective layer, without damaging the protective layer.
    Type: Grant
    Filed: November 6, 2009
    Date of Patent: February 8, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Akihiro Chida
  • Patent number: 7883940
    Abstract: Method, algorithms, architectures, packages, circuits, and/or approaches for relatively low cost packaged integrated circuits (e.g., ball grid array or BGA packages) are disclosed. For example, a packaged integrated circuit can include a chip with a plurality of bond pads thereon; a plurality of bond pad connectors in electrical communication with the plurality of bond pads; a substrate having a plurality of layers, where at least one of the layers is configured to electrically connect a plurality of bond pad connectors and a plurality of external package connections; and a redistribution layer on the chip, where the redistribution layer is configured to electrically connect at least one of the bond pad connectors and at least one of the bond pads on the chip. Such an approach enables reductions in overall package costs. The RDL may complete an electrical path between one or more substrate traces and the corresponding bond pad(s) to avoid increasing the substrate layer count.
    Type: Grant
    Filed: June 25, 2007
    Date of Patent: February 8, 2011
    Assignee: Marvell International Ltd.
    Inventor: Randall D. Briggs
  • Patent number: 7883941
    Abstract: A method for fabricating a memory device is provided. A semiconductor layer is provided that includes first, second, third and fourth well regions of a first conductivity type in the semiconductor layer. A first gate structure overlies the first well region, a second gate structure overlies the second well region, a third gate structure overlies the third well region and is integral with the second gate structure, and a fourth gate structure overlies the fourth well region. Sidewall spacers are formed adjacent a first sidewall of the first gate structure and sidewalls of the second through fourth gate structures. In addition, an insulating spacer block is formed overlying a portion of the first well region and a portion of the first gate structure. The insulating spacer block is adjacent a second sidewall of the first gate structure.
    Type: Grant
    Filed: May 29, 2008
    Date of Patent: February 8, 2011
    Assignee: GlobalFoundries Inc.
    Inventor: Hyun-Jin Cho
  • Patent number: 7883942
    Abstract: Gate lines are formed on a substrate. A gate insulating layer, an intrinsic a-Si layer, an extrinsic a-Si layer, a lower film of Cr and an upper film of Al containing metal are sequentially deposited. A photoresist having thicker first portions on wire areas and thinner second portions on channel areas is formed on the upper film. The upper film on remaining areas are wet-etched, and the lower film and the a-Si layers on the remaining areas are dry-etched along with the second portions of the photoresist. The upper film, the lower film, and the extrinsic a-Si layer on the channel areas are removed. The removal of the upper film and the lower film on the channel areas are performed by wet etching, and the first portions of the photoresist are removed after the removal of the upper film on the channel areas.
    Type: Grant
    Filed: October 19, 2007
    Date of Patent: February 8, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Bum-Gee Baek, Kwon-Young Choi, Young-Joon Rhee, Bong-Joo Kang, Seung-Taek Lim, Hyang-Shik Kong, Won-Joo Kim
  • Patent number: 7883943
    Abstract: A method for manufacturing a thin film transistor and a display device using a small number of masks is provided. A conductive film is formed, a thin-film stack body having a pattern is formed over the conductive film, an opening portion is formed in the thin-film stack body so as to reach the conductive film, a gate electrode layer is formed by processing the conductive film using side-etching, and an insulating layer, a semiconductor layer, and a source and drain electrode layer are formed over the gate electrode layer, whereby a thin film transistor is manufactured. By provision of the opening portion, controllability of etching is improved.
    Type: Grant
    Filed: March 4, 2009
    Date of Patent: February 8, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hidekazu Miyairi, Takafumi Mizoguchi
  • Patent number: 7883944
    Abstract: A method of forming a semiconductor device is provided that may include providing a semiconductor layer including a raised source and raised drain region that are separated by a recessed channel having a thickness of less than 20 nm, and forming a spacer on a sidewall of the raised source and drain region overlying a portion of the recessed channel. In a following process step, a channel implantation is performed that produces a dopant spike of opposite conductivity as the raised source and drain regions. Thereafter, the offset spacer is removed, and gate structure including a metal gate conductor is formed overlying the recessed channel.
    Type: Grant
    Filed: March 19, 2009
    Date of Patent: February 8, 2011
    Assignee: International Business Machines Corporation
    Inventors: Huilong Zhu, Bruce B. Doris, Philip J. Oldiges
  • Patent number: 7883945
    Abstract: A method or manufacturing an array substrate at a low cost. Silicon patterns are formed. A first impurity is implanted at a high concentration. Gate metal patterns are formed. A second impurity is implanted. The first impurity is implanted at a low concentration. A pixel electrode is formed. The first impurity is simultaneously implanted into partial portions of the pixel pattern part, the storage pattern part, and the driving pattern part.
    Type: Grant
    Filed: August 8, 2007
    Date of Patent: February 8, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-Goo Jung, Hyun-Uk Oh
  • Patent number: 7883946
    Abstract: A method for forming a submicron device includes depositing a hard mask over a first region that includes a polysilicon well of a first dopant type and a gate of a second dopant type and a second region that includes a polysilicon well of a second dopant type and a gate of a first dopant type. The hard mask over the first region is removed. Angled implantation of the first dopant type is performed to form pockets under the gate of the second dopant type.
    Type: Grant
    Filed: May 8, 2008
    Date of Patent: February 8, 2011
    Assignee: Altera Corporation
    Inventors: Che Ta Hsu, Christopher J. Pass, Dale Ibbotson, Jeffrey T. Watt, Yanzhong Xu
  • Patent number: 7883947
    Abstract: Methods for fabricating and testing integrated circuit devices and systems. The integrated circuit device generally includes two semiconductor dies. The first die has little or no I/O or ESD protection, and the second die includes at least one exposed terminal in electrical communication with one or more terminals on the first die, at least one I/O circuit in electrical communication with one or more terminals on the second die, and at least one I/O terminal in electrical communication with the I/O circuit(s). The method of forming an integrated circuit includes aligning at least one of the exposed terminals on the first die with at least one of the exposed terminals on the second die, and forming at least one electrical junction between them such that the exposed terminal(s) on the first die is/are in electrical communication with an I/O circuit and an I/O terminal on the second die.
    Type: Grant
    Filed: August 17, 2010
    Date of Patent: February 8, 2011
    Assignee: Marvell International Ltd.
    Inventors: Chuan-Cheng Cheng, Choy Hing Li, Shiann-Ming Liou
  • Patent number: 7883948
    Abstract: Methods and structures for relieving stresses in stressed semiconductor liners. A stress liner that enhances performance of either an NFET or a PFET is deposited over a semiconductor to cover the NFET and PFET. A disposable layer is deposited to entirely cover the stress liner, NFET and PFET. This disposable layer is selectively recessed to expose only the single stress liner over a gate of the NFET or PFET that is not enhanced by such stress liner, and then this exposed liner is removed to expose a top of such gate. Remaining portions of the disposable layer are removed, thereby enhancing performance of either the NFET or PFET, while avoiding degradation of the NFET or PFET not enhanced by the stress liner. The single stress liner is a tensile stress liner for enhancing performance of the NFET, or it is a compressive stress liner for enhancing performance of the PFET.
    Type: Grant
    Filed: May 14, 2009
    Date of Patent: February 8, 2011
    Assignee: International Business Machines Corporation
    Inventors: Brian J. Greene, Rajesh Rengarajan
  • Patent number: 7883949
    Abstract: Methods of forming a p-channel MOS device in silicon carbide include forming an n-type well in a silicon carbide layer, and implanting p-type dopant ions to form a p-type region in the n-type well at a surface of the silicon carbide layer and at least partially defining a channel region in the n-type well adjacent the p-type region. A threshold adjustment region is formed in the channel region. The implanted ions are annealed in an inert atmosphere at a temperature greater than 1650° C. A gate oxide layer is formed on the channel region, and a gate is formed on the gate oxide layer. A silicon carbide-based transistor includes a silicon carbide layer, an n-type well in the silicon carbide layer, and a p-type region in the n-type well at a surface of the silicon carbide layer and at least partially defining a channel region in the n-type well adjacent the p-type region.
    Type: Grant
    Filed: April 26, 2007
    Date of Patent: February 8, 2011
    Assignee: Cree, Inc
    Inventors: Mrinal Kanti Das, Qingchun Zhang, Sei-Hyung Ryu
  • Patent number: 7883950
    Abstract: Disclosed is a method of manufacturing a semiconductor device. The method comprises consecutively depositing and patterning polysilicon and mask material on a substrate to form a polysilicon layer and a mask layer, reducing a width of the polysilicon layer, depositing and etching insulating material on the substrate to form a spacer on a lateral side of the polysilicon layer, and forming a source/drain region in the substrate at sides of the spacer.
    Type: Grant
    Filed: October 19, 2007
    Date of Patent: February 8, 2011
    Assignee: Dongbu Hitek Co., Ltd.
    Inventor: Ji Ho Hong
  • Patent number: 7883951
    Abstract: A semiconductor device and a method for forming it are described. The semiconductor device comprises a metal NMOS gate electrode that is formed on a first part of a substrate, and a silicide PMOS gate electrode that is formed on a second part of the substrate.
    Type: Grant
    Filed: November 2, 2006
    Date of Patent: February 8, 2011
    Assignee: Intel Corporation
    Inventors: Justin K. Brask, Mark L. Doczy, Jack Kavalieros, Matthew V. Metz, Chris E. Barns, Uday Shah, Suman Datta, Christopher D. Thomas, Robert S. Chau
  • Patent number: 7883952
    Abstract: A method of manufacturing a flash memory device that prevents generation of voids when forming an interlayer dielectric film. The method may include forming a gate on a semiconductor substrate, and then sequentially stacking a first dielectric film and a second dielectric film on the semiconductor substrate, and then forming a first spacer comprising a first dielectric film pattern and a second dielectric film pattern on sidewalls of the gate by performing a first etching process, and then forming source and drain areas in the semiconductor substrate, and then removing the second dielectric film, and then sequentially stacking a third dielectric film and a fourth dielectric film on the semiconductor substrate, and then forming a second spacer comprising the first dielectric pattern and a third dielectric pattern on the sidewalls of the gate by performing a second etching process, and then forming an interlayer dielectric film on the semiconductor substrate including the gate and the first spacer.
    Type: Grant
    Filed: June 26, 2008
    Date of Patent: February 8, 2011
    Assignee: Dongbu HiTek Co., Ltd.
    Inventor: Hyun-Ju Lim
  • Patent number: 7883953
    Abstract: A semiconductor process and apparatus includes forming <100> channel orientation CMOS transistors (24, 34) with enhanced hole mobility in the NMOS channel region and reduced channel defectivity in the PMOS region by depositing a first tensile etch stop layer (51) over the PMOS and NMOS gate structures, etching the tensile etch stop layer (51) to form tensile sidewall spacers (62) on the exposed gate sidewalls, and then depositing a second hydrogen rich compressive or neutral etch stop layer (72) over the NMOS and PMOS gate structures (26, 36) and the tensile sidewall spacers (62). In other embodiments, a first hydrogen-rich etch stop layer (81) is deposited and etched to form sidewall spacers (92) on the exposed gate sidewalls, and then a second tensile etch stop layer (94) is deposited over the NMOS and PMOS gate structures (26, 36) and the sidewall spacers (92).
    Type: Grant
    Filed: September 30, 2008
    Date of Patent: February 8, 2011
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Da Zhang, Voon-Yew Thean, Christopher V. Baiocco, Jie Chen, Weipeng Li, Young Way Teh, Jin Wallner
  • Patent number: 7883954
    Abstract: The illumination system has a light source (1) with a plurality of light emitters (R, G, B). The light emitters comprise at least a first light-emitting diode of a first primary color and at least a second light-emitting diode of a second primary color, the first and the second primary colors being distinct from each other. The illumination system has a facetted light-collimator (2) for collimating light emitted by the light emitters. The facetted lightcollimator is arranged along a longitudinal axis (25) of the illumination system. Light propagation in the facetted light-collimator is based on total internal reflection or on reflection at a reflective coating provided on the facets of the facetted light-collimator. The facetted light-collimator merges into a facetted light-reflector (3) at a side facing away from the light source. The illumination system further comprises a light-shaping diffuser (17). The illumination system emits light with a uniform spatial and spatio-angular color distribution.
    Type: Grant
    Filed: August 19, 2005
    Date of Patent: February 8, 2011
    Assignee: NXP B.V.
    Inventors: Peter Magnee, Wibo Van Noort, Johannes Donkers
  • Patent number: 7883955
    Abstract: A semiconductor device has a thicker gate dielectric layer (gate-insulation film 16 of, e.g., 40 nm) for a high voltage PMOS transistor (Tr1) that is formed simultaneously in a first thermal oxidation process together with the formation of LOCOS isolation structures (3) for element seaaration of low voltage PMOS and NMOS transistors (Tr3, Tr4), and has a thinner gate dielectric layer (gate-insulation film 25 of, e.g., 7 nm) for a high voltage NMOS transistor (Tr2) that is formed simultaneously in a second thermal oxidation process together with the formation of gate dielectric layers (gate-insulation films 33, 42) of low voltage PMOS and NMOS transistors (Tr3, Tr4).
    Type: Grant
    Filed: April 6, 2010
    Date of Patent: February 8, 2011
    Assignee: Texas Instruments Incorporated
    Inventor: Yoichi Okumura
  • Patent number: 7883956
    Abstract: Methods of forming coplanar active regions and isolation regions and structures thereof are disclosed. One embodiment includes shallow-trench-isolation (STI) formation in a semiconductor-on-insulator (SOI) layer on a substrate of a semiconductor structure; and bonding a handle wafer to the STI and SOI layer to form an intermediate structure. The intermediate structure may have a single layer including at least one STI region and at least one SOI region therein disposed between the damaged substrate and the handle wafer. The method may also include cleaving the hydrogen implanted substrate and removing any residual substrate to expose a surface of the at least one STI region and a surface of the at least one SOI region. The exposed surface of the at least one STI region forms an isolation region and the exposed surface of the at least one SOI region forms an active region, which are coplanar to each other.
    Type: Grant
    Filed: February 15, 2008
    Date of Patent: February 8, 2011
    Assignee: International Business Machines Corporation
    Inventor: Huilong Zhu
  • Patent number: 7883957
    Abstract: Provided is an image sensor and a method for manufacturing the same. In the image sensor, a first substrate has a lower metal line and circuitry thereon. A crystalline semiconductor layer contacts the lower metal line and is bonded to the first substrate. A photodiode is provided in the crystalline semiconductor layer and electrically connected with the lower metal line. A pixel isolation layer is formed in regions of the photodiode.
    Type: Grant
    Filed: September 5, 2008
    Date of Patent: February 8, 2011
    Assignee: Dongbu Hitek Co., Ltd.
    Inventor: Joon Hwang
  • Patent number: 7883958
    Abstract: A phase change memory device that has a diode with an enlarged, i.e., bulging, PN interfacial junction and a corresponding fabrication method are presented. The phase change memory device includes a semiconductor substrate, an insulation layer, a diode, and a phase change memory cell. The insulation layer is placed on the semiconductor substrate and has a contact hole which is wider in a middle portion than the lower and upper portions of the contact hole. The diode is formed within the contact hole and PN interfacial junction at the wider middle portion of the diode within the contact hole. The phase change memory cell is formed on top of the diode.
    Type: Grant
    Filed: April 30, 2009
    Date of Patent: February 8, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventor: Nam Kyun Park
  • Patent number: 7883959
    Abstract: The invention includes methods of forming electrically conductive material between line constructions associated with a peripheral region or a pitch region of a semiconductor substrate. The electrically conductive material can be incorporated into an electrically-grounded shield, and/or can be configured to create a magnetic field bias. Also, the conductive material can have electrically isolated segments that are utilized as electrical jumpers for connecting circuit elements. The invention also includes semiconductor constructions comprising the electrically conductive material between line constructions associated with one or both of the pitch region and the peripheral region.
    Type: Grant
    Filed: August 12, 2010
    Date of Patent: February 8, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Mark Fischer, Terrence B. McDaniel
  • Patent number: 7883960
    Abstract: A method of manufacturing a semiconductor device includes forming a conductive layer over a semiconductor substrate, selectively removing the conductive layer for forming a resistance element and a gate electrode, forming sidewall spacers over sidewalls of the remaining conductive layer, forming a first insulating film containing a nitrogen over the semiconductor substrate having the sidewall spacers, implanting ions in the semiconductor substrate through the first insulating film, forming a second insulating film containing a nitrogen over the first insulating film after implanting ions in the semiconductor substrate through the first insulating film, and selectively removing the first and the second insulating film such that at least a part of the first and the second insulating films is remained over the semiconductor substrate and over the conductive layer.
    Type: Grant
    Filed: March 24, 2009
    Date of Patent: February 8, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Masatoshi Fukuda, Akiyoshi Hatada, Katsuaki Ookoshi, Kenichi Okabe, Tomonari Yamamoto
  • Patent number: 7883961
    Abstract: A manufacturing method for a ferroelectric memory device including: forming a lower electrode; forming an electrode oxide film composed of an oxide of a constituent material of the lower electrode; forming a first ferroelectric layer on the lower electrode by reaction between organometallic source material gas and oxygen gas; forming a second ferroelectric layer on the first ferroelectric layer by reaction between organometallic source material gas and oxygen gas; and forming an upper electrode on the second ferroelectric layer. In the method, the oxygen gas in the forming of the first ferroelectric layer is in an amount less than the amount of oxygen necessary for reaction of the organometallic source material gas. In the method, the oxygen gas in the forming of the second ferroelectric layer is in an amount greater than the amount of oxygen necessary for reaction of the organometallic source material gas.
    Type: Grant
    Filed: November 28, 2007
    Date of Patent: February 8, 2011
    Assignees: Seiko Epson Corporation, Fujitsu Semiconductor Limited
    Inventors: Hiroaki Tamura, Masaki Kurasawa, Hideki Yamawaki
  • Patent number: 7883962
    Abstract: A DRAM array having trench capacitor cells of potentially 4F2 surface area (F being the photolithographic minimum feature width), and a process for fabricating such an array. The array has a cross-point cell layout in which a memory cell is located at the intersection of each bit line and each word line. Each cell in the array has a vertical device such as a transistor, with the source, drain, and channel regions of the transistor being formed from epitaxially grown single crystal silicon. The vertical transistor is formed above the trench capacitor.
    Type: Grant
    Filed: August 2, 2010
    Date of Patent: February 8, 2011
    Assignee: Micron Technology, Inc.
    Inventor: Wendell P. Noble
  • Patent number: 7883963
    Abstract: Memory cells containing two split sub-lithographic charge storage nodes on a semiconductor substrate and methods for making the memory cells are provided. The methods can involve forming two split sub-lithographic charge storage nodes by using spacer formation techniques. By removing an exposed portion of a fist poly layer between sloping side surfaces or outer surfaces of spacers while leaving portions of the first poly layer protected by the spacers, the method can provide two split sub-lithographic first poly gates. Further, by removing an exposed portion of a charge storage layer between sloping side surfaces or outer surfaces of spacers, the method can provide two split, narrow portions of the charge storage layer, which subsequently form two split sub-lithographic charge storage nodes.
    Type: Grant
    Filed: October 25, 2007
    Date of Patent: February 8, 2011
    Assignee: Spansion LLC
    Inventors: Minghao Shen, Chungho Lee, Hiroyuki Kinoshita, Huaqiang Wu
  • Patent number: 7883964
    Abstract: A nonvolatile semiconductor memory includes: a device region and a device isolating region, which have a pattern with a striped form that extends in a first direction, and are alternately and sequentially disposed at a first pitch in a second direction that is perpendicular to the first direction; and a contact made of a first conductive material, which is connected to the device region and disposed at the first pitch in the second direction. On a cross section of the second direction, the bottom width of the contact is longer than the top width of the contact, and the bottom width is longer than the width of the device region.
    Type: Grant
    Filed: July 29, 2008
    Date of Patent: February 8, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akira Goda, Hiroyuki Nitta
  • Patent number: 7883965
    Abstract: A semiconductor device includes a device isolation structure, a recess channel structure, and a gate electrode. The device isolation structure is formed in a semiconductor substrate to define an active region. The recess channel structure is disposed in the semiconductor substrate under the active region. The gate electrode includes a holding layer disposed in a gate region to fill the recess channel structure. The holding layer prevents a seam and a shift of the seam occurring in the recess channel structure.
    Type: Grant
    Filed: December 30, 2006
    Date of Patent: February 8, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Shin Gyu Choi, Seung Chul Oh
  • Patent number: 7883966
    Abstract: A split gate (flash) EEPROM cell and a method for manufacturing the same is disclosed, in which a control gate and a floating gate are formed in a vertical structure, to minimize a size of the cell, to obtain a high coupling ratio, and to lower a programming voltage. The split gate EEPROM cell includes a semiconductor substrate having a trench; a tunneling oxide layer at sidewalls of the trench; a floating gate, a dielectric layer and a control gate in sequence on the tunneling oxide layer; a buffer dielectric layer at sidewalls of the floating gate and the control gate; a source junction in the semiconductor substrate at the bottom surface of the trench; a source electrode in the trench between opposing buffer dielectric layers, electrically connected to the source junction; and a drain junction on the surface of the semiconductor substrate outside the trench.
    Type: Grant
    Filed: August 27, 2009
    Date of Patent: February 8, 2011
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Heung Jin Kim
  • Patent number: 7883967
    Abstract: A nonvolatile semiconductor memory device includes a gate portion formed by laminating a tunnel insulating film, floating gate electrode, inter-poly insulating film and control gate electrode on a semiconductor substrate, and source and drain regions formed on the substrate. The tunnel insulating film has a three-layered structure having a silicon nitride film sandwiched between silicon oxide films. The silicon nitride film is continuous in an in-plane direction and has 3-coordinate nitrogen bonds and at least one of second neighboring atoms of nitrogen is nitrogen.
    Type: Grant
    Filed: July 24, 2006
    Date of Patent: February 8, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yuuichiro Mitani, Daisuke Matsushita, Ryuji Ooba, Isao Kamioka, Yoshio Ozawa
  • Patent number: 7883968
    Abstract: The present invention is an object to provide a high-performance vertical field effect transistor having a microminiaturized structure in which the distance between the gate and the channel is made short not through a microfabrication process, having a large gate capacitance, and so elaborated that the gate can control the channel current with a low voltage, and a method for simply and efficiently manufacturing such a field effect transistor not through a complex process such as a microfabrication process.
    Type: Grant
    Filed: February 19, 2010
    Date of Patent: February 8, 2011
    Assignee: Fujitsu Limited
    Inventor: Mizuhisa Nihei
  • Patent number: 7883969
    Abstract: Unit cells of metal oxide semiconductor (MOS) transistors are provided having an integrated circuit substrate and a MOS transistor on the integrated circuit substrate. The MOS transistor includes a source region, a drain region and a gate. The gate is between the source region and the drain region. A channel region is provided between the source and drain regions. The channel region has a recessed region that is lower than bottom surfaces of the source and drain regions. Related methods of fabricating transistors are also provided.
    Type: Grant
    Filed: April 21, 2008
    Date of Patent: February 8, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chang-Woo Oh, Dong-Gun Park, Sung-Young Lee, Chang-Sub Lee, Jeong-Dong Choe
  • Patent number: 7883970
    Abstract: A semiconductor device having a decoupling capacitor and a method of fabricating the same are provided. The semiconductor device includes a semiconductor substrate having a cell region, a first peripheral circuit region, and a second peripheral circuit region. At least one channel trench is disposed in the cell region of the semiconductor substrate. At least one first capacitor trench is disposed in the first peripheral circuit region of the semiconductor substrate, and at least one second capacitor trench is disposed in the second peripheral circuit region of the semiconductor substrate. A gate electrode is disposed in the cell region of the semiconductor substrate and fills the channel trench. A first upper electrode is disposed in the first peripheral circuit region of the semiconductor substrate and fills at least the first capacitor trench. A second upper electrode is disposed in the second peripheral circuit region of the semiconductor substrate and fills at least the second capacitor trench.
    Type: Grant
    Filed: December 23, 2008
    Date of Patent: February 8, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyun-Ki Kim, Jung-Hwa Lee, Ji-Young Kim
  • Patent number: 7883971
    Abstract: Disclosed are a gate structure in a trench region of a semiconductor device and a method for manufacturing the same. The semiconductor device includes a pair of drift regions formed in a semiconductor substrate; a trench region formed between the pair of drift regions; an oxide layer spacer on sidewalls of the trench region; a gate formed in the trench region; and a source and a drain formed in the pair of the drift regions, respectively.
    Type: Grant
    Filed: April 28, 2009
    Date of Patent: February 8, 2011
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Kwang Young Ko
  • Patent number: 7883972
    Abstract: A semiconductor device may include a fin structure having source/drain regions and channel fins connected between source/drain patterns. A gate insulation layer may be provided on the channel fins. A gate electrode may include lower gate patterns and an upper gate pattern. The lower gate patterns may extend in a vertical direction and contact the gate insulation layer. The upper gate pattern may extend in a second horizontal direction substantially perpendicular to the first horizontal direction. The upper gate pattern may be connected to upper portions of the lower gate patterns.
    Type: Grant
    Filed: July 31, 2008
    Date of Patent: February 8, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-Man Yoon, Choong-Ho Lee, Chul Lee, Dong-Gun Park
  • Patent number: 7883973
    Abstract: A method is provided of forming a semiconductor device. A substrate is provided having a dielectric layer formed thereover. The dielectric layer covers a protected region of the substrate, and has a first opening exposing a first unprotected region of the substrate. A first dopant is implanted into the first unprotected region through the first opening in the dielectric layer, and into the protected region through the dielectric layer.
    Type: Grant
    Filed: December 16, 2008
    Date of Patent: February 8, 2011
    Assignee: Texas Instruments Incorporated
    Inventors: Seetharaman Sridar, Marie Denison, Sameer Pendharkar