Abstract: Apparatus, method and program product may detect an attempt to tamper with a microchip by detecting an unacceptable alteration in a measured capacitance associated with capacitance structures proximate the backside of a microchip. The capacitance structures typically include metallic shapes and may connect using through-silicon vias to active sensing circuitry within the microchip. In response to the sensed change, a shutdown, spoofing, self-destruct or other defensive action may be initiated to protect security sensitive circuitry of the microchip.

Abstract: A cathodic protection monitor to be electrically connected to a cathodic protection rectifier that is adapted to prevent rust, corrosion and possible leakage in an underground pipe or storage tank above which the rectifier is supported. The cathodic protection monitor includes a CPU that reads, digitizes and stores analog current and voltage signals which are supplied from the DC output of the rectifier and are indicative of the effectiveness thereof. The monitor includes an ISM band transceiver and antenna by which the CPU is polled and from which packets of stored data are transmitted to a data collector at an overhead airplane or nearby motor vehicle for retransmission and analysis by the pipe owner or maintenance crew.

Abstract: A stiffener assembly for use with testing devices is provided herein. In some embodiments, a stiffener assembly for use with testing devices can be part of a probe card assembly that can include a stiffener assembly comprising an upper stiffener coupled to a plurality of lower stiffeners; and a substrate constrained between the upper stiffener and the plurality of lower stiffeners, the stiffener assembly restricting non-planar flex of the substrate while facilitating radial movement of the substrate with respect to the stiffener assembly.

Abstract: An interposer may include a first base, at least one first signal line in the first base, and at least one first ground line in the first base, wherein the ground line surrounds the at least one first signal line. The at least one first signal line and the at least one first ground line may be exposed through an upper surface of the first base. The at least one first signal line may be configured to conduct a test current through the first base. An interposer may also include a second base below the first base and may include a printed circuit board between the first base and the second base. A probe card may include a multilayer substrate having at least one contact needle, a coaxial board having at least one coaxial signal cable and the above described interposer between the multilayer substrate and the coaxial board.

Abstract: Multi-touchdown, parallel test probe cards having probe elements arranged to provide greater efficiency during testing of a substrate having a plurality of die thereon. Probe elements may be arranged in a number of configurations that allow for efficient usage of the probe elements.

Abstract: An IC device (10) held on an IC carrier (24) is a double-sided electrode type BGA IC device (10) provided with bump electrodes (14) on a first surface of a package. The IC device has, on a second surface opposite the first surface, (a) a central protrusion (30), (b) a peripheral portion (32) lower than the protrusion by one step, and (c) upper electrodes (18) formed on the peripheral portion of the IC device. The IC carrier is provided with a frame (36), a cover (40), and a holding means (42). The frame forms a device reception space (38) for receiving the IC device. The cover can cover the upper electrodes while in contact with the periphery of the IC device held on the IC carrier. The holding means can hold the IC device on the IC carrier with the cover covering the upper electrodes of the IC device. The IC device can be set in an IC socket while being mounted on the IC carrier.

Abstract: A parking-structure test system has motherboards that test memory modules. The motherboards are not stationary but are placed inside movable trays that move along conveyors. An unloader removes tested memory modules from test sockets on the motherboards, and a loader inserts untested memory modules into the motherboards using a robotic arm. A conveyor carries the motherboards from the loader to a parking and testing structure. An elevator raises or lowers the motherboards to different parking levels in the parking and testing structure. The motherboards move from the elevator to test stations on the parking level. A retractable connector from the test station makes contact with a motherboard connector to power up the motherboard, which then tests the memory modules. Test results are communicated from the test station to a host controller, which instructs the loader-unloader to sort the tested memory modules once the motherboard returns via the elevator and conveyors.

Abstract: In a semiconductor inspecting device having a contact to be electrically connected to an electrode pad formed in a semiconductor device which is an object to be measured, and a substrate provided with the contact, the contact is provided obliquely to a main surface of the substrate.

Abstract: Various apparatus and methods of testing a semiconductor chip for soft defects are disclosed. In one aspect, a method of testing a semiconductor chip that has a surface and plural circuit structures positioned beneath the surface is provided. An external stimulus is applied to a series of fractional portions of the surface to perturb portions of the plural circuit structures such that at least one of the series of fractional portions is smaller than another of the series of fractional portions. The semiconductor chip is caused to perform a test pattern during the application of external stimulus to each of the fractional portions to determine if a soft defect exists in any of the series of fractional portions.

Abstract: An improved interconnection system and method is described, such as for connectors, socket assemblies and/or probe card systems. An exemplary system comprises a probe card interface assembly (PCIA) for establishing electrical connections to a semiconductor wafer mounted in a prober. The PCIA comprises a motherboard parallel to the semiconductor wafer having an upper surface and an opposing lower planar mounting surface, a reference plane defined by a least three points located between the lower surface of the motherboard and the wafer, at least one component located below the motherboard mounting surface, and a mechanism for adjusting the planarity of the reference plane with respect to the wafer. A probe chip having a plurality of spring probes extending there from is mountable and demountable from the PCIA, without the need for further planarity adjustment. The interconnection structures and methods preferably provide improved fabrication cycles.

Abstract: An integrated circuit includes N configurable cells each including one functional input, one output, one propagation input and one output. The circuit includes a functional mode in which the N configurable cells are coupled by their functional input and their output to logic blocks with which they cooperate to form at least one logic circuit. The disclosed circuit also includes a test mode in which the N configurable cells are coupled by their propagation input and their output to the logic blocks and in which the output of the Nth configurable cell is coupled to a functional input of the first logic block to form an oscillator.

Abstract: A method for single event transient filtering in an integrated circuit device is described. The device comprises three sequential elements, each having a data input and a data output with each of the three data outputs coupled to one of three inputs of a voting gate. The method comprises generating first and second nominally equivalent logic signals in first and second SET domains, converting the first and second nominally equivalent logic signals into first, second and third nominally equivalent data channels, and transmitting the first, second and third nominally equivalent data channels to the data inputs of the first, second and third sequential elements.

Abstract: A calibration circuit is capable of correcting an error of a calibration operation by adjusting a calibration code generated thereby. The calibration circuit of a semiconductor memory device includes a code generator, a calibration resistor unit, and a variable resistor unit. The code generator is configured to generate a calibration code for determining a termination resistance in response to a voltage of a first node and a reference voltage. The calibration resistor unit, which has internal resistors turned on/off in response to the calibration code, is connected to the first node. The variable resistor unit is connected in parallel with the calibration resistor unit and has a resistance that varies with a setting value.

Abstract: An on-chip termination (OCT) calibration circuit includes one or more transistors coupled between a first terminal and a supply voltage, one or more transistors coupled between the first terminal and a low voltage, and a feedback loop circuit. The feedback loop circuit compares a signal from the first terminal to first and second reference signals to generate a first calibration code that controls conductive states of the one or more transistors coupled between the first terminal and the supply voltage and a second calibration code that controls conductive states of the one or more transistors coupled between the first terminal and the low voltage. The OCT calibration circuit controls an on-chip termination impedance at a pin using the first calibration code and the second calibration code.

Abstract: An apparatus and system are provided to adjust an output voltage of an integrated circuit (IC) die. For instance, the apparatus can include an on-chip source termination and a bias generator. The bias generator can be configured to provide a source current to the on-chip source termination to adjust the output voltage. In particular, when adjusting the output voltage of the IC die, the bias generator can adjust the source current using a first current with a first adjustable current gain and a second current source with a second adjustable current gain.

Abstract: A programmable logic device (PLD) with a plurality of programmable regions is disclosed. Some of the programmable regions have switch power or ground supplies to allow them to be put into a low-power state in one or more low-power modes. At least one of the programmable regions always remains on during the low-power modes to enable the user to design custom PLD power management logic that may be placed in the always-on programmable region.

Abstract: This invention is an integrated circuit having at least one data pin connecting to external circuits. The invention includes a plurality of operational units each having at least one data input/output for data transfer and an enable input. The operational unit have a normal mode and a stall mode controlled by an enable input. The operational units can exchange data via the data input/output in normal mode and are not capable of exchanging data in the stall mode. A selection logic selectively enables an operation unit and connects the data input/output of the enabled operation unit to the at least one data pin. The selection logic is responsive to external signals on at least one data pin to selectively enable operation units.

Abstract: A system LSI includes an input/output section and a logic circuit section. The input/output section includes an I/O power source cell having a supply voltage higher than a power source for the logic circuit section and a plurality of I/O cells in each of which an I/O power source line is provided for supplying source power from the I/O power source cell. The logic circuit section includes an I/O power consuming circuit which uses the I/O power source cell as a power source. The I/O power consuming circuit is connected to a line leading from an I/O power source line in at least one of the plurality of I/O cells.

Abstract: A voltage level shifting circuit for an integrated circuit system having an internal low voltage power supply (VCCL) and an external high voltage power supply (VCCH) is disclosed, the voltage level shifting circuit comprises a pair of cross coupled PMOS transistors connected to the VCCH, a NMOS transistor with a source connected to a ground (VSS) and a gate connected to a first signal swinging between the VCCL and the VSS, and a switching device coupled between a drain of one of the pair of PMOS transistors and a drain of the NMOS transistor, wherein the pair of PMOS transistors are high voltage transistors and the switching device is off when the VCCL is below a predetermined voltage level, and the switching device is on when the VCCL is above the predetermined voltage level.

Abstract: A level shifter circuit includes first and second transistors that receive a first input signal at control inputs. A level shifted output signal is generated by the first and the second transistors. Third and fourth transistors receive a second input signal at control inputs. The first input signal is an inverse of the second input signal. A first multiplexer circuit is configurable to couple a control input of a fifth transistor to the first and the second transistors. A second multiplexer circuit is configurable to couple a control input of a sixth transistor to the third and the fourth transistors.

Abstract: In a particular embodiment, a method includes receiving an input voltage at an input to a level shifting circuit that includes voltage pull-up logic. The method includes providing an output signal from the level shifting circuit. The method also includes selectively activating the voltage pull-up logic circuit of the level shifting circuit.

Abstract: A voltage level shifting circuit may include a differential first-stage level shifter that receives a binary input signal and generates a non-inverted first-stage shifted output signal and an inverted first-stage shifted output signal, a second-stage level shifter that receives the first-stage shifted output signals and generates a non-inverted second-stage shifted output signal and an inverted second-stage shifted output signal, and a signal generator that generates a level shifted final output signal corresponding to the binary input signal that is based on the non-inverted second-stage shifted output signal and the inverted second-stage shifted output signal. The voltage swing of the first stage output signals may be limited to swing between a non-zero lower value and an upper value that is less than or equal to a source-to-drain voltage rating of transistors in the differential first-stage level shifter.

Abstract: There is provided an output driver, which includes a pre-driver configured to generate a main driving control signal in response to a data signal, a main driver configured to drive an output terminal in response to the main driving control signal, an auxiliary driving control signal generator configured to generate an auxiliary driving control signal having an activation interval corresponding to the data signal and an interval control signal, and an auxiliary driver configured to drive the output terminal in response to the auxiliary driving control signal.

Abstract: The invention relates to an interfacing device for pseudo-differential transmission through interconnections used for sending a plurality of electrical signals. The interfacing device of the invention includes signal terminals and a common terminal. A transmitting circuit receives the input signals of the transmitting circuit coming from a source. The output of the transmitting circuit delivers, when the transmitting circuit is in the activated state, voltages between one of the signal terminals and the reference terminal (ground). A receiving circuit delivers, when the receiving circuit is in the activated state, output signals of the receiving circuit determined each by the voltage between one of the signal terminals and the common terminal, to the destination. In the closed state, the common terminal switching circuit is, for the common terminal, equivalent to a voltage source delivering a constant voltage, connected in series with a passive two-terminal circuit element presenting a low impedance.

Abstract: Techniques in which an optimal set of clock gating elements is determined for a selected circuit design. Those clock gating elements are coupled to selected flip-flops, with the effect that those selected flip-flops will consume less dynamic power during operation of the logic circuit. The selected set of clock gating elements provides an optimal savings in overall power consumption after modification of that selected circuit design.

Abstract: A digital compensation of an input stage of a comparator may be achieved by providing switched load elements, which may be appropriately connected to the differential input pair of the comparator in order to match transistor characteristics of the input pair and also match the load value of the input stage. Thus, enhanced offset behavior may be accomplished without providing an external signal and/or without requiring complex reference voltages/currents.

Abstract: An electronic device compares a first voltage with a selected first reference voltage or second reference voltage. The electronic device includes a comparator having a first input receiving the first voltage, a second input receiving the selected reference voltage and an output providing an output signal based on a comparison. A control stage connected to the output of the comparator generates a control signal based on the output of the comparator. The electronic device selects either the first reference voltage or the second reference voltage in response to the control signal thus comparing the first voltage with the selected reference voltage.

Abstract: A pulse signal generating device includes: the plurality of encoders each of which outputs an encoder signal with a pulse period corresponding to the speed of an object to be detected; delay amount control unit that controls a relative delay amount with respect to a pulse signal for each of the plurality of pulse output signals output from the plurality of encoders; a detection unit that individually detects abnormalities in pulses of the plurality of encoder signals; a switching unit that performs switching to one pulse output signal, in which pulse abnormalities are not detected, of the plurality of pulse output signals; and a pulse generating unit that generates a pulse signal by delaying the one pulse output signal switched by the switching unit by the corresponding relative delay amount.

Abstract: A source driver includes four output switches, two resistors, and a charge-sharing switch. The first output switch and the first resistor are coupled in series to a first output channel of the source driver. The second output switch and the second resistor are coupled in series to a second output channel of the source driver. The third output switch is coupled in parallel to the first output switch. The fourth output switch is coupled in parallel to the second output switch. The charge-sharing switch is coupled between the first resistor and the second resistor. The third output switch and the fourth output switch are controlled to adjust the resistance of the output current path of the source driver.

Abstract: A circuit arrangement (10) for driving an electrical load (2) comprises an input (11) for feeding a power-supply voltage (Vs) with an AC component and an output (13) for providing an output signal (Sout) for driving a connectable electrical load (2). The circuit arrangement (10) further comprises a frequency processing circuit (20) for proving a reference frequency (f1) as a function of the AC component, and a demodulator (60) with a first input (61) for feeding the reference frequency (f1), with a second input (62) that is coupled to the input (11) of the circuit arrangement (10), and with an output (63) that is coupled to the output (13) of the circuit arrangement (10).

Abstract: Control circuitry, comprising: first control means operable to generate a first control signal, the first control signal being indicative of a relationship between an output signal and a first reference signal, and to generate said output signal in dependence upon said first control signal, the first control means being configured to tend to maintain a first desired relationship between the output signal and the first reference signal in response to said first control signal; and second control means configured to influence operation of said first control means in response to said first control signal by way of a second control signal so as to tend to maintain a second desired relationship between said first control signal and a second reference signal.

Abstract: A phase locked loop (PLL) includes a frequency detector and a type 1 PLL including a phase detector. The phase detector produces a phase error signal indicative of a difference in phase between a reference signal and a feedback signal, while the frequency detector produces a frequency error signal indicative of a difference in frequency between the reference signal and the feedback signal. Logic switches between the phase detector and the frequency detector based on the frequency error signal.

Abstract: Provided is an oscillation frequency control circuit for correcting its frequency, keeping the oscillation frequency stable when self-oscillating, and oscillating with a control voltage generated by making a fixed voltage given from outside variable. In the oscillation frequency control circuit, a CPU selects/outputs the control voltage preferentially according to a command of a control voltage selection. If the command is not given and the level of an outside reference signal detected by a detecting circuit is within an adequate range, it turns a select switch on. If the command is not given and the level of the outside reference signal is out of the adequate range, it turns the select switch off and outputs information about pulse generation stored in a memory to a PWM circuit.

Abstract: Circuits for forming the inputs of a latch are provided. In some embodiments, circuits for forming inputs of a latch comprise: a first transistor having a first gate terminal, a first drain terminal, a first source terminal, a first gate length, and a first common mode level at the first gate terminal, wherein the first gate terminal provides a data input to the latch; and a second transistor having a second gate terminal, a second drain terminal, a second source terminal, a second gate length, and a second common mode level at the second gate terminal, wherein the second gate terminal provides a clock input to the latch, the second drain terminal is coupled to the first source terminal, and the first gate length and the second gate length are sized so that the first common model level and the second common mode level are substantially equal.

Abstract: A phase mixer includes a phase mixing unit configured to mix a phase of a first input signal and a phase of a second input signal in response to a phase control signal and output a phase mixed signal whose phase is varied by one or more units of a unit phase value, and a phase value adjusting unit configured to control an operation of the phrase mixing unit so that the unit phase value is adjusted in response to a code signal coding at least one of a process, voltage, or temperature (PVT) variation.

Abstract: A programmable delay element, variable-length delay chain, and ring oscillator are disclosed. The programmable delay element performs phase interpolation of input signals in response to a control signal and can be used in combination with other delay elements to create a highly-modular, variable-length delay chain or ring oscillator. The ring oscillator can be used as part of a digitally-controlled oscillator (DCO) in a digital clock synthesizer to adjust the frequency and phase of a clock signal by fractional unit delay steps. Within the variable-length delay chain, some programmable delay elements can be configured to scale the delay-step of other programmable delay elements so that a plurality of step sizes can be implemented with identical delay elements. Also, variations of the delay chain generate in-phase and quadrature phase (I/Q) signals in either an end-tap or center-tap configuration.

Abstract: A clock generating circuit generates a high frequency clock having a constant duty and the same period as that of an external clock. A clock generating circuit generates a clock signal (hereinafter “the clock”) used for outputting a data signal to a data pin. The clock generating circuit includes at least a dividing portion and a clock generating portion. A dividing portion divides an internal clock signal (hereinafter “the internal clock”) generated based on an external clock signal (hereinafter “the external clock”) and outputs a plurality of divided clock signals (hereinafter “the divided clocks”). The clock generating portion performs a predetermined logical operations combining the divided clocks to generate the clock having a constant duty and the same period as the external clock.

Abstract: A multi-channel integrator includes a first switch, a second switch, and a plurality of integration units. First terminals of the first and second switches receive a first reference voltage. Each of the integration units includes an operational amplifier (OP-AMP), a feedback switch, a third switch, a fourth switch, and a feedback capacitor. A second input terminal of the OP-AMP receives a second reference voltage. Two terminals of the feedback switch are respectively coupled to a first input terminal and an output terminal of the OP-AMP. First terminals of the third switch and the fourth switch are respectively coupled to the first input terminal and the output terminal of the OP-AMP. A first terminal of the feedback capacitor is coupled to the second terminals of the first and the third switches. A second terminal of the feedback capacitor is coupled to the second terminals of the second and the fourth switches.

Abstract: Conventional diode rectifiers usually suffer from a higher conduction loss. The present invention discloses a gate-controlled rectifier, which comprises a line voltage polarity detection circuit, a constant voltage source, a driving circuit and a gate-controlled transistor. The line voltage polarity detection circuit detects the polarity of the line voltage and controls the driving circuit to turn on or turn off the gate-controlled transistor. The gate-controlled transistor may be a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) with a gate, a source and a drain or an Insulated Gate Bipolar Transistor (IGBT) with a gate, an emitter and a collector. The constant voltage source is provided or induced by external circuits and referred to the source of the MOSFET or the emitter of the IGBT. Thanks to a lower conduction loss, this gate-controlled rectifier can be applied to rectification circuits to increase the rectification efficiency.

Abstract: An input device including an electrode a width dimension of which changes in its direction of extension, an output portion an output signal of which corresponds to an electrostatic capacity induced between the electrode and an electrically charged body when the body approaches or touches the electrode, a detecting portion to detect a change of an output signal value of the output portion, and an operation recognizing portion configured to recognize, on the basis of the detected change of the output signal value, one of a pressing operation and a sliding operation of the body performed with respect to the electrode, wherein the pressing operation is performed by a moving action of the body in which the body approaches or touches the electrode, while the sliding operation is performed by a sliding action of the body in the direction of extension of the electrode while the body is held in close proximity to or in touch with the electrode.

Abstract: A charge pump circuit generates a desired output voltage by stepping up an input voltage. An LCD driver IC and an electronic appliance are provided with the charge pump circuit.

Abstract: A method and apparatus is provided for reducing interference in circuits. A management strategy is provided to reduce reference spurs and interference in circuits. The management strategy uses a combination of one or more techniques which reduce the digital current, minimize mutual inductance, utilize field cancellation, prevent leakage current, and/or manage impedance. These techniques may be used alone, or preferably, used on combination with one another.

Abstract: A linear power amplifier system using pulse area modulation includes: an envelop/phase decomposer for decomposing an input signal into an envelop signal and a phase signal; a pulse area modulator for modulating the envelop signal such that an area of the modulated envelop signal is proportional to an amplitude of the envelop signal; a control signal generator for converting the modulated envelop signal into a control signal; an automatic gain adjuster for equalizing pulse height of the modulated envelop signal; a mixer for mixing the phase signal with the output of the automatic gain adjustor to produce a RF pulse train; a power amplifier for amplifying the RF pulse train, to generate an amplified RF pulse train; and a band pass filter for restoring the original input signal from the amplified RF pulse train. The output level of the power amplifier is controlled by the control signal.

Abstract: The present invention relates to an integrated Doherty type amplifier arrangement and an amplifying method for such an arrangement, wherein a lumped element hybrid power divider (12) is provided for splitting input signals of main and peak amplifier stages (20, 30, 40) at predetermined phase shifts and non-equal division rates and at least one wideband lumped element artificial line (Z 1, Z2) combined with wideband compensation circuit for receiving said first amplified signal and for applying said predetermined phase shift to said first amplified signal and its higher harmonics. Thereby, the low gain of the peak amplifier is compensated by providing the non-equal power splitting at the input. Moreover, the use of the lumped element hybrid power divider leads to an improved isolation between the input ports of the main and peak amplifiers decreasing final distortions of the output signal.

Abstract: The present invention relates to an amplification device for a satellite in order to amplify a plurality of n transmission channels to an output corresponding to a beam, the device comprising: frequency band combining means comprising n inputs in order to receive the n transmission channels and q outputs in order to supply respectively the channels grouped together within q frequency bands, a power amplification unit including p active amplifiers in parallel for the distributed amplification of the n channels, gain and phase adjustment means corresponding to the p power amplifiers on the q frequency bands.

Abstract: A Class D amplifier includes a ramp generator configured to generate a first signal and a second signal. Each of the first signal and the second signal oscillate between a minimum value and a maximum value. A signal generator is configured to receive an input signal, the first signal and the second signal. The input signal has a value that is between the minimum value and the maximum value. A signal generator is configured to generate a third signal and a fourth signal. The third signal is generated based on each of the first signal and the second signal transitioning from a value above the value of the input signal to a value below the value of the input signal. The fourth signal is generated based on each of the first signal and the second signal transitioning from a value below the value of the input signal to a value above the value of the input signal. An output stage is configured to drive a load based on the third signal and the fourth signal.

Abstract: An amplifier which operates with low power is provided. In the amplifier, a first input unit includes a first control circuit and a second control circuit each including one terminal connected to an output node and the other terminal connected to a respective input transistor from among the plurality of input transistors, and controls the amount of current flowing into the plurality of input transistors or flowing out of the plurality of input transistors according to operating modes of the amplifier, whereby even when an A bias current is increased in order to increase a slew rate of the amplifier, a B bias current a the quiescent current do not increase.

Abstract: An operational amplifier and a method for amplifying a signal. Embodiments provide a convenient and effective mechanism for reducing die area, design time and design verification time by sharing compensation components between the common-mode and differential feedback networks of the operational amplifier. As such, fewer compensation components are required, thereby reducing component die area. Additionally, given that the compensation components are shared between the common-mode and differential feedback networks, the feedback networks can be stabilized together with fewer compensation components to specify and verify, thereby reducing design and design verification time. Further, embodiments provide a compensation component coupling which does not couple directly to virtual ground, thereby reducing the noise of the operational amplifier.

Abstract: A wideband low-noise amplifier includes a source-degenerated common-source amplifier, a common-gate amplifier, and a matching frequency band determiner. The source-degenerated common-source amplifier is configured to amplify an input signal to output a first signal that is opposite in phase to the input signal. The common-gate amplifier is connected in parallel to the source-degenerated common-source amplifier to amplify the input signal to output a second signal that has the same phase as the input signal. The matching frequency band determiner is configured to isolate an input terminal of the source-degenerated common-source amplifier and an input terminal of the common-gate amplifier and determine a matching frequency band.

Abstract: An embodiment of the invention provides a clock and data recovery circuit. The clock and data recovery circuit comprises a phase detector, a pre-accumulator, a register, an accumulator and a digital controlled oscillator. By using the transmission path formed by the pre-accumulator, the output of the phase detector can be transmitted to the digital controlled oscillator in advance to adjust the frequency of its output clock signal and the latency due to the accumulator can be reduced.