Abstract: Systems and methods are provided for determining the value of a capacitance. A system for sensing capacitance comprises an oscillator arrangement comprising a plurality of oscillators and a mismatch compensation arrangement coupled between the oscillator arrangement and a first capacitive element having a first capacitance. The mismatch compensation arrangement is configured to selectively couple the first capacitive element to a respective oscillator of the plurality of oscillators, wherein an oscillation frequency of the respective oscillator is influenced by the first capacitance.

Abstract: A capacitance measurement circuit includes an operation amplifier; a reference capacitor having a first terminal coupled to a first input terminal of the operation amplifier and a second terminal selectively coupled to a first or second reference voltage; a sensor capacitor having a first terminal coupled to a second input terminal of the operation amplifier and a second terminal selectively coupled to the first or second reference voltage; an approximation unit having an output terminal and an input terminal coupled to an output terminal of the operation amplifier; a conversion unit having an output terminal and an input terminal coupled to the output terminal of the approximation unit; and a coupling capacitor having a first terminal coupled to the first or second input terminal of the operation amplifier and a second terminal coupled to the output terminal of the conversion unit.

Abstract: A capacitive occupant sensor for detecting an occupant sitting on a seat cushion of a seat of a vehicle includes a capacitive sensor mat, a cushion member, and a floating electrode. The capacitive sensor mat is disposed in the seat cushion and has a surface. The cushion member is disposed on the surface of the capacitive sensor mat. The floating electrode is disposed on an opposite side of the cushion member from the surface of the capacitive sensor mat. A projected area of the floating electrode with respect to the surface is smaller than the surface. The floating electrode is in an electrically-floating state with respect to the capacitive sensor mat. The occupant is detected based on an occupant capacitance between the capacitive sensor mat and the occupant and a floating capacitance between the capacitive sensor mat and the floating electrode.

Abstract: Fill level sensors designed as potentiometers are known, having two resistor strips on an electrically insulating carrier, on each of which a plurality of conductor segments are disposed at a distance from each other and act together with a pickup shoe that can move relative to the carrier, wherein the conductor segments of the one resistor strip are disposed offset from the resistors of the other resistor strip in the direction of motion of the pickup shoe. The pickup shoe electrically connects one conductor segment of the one resistor strip to a conductor segment of the other resistor strip. In order to contact the two conductor segments to be bridged, the pickup shoe has two contacts.

Abstract: Apparatus for recording electrical activity produced by cells in-vitro, which comprises a device having a polymeric structure (12) comprising a well (14) for housing and culturing cells, a duct (15) disposed at right angles to said well and connected to its bottom region, and two electrodes (13,13?) for recording a potential in said well, wherein the width of said well is at least ten times, preferably twenty times and more preferably fifty times, the width of said duct, and the width of at least of said electrodes (13) is at least ten times the width of said duct. The polymeric structure preferably comprises two such wells (14,14?) connected by said duct (15), so that one of the electrodes can be placed in one well and another one of the electrodes can be placed in the other well.

Abstract: [Object] To provide a method for measuring a target component in an erythrocyte-containing specimen with high reliability while suppressing the influence of the Ht value of the specimen. [Solution to Problem] In the measurement method of the present invention, first, prior to measurement, a relationship between amounts of the target component and a plurality of signals corresponding thereto is provided. Then, a plurality of signals derived from the target component in the erythrocyte-containing specimen are acquired with a biosensor. With reference to the relationship, the amount of the target component in the specimen is determined based on the thus-acquired plurality of signals.

Abstract: A particle measuring apparatus comprising: a detection device with an aperture through which pass particles contained in a particle suspension liquid, for detecting a signal generated when a particle passes through the aperture; and a detection device supporting part comprising an elastic body, for supporting the detection device through the elastic body is disclosed.

Abstract: Provided are a device for evaluating a degree of degradation of a lubricating oil, a method of evaluating a degree of degradation of a lubricating oil, and an on-line lubricating oil management device, which are capable of measuring the degree of degradation of the lubricating oil in a simple and stable manner. The device for evaluating a degree of degradation of a lubricating oil, the method of evaluating a degree of degradation of a lubricating oil, and the on-line lubricating oil management device using the device and the method use a pH-ISFET, and make a determination as to a state of degradation of the lubricating oil through measurement of a change in hydrogen concentration of the lubricating oil by using, as an output, a change in current flowing between a drain and a source in a case where a constant voltage is applied between the drain and the source or a change in voltage between the drain and the source in a case where a constant current is caused to flow between the drain and the source.

Abstract: A semiconductor chip includes a line structure arranged along a peripheral region of the semiconductor chip region in order to inspect a crack, a first pad and second pad arranged on different end portions of the line structure, a second pad arranged on another end portion of the line structure, an inspection device activated during a crack test mode to electrically connect the first pad, the line structure and the second pad. The inspection device may include a first switching circuit connected between the first pad and the line structure, the first switching circuit being deactivated during a normal operation mode and being activated a crack test mode; and a second switching circuit connected between the second pad and the line structure, the second switching circuit being deactivated during the normal operation mode and being activated during the crack test mode.

Abstract: A testing device suitable for a testing apparatus with light inspection of a display panel is provided, in which the testing device includes a main part and two contact parts. The testing device is fixed to the testing apparatus with light inspection by the main part. Two contact parts are respectively extended from two ends of the main part along a first direction, and each of the contact parts has a plurality of tips. The tips of each contact part have different heights. Besides, a testing apparatus is also provided. Therefore, the abovementioned testing device and the testing apparatus are able to drastically extend the user lifetime, improve the inspection accuracy and save cost.

Abstract: A probe card has a thin film substrate having projection electrodes on a first surface facing the semiconductor wafer and at a position facing the pad electrodes, a non-contact electrode, and first electrodes provided a second surface opposite to the first surface; and a wiring substrate having second electrodes disposed at a side opposite to the semiconductor wafer in the thin film substrate and at a position facing the first electrodes. The wiring substrate and the thin film substrate form a first sealed space and the thin film substrate and the semiconductor wafer form a second sealed space. By reducing the pressure in the first and the second sealed space, the first and the second electrodes are brought into close contact with each other and the pad electrodes and the projection electrodes are brought into close contact with each other, and the pressure of each of the first and second sealed space can be independently adjusted.

Abstract: A probe apparatus exchanging signals with a target device, includes: a contact section electrically connected to the target device by contacting a terminal of the target device; a non-contact section that exchanges signals with the target device in a state not contacting the terminal of the target device; and a retaining section that retains the contact section and the non-contact section, in such a manner that a relative position between the contact section and the non-contact section in a connection direction connecting the non-contact section and a region corresponding to the target device is displaceable.

Abstract: An improved efficiency system for testing electronic components in a motherboard/daughterboard assembly in which the daughterboard is mounted in spaced parallel relationship the to motherboard includes one or more device-under-test socket sub-assemblies having a test socket thereon for receiving a device-under-test and a connector component for disengagable connection to a complementary connector component on the daughterboard with the socket sub-assembly effecting interengagement of the complementary connector component on the daughterboard via an opening in the motherboard to allow ready access to the test socket for temporary installation, testing, and removal of a device-under-test.

Abstract: One embodiment is a transport apparatus for moving carriers of microelectronic devices along a track, the transport apparatus including: (a) a track with two rails adapted to support the carriers; (b) a trolley adapted to be transported in a direction along the track by a linear actuator; and (c) a first and a second engagement feature attached to the trolley wherein the first engagement feature is adapted to engage temporarily with a first of the carriers, and the second engagement feature is adapted to engage temporarily with a second of the carriers; wherein a predetermined movement of the trolley slidably moves the first carrier onto a test position and slidably moves the second carrier off the test position simultaneously.

Abstract: An embodiment of a test structure in accordance with the present invention comprises a pair of interdigitated comb portions of a metallization layer present in a recess of an inter-layer dielectric (ILD) formed over a polysilicon heater element. A third portion of the metallization layer comprises a serpentine metal line interposed between the comb portions. Application of force voltages, and detection of sense voltages, at various nodes of the metallization portions allows identification of the following: (1) electromigration of metal in the metallization portions; (2) extrusion of metal from one metallization portion to contact another; (3) breakdown voltage (Vbd) and time dependent dielectric breakdown (TDDB) of the ILD; (4) contamination in the metallization portions with mobile ions; and (5) k valve and drift in k value of the ILD. A bias voltage may be applied to the polysilicon heater to accomplish temperature control during testing.

Abstract: A data transmission circuit includes a data transmission unit and a data receiving unit. The data transmission unit generates transmission data based on first chip data and transmit the transmission data via a Through Silicon Via (TSV). The data receiving unit differentially amplifies the transmission data with respect to a reference voltage to generate second chip data.

Abstract: In an output circuit having a de-emphasis for use in high-speed serial transmission, a circuit for suppressing a fluctuation of a common mode potential which occurs in output amplitude is provided. A positive pole and a negative pole of an output circuit in a serial transmission device for differential transmission having de-emphasis are connected to the respective outputs of a differential circuit that differentially receives outputs of a detector device for a pattern of data to be transmitted, and a detector device for an inverted pattern of the data to be transmitted. When a specific pattern of data to be transmitted and its reverted pattern appear, a current of the output circuit is compensated by the connected differential circuit, thereby enabling a common mode noise to be prevented.

Abstract: A data driving impedance auto-calibration circuit includes: a detection block configured to calibrate a characteristic voltage generated by detecting an operation characteristic variation of an element, according to a code signal, and generate a calibrated characteristic voltage; a comparison block configured to compare the calibrated characteristic voltage with a reference voltage and output a comparison result signal; and a code calibration block configured to calibrate the code signal according to the comparison result signal.

Abstract: A system for controlling the termination impedance of memory device data bus terminals is fabricated on the same die as the memory device. The system includes a termination resistor connected to each data bus terminal, which is connected in parallel with several transistors that are selectively turned on to adjust the termination impedance. The transistors are controlled by a circuit that determines the resistance of the termination resistor and turns on the correct number of transistor to properly set the termination impedance. In one example, the resistance of the termination resistor is determined by directly measuring a resistor of the same type as the termination resistor. In another example, the resistance of the termination resistor is determined indirectly by measuring parameters that affect the resistance of the termination resistor. In either case, the system can maintain the termination impedance of the data bus terminals constant despite changes in the termination resistor.

Abstract: Circuits and power up sequences to reduce power consumption in programmable logic devices is disclosed.

Abstract: A driver supplies data signal via a supply node. A voltage-relaxing transistor has a source connected to the supply node of the driver, a drain connected to a signal node connected to a signal line, and a gate to which the voltage at the signal node is applied.

Abstract: A metastability-hardened storage circuit includes at least one inverting circuit. The inverting circuit has a logical input. The logical input of the inverting circuit is split into a pair of physical inputs.

Abstract: A power supply apparatus for a radio frequency power amplifier (RFPA) is provided, where the output end of a voltage controlled voltage source (VCVS) and the output ends of N current controlled current sources (CCCSs) are coupled in parallel to supply power to the RFPA. The apparatus further includes an nth sampling unit, configured to sample the sum of the output currents of the first (n?1) CCCSs and the VCVS to obtain an nth sampling signal; and an nth filtering unit, configured to filter the nth sampling signal according to a predefined nth passband and output the filtered nth sampling signal to an nth CCCS, thus controlling the output current of the nth CCCS. The nth passband is higher than an (n?1)th passband. The switching frequency of the nth CCCS is higher than the switching frequency of an (n?1)th CCCS. N is an integer greater than or equal to 2, and n is a positive integer smaller than or equal to N.

Abstract: A frequency generator is used for generating a frequency within a frequency range. The frequency generator includes a variable current source, a voltage drop generation unit, a voltage source, a detection unit, a conversion unit, and an oscillating circuit. The variable current source is used for outputting a current according to a control signal. The voltage drop generation unit is used for generating a voltage drop according to the current. The voltage source is used for outputting a voltage range. The detection unit is used for outputting the control signal to the variable current source according to a relationship between the voltage drop and the voltage range. The conversion unit is used for outputting a digital code according to the relationship between the voltage drop and the voltage range. The oscillator circuit is used for generating the frequency according to the digital code.

Abstract: A method includes generating a plurality of reference phases of a reference signal and selecting a sub-phase from each of the plurality of reference phases to form a set of selected sub-phases. In the method selecting operates in response to synchronized outputs of a multi-phase phase accumulator that operates synchronously in accordance with one of the sub-phases of the set of sub-phases, and where the outputs of the multi-phase phase accumulator may be synchronized using at least one additional sub-phase.

Abstract: A power-on reset (POR) circuit includes a first transistor (MPa) having a source coupled to a first supply voltage (VDD) and a gate coupled to a second supply voltage (GND). A resistor (R0) has a first terminal coupled by a depletion mode transistor (JP0) to the second supply voltage and a second terminal coupled to a drain of the first transistor. A Schmitt trigger (20) has an input coupled to receive a first signal (VTRIGGER) on a conductor (14) coupled to the second terminal of the resistor and a terminal of a capacitor (C0), for producing an output voltage (VO) representative of a power-on reset signal (VPOR) in response to an interruption of the first supply voltage (VDD).

Abstract: A semiconductor apparatus comprises a power-up signal generation section configured to generate a power-up signal, a driver configured to drive and output the power-up signal, and a main circuit block configured to perform predetermined functions in response to an output from the driver, wherein the power-up signal generation section and an input terminal of the driver are connected by a disconnectable element.

Abstract: A semiconductor device includes an internal circuit; a plurality of power switches arranged in parallel configured to supply a current to the internal circuit; an instruction circuit configured to output a instruction signal for controlling power supply to the internal circuit; a variation detection circuit configured to detect the current and to output a detection result; and a logic circuit configured to control a timing when the plurality of power switches becomes a conducting state in accordance with the detection result and the instruction signal.

Abstract: In some embodiments, a reset circuit for an electronic circuit equipped with a backup power capacitor includes a first detector arranged to detect a predetermined first voltage of the backup capacitor, a second detector arranged to detect a predetermined second voltage of the backup capacitor, the second voltage being lower than the first voltage, and a controller arranged to control an output of a reset request signal based on detection results of the first detector and the second detector. The controller is configured to output the reset request signal when the first detector detects the first voltage after the second detector detected the second detector.

Abstract: A phase-locked loop circuit comprises a phase error detector for receiving a multi-phase reference signal and a synchronized phase signal of the phase-locked-loop circuit, and for performing a rotational transformation to convert the multi-phase reference signal into two-phase quantities at a synchronous rotation d-q reference frame. A monotonic transfer module receives the two-phase quantities, and generates a monotonic phase error signal which is monotonic when a phase difference between the multi-phase reference signal and the synchronized phase signal ranges from ?180 degrees to 180 degrees. A regulator receives the monotonic phase error signal, and generates a synchronized rotation frequency. An integrator receives the synchronized rotation frequency, and generates the synchronized phase signal.

Abstract: There is provided a frequency synthesizer capable of improving phase noise. A sinusoidal signal with a frequency set by a frequency setting part is output as a digital signal from a set signal output part, and the digital signal is D/A-converted. A difference between a sinusoidal signal with a frequency corresponding to an output frequency of a voltage controlled oscillating part and a sinusoidal signal output from a D/A converting part is amplified by a differential amplifier, and an amplified signal is input via an A/D converting part to a means for extracting a phase difference between the aforesaid sinusoidal signals. A voltage corresponding to a signal being the result of integration of the phase difference is input as a control voltage to the voltage controlled oscillating part. Then, a gain of the differential amplifier is set larger than a maximum value of phase noise degradation of the A/D converting part, whereby the phase noise degradation of the A/D converting part is cancelled.

Abstract: Apparatus (300; 400; 500) for lock-in amplifying an input signal (SI), including one or more lock-in amplifiers (304, 307, 308; 422, 423, 424; 504, 507, 515, 516) with a first input terminal (In) for the input signal (SI) to be lock-in amplified and a second input terminal (Ref) for a reference signal, wherein at least one phase-locked loop circuit (312; 508, 514) is provided, which phase-locked loop circuit (312; 508, 514) comprises one of the one or more lock-in amplifiers (304; 422, 504; 515), an oscillator (306; 506, 511) and a feedback path (303; 421; 503, 517) from the oscillator (306; 506, 511) to the second input (Ref) of the one lock-in amplifier (304; 422, 504; 515), wherein an input terminal of the at least one phase-locked loop circuit (312; 508, 514) is connected with the first input terminal (In) of the one or more lock-in amplifiers (304, 307, 308; 422, 423, 424; 504, 507, 515, 516) and an output terminal of the oscillator (306; 506, 511) is connected to the second input terminal (Ref) of the o

Abstract: A feedback loop circuit includes a phase detector and delay circuits. The phase detector generates an output signal based on a delayed periodic signal. The delay circuits are coupled in a delay chain that delays the delayed periodic signal. Each of the delay circuits comprises variable delay blocks and fixed delay blocks that are coupled to form at least two delay paths for an input signal through the delay circuit to generate a delayed output signal. Delays of the variable delay blocks in the delay circuits vary based on the output signal of the phase detector. Each of the delay circuits reroutes the input signal through a different one of the delay paths to generate the delayed output signal based on the output signal of the phase detector during operation of the feedback loop circuit. Each of the variable delay blocks and the fixed delay blocks is inverting.

Abstract: A semiconductor apparatus for reducing unnecessary current consumption disclosed. The semiconductor apparatus includes: a clock signal transmission unit that selectively transmits a clock signal in accordance with the frequency of the clock signal at an operation standby mode. A delay locked loop generates a DLL clock signal on the basis of the clock signal inputted through the clock signal transmission unit. The delay locked loop generates the DLL clock signal during a period where the clock signal is transmitted.

Abstract: A delay locked loop (DLL) apparatus includes a first delay unit converting a reference clock into a rising clock. A second delay unit converts the reference clock into a falling clock, and a replica delay unit replica-delays the rising clock. A first phase detector compares the phases of the reference clock and the delayed rising clock to output a first detection signal corresponding to the compared phases. A controller synchronizes the rising edge of the rising clock with the rising edge of the reference clock according to the first detection signal of the first phase detector. A second phase detector compares the phases of the synchronized rising clock and the synchronization clock to output a second detection signal corresponding to the compared phases. The DLL apparatus compensates for a skew between an external clock and data and between external and internal clocks by employing a single replica delay unit.

Abstract: An apparatus for the controlled delay of an input signal includes a signal input for receiving an input signal. The input signal is supplied to a delay line with a multiplicity of delay elements. Outputs of the delay elements allow respective differently delayed phase signals to be tapped off. Furthermore, a register line with a multiplicity of register elements is provided. The register elements are each associated with one of the delay elements. Each of the register elements has a reset input and a clock input. The reset inputs are coupled to the signal input. The outputs of the delay elements are each coupled to the clock input of the register element associated therewith.

Abstract: A charge pump circuit includes a first power transistor selectively actuated by a first control signal to deliver relatively higher amounts of current to a capacitor and a second non-power transistor connected in parallel with the first power transistor and selectively actuated by a second control signal to deliver relatively lower amounts of current to the capacitor. The charge pump circuit includes a pumped voltage output that is sensed to generate a sensed voltage output. A comparison circuit compares the sensed voltage output to a threshold voltage. A logic circuit receives an output of the comparison circuit and enables the first power transistor and disables the second non-power transistor in a first mode of operation if the comparison is not satisfied. The logic circuit further disables the first power transistor and enables the second non-power transistor in a second mode of operation if the comparison is satisfied.

Abstract: An oscillation signal generator for compensating for an in-phase (I)/quadrature-phase (Q) mismatch and a communication system including the same are provided. The oscillation signal generator includes a first latch configured to generate an I oscillation signal, a second latch that is cross-coupled with the first latch and generates a Q oscillation signal, and a phase compensator connected to at least one of the first latch or the second latch. The phase compensator complementarily adjusts bias currents of the first and second I differential transistor pairs of the first latch and/or complementarily adjusts bias currents of the first and second Q differential transistor pairs of the second latch. Accordingly, the I/Q mismatch is compensated for without an additional device, so that the phase match between an I signal and a Q signal is improved in the communication system.

Abstract: A method is provided for improving clock recovery signal jitter in digital communication based on a phase adjustment technique in a phase interpolation. A clock signal is expressed as the combination of two sinusoidal signals. The phase interpolating process determines the amplitude of the first sinusoidal signal, and the amplitude of the second sinusoidal signal that is 90° out of phase from the first sinusoidal signal. The clock signal is then formed by combining first sinusoidal signal with the second sinusoidal signal by choosing the first and second amplitude such that the amplitude of the clock signal is substantially a constant. Modulation of the clock signal amplitude is significantly improved by the disclosed technique over the conventional technique when the sum of the first and second amplitudes of the two sinusoidal functions is kept a constant.

Abstract: A signal input circuit includes an input unit, a first compensation circuit, a second compensation circuit, and an enable circuit. The input unit receives a first input signal to output an output signal to an output node. The first compensation circuit is connected to the output node and discharges the output node in response to a second input signal. The second compensation circuit is connected to the output node and supplies a current to the output node in response to the second input signal. The enable circuit enables the input unit and the first and second compensation circuits in response to at least one operation mode selection signal.

Abstract: A semiconductor circuit is provided in which no error signal is generated even when the circuit is exposed to a transient voltage noise that occurs with a transition from a first state indicating a conduction of a high-potential side switching device to a second state indicating a non-conduction of the high potential side switching device, or vice versa. A high potential switching device drive circuit 1 includes short circuit devices 31 and 32 that are controlled by the second level shifted signals S6 and S7 simultaneously generated across the second load resistances 30 and 29, respectively, to thereby serving to prevent a signal from being generated at one of the output sections where the other one of the first level shifted signals S4 and S5 is to be generated, when either one of the first shifted signals S4 and S5 in level shift circuit ON and OFF sections is generated across first load resistance 28 or 27 in a level shift circuit 2.

Abstract: A method for tracking power supplies includes the following steps: receiving, by a controller, a signal to be tracked and outputting, according to the signal to be tracked, a control signal. The control signal controls at least two sets of voltage level selection circuits in selecting at least one tracking voltage level from at least two groups of isolation voltage levels and controls each set of the voltage level selection circuits selecting at most one tracking voltage level from a group of isolation voltage levels. An isolation power supply provides the at least two groups of isolation voltage levels according to the voltage level interval of the signal to be tracked. Each group of isolation voltage levels includes at least two tracking voltage levels. The voltage level selection circuits provide the selected tracking voltage level to supply power to a load circuit. An apparatus for tracking power supplies is also provided.

Abstract: A modulator drive circuit provides a modulator drive signal, representative of a data waveform, to modulate an optical signal for transport across a network infrastructure. The modulator drive circuit includes a broadband Bias-T circuit insensitive to the frequency range of the data waveform. The Bias-T circuit provides for an adjustable bias level to maintain proper operation of a modulator used to modulate the optical signal. One or more modulator drive circuits may be provided on a single substrate.

Abstract: The invention relates to a receiving circuit for transmission through interconnections used for sending a plurality of electrical signals. Each of the output signals of the receiving circuit produced by the receiving circuit of the invention is delivered by an output of a combining circuit having 4 inputs and 4 outputs. Each signal terminal of the receiving circuit is connected to a first input terminal of a differential circuit, the differential circuit also having a second input terminal and a single output terminal. The common terminal of the receiving circuit is connected to the second input terminal of each of the differential circuits. Each input of the combining circuit is coupled to the output terminal of one of the differential circuits. Each of the output signals of the receiving circuit is a linear combination of the voltages between one of the signal terminals and the common terminal.

Abstract: A two-level or multi-level inverter are supplied with a positive auxiliary voltage (Ug+) and a negative auxiliary voltage (Ug?). A bootstrap technique provides a first positive auxiliary voltage and a first negative auxiliary voltage from the supplied potentials. The bootstrap technique provides at least one additional negative auxiliary voltage to a switch driver of at least one semiconductor switch from the first negative auxiliary voltage. At the start up of an inverter, the inverter can perform a startup sequence to provide auxiliary voltages to the respective auxiliary voltage inputs of the switch drivers by turning the power semiconductors sequentially on and off.

Abstract: In some embodiments, an input/output (I/O) circuit sends and receives a high-level signal and a low-level signal via a coupling capacitance provided on a communication line. The I/O circuit includes a receiving portion including a first detection circuit arranged to detect one of the signals and a second detection circuit arranged to detect the other signal, a transmitting portion including a three-value output circuit configured to output one of signals consisting of a high-level signal, a low-level signal, and a high impedance signal, and a control circuit configured to control the receiving portion and the transmitting portion. The control circuit judges a level of an inputted signal depending on detection results of the first detection circuit and the second detection circuit in a receiving state and controls an output value of the three-value output circuit in a transmitting state.

Abstract: A photoelectric conversion device comprising an electrically conductive film, an organic photoelectric conversion film, and a transparent electrically conductive film, wherein the organic photoelectric conversion film contains a compound represented by the following formula (1) and an n-type organic semiconductor: wherein each of R1 and R2 independently represents a substituted aryl group, an unsubstituted aryl group, a substituted heteroaryl group or an unsubstituted heteroaryl group, each of R3 to R11 independently represents a hydrogen atom or a substituent provided that an acidic group is excluded, m represents 0 or 1, n represents an integer of 0 or more, R1 and R2, R3 and R4, R3 and R5, R5 and R6, R6 and R8, R7 and R8, R7 and R9, or R10 and R11 may be combined each other to form a ring, and when n is an integer of 2 or more, out of a plurality of R7's and R8's, a pair of R7's, a pair of R8's, or a pair of R7 and R8 may be combined each other to form a ring.

Abstract: A novel capacitor for use in a charge pump circuit has a substrate with a planar surface. A first electrode is in a first plane spaced apart from the planar surface. A second electrode is adjacent to and is spaced apart from the first electrode in the first plane and is capacitively coupled thereto. A third electrode is in a second plane, spaced apart from the first plane and is capacitively coupled to the first electrode. A fourth electrode is adjacent to and spaced apart from the third electrode in the second plane and is capacitively coupled to the third electrode and capacitively coupled to the second electrode. The first and fourth electrodes are electrically connected together and the second and third electrodes are electrically connected together. In addition, a cylindrical shape electrode, and a great wall electrode, and charge pump capacitor-by-pattern-filling is disclosed.

Abstract: An integrated circuit containing a configurable dual n/p-channel 3-D resurf high voltage MOS field effect transistor (MOSFET) is disclosed. An n-channel drain is coterminous with a p-channel source in an n-well, and a p-channel drain is coterminous with an n-channel source in a p-well. A lateral drift region including n-type drift lanes and p-type drift lanes extends between the n and p wells. A resurf layer abuts the lateral drift region. The n-channel MOS gate is separate from the p-channel MOS gate. The p-channel MOS gate may be operated as a field plate in the n-channel mode, and vice versa. An n-channel MOS transistor may be integrated into the n-channel MOS source to provide an n-channel cascode transistor configuration, and similarly for a p-channel cascode configuration, to debias parasitic bipolar transistors under the MOS gates. Circuits using the MOSFET with various loads are also disclosed.

Abstract: A semiconductor device, a semiconductor memory tester, and a multi-chip package are provided. The semiconductor device includes a plurality of nonvolatile semiconductor memories; a boosting circuit which generates a boosted voltage for operating the plurality of nonvolatile semiconductor memories; and a boosting circuit controller which controls the operation of the boosting circuit to generate the boosted voltage on the basis of an operation sequence of the plurality of nonvolatile semiconductor memories.