Abstract: An integrated circuit has an untrimmed bandgap generation circuit; and a bandgap generation circuit coupled to the untrimmed bandgap generation circuit. The bandgap generation circuit has a current source controlled by the untrimmed bandgap generation circuit and coupled in series with a resistor and a first bipolar diode device, one or more of bipolar diode devices, each bipolar diode device coupled in parallel with the first bipolar diode device, wherein a trimmed bandgap reference voltage output of the integrated circuit is a function of the number of bipolar diode devices.

Abstract: Provided is a reference voltage circuit in which a temperature characteristic of a reference voltage is excellent and a circuit scale is small. In the reference voltage circuit, for example, a temperature correction circuit separated from the reference voltage circuit is not used and a difference voltage between threshold voltages of two E-type NMOS transistors (14 and 15) is added to a threshold voltage of a D-type NMOS transistor to generate a reference voltage (Vref). Therefore, the influence of the D-type NMOS transistor on the reference voltage (Vref), which is a degradation factor of the temperature characteristic of the reference voltage (Vref), may be reduced to suppress a change in tilt and curve of the reference voltage (Vref) with respect to a temperature.

Abstract: A test apparatus that tests a device under test, comprising a signal input section that supplies a test signal to a device under test and a judging section that judges acceptability of the device under test based on a response signal output by the device under test in response to the test signal. The signal input section includes an operation circuit that operates to generate the test signal and a power supply stabilizing circuit provided in the same chip to stabilize power supply voltage supplied to the operation circuit. The power supply stabilizing circuit includes a high-speed compensating section compensating for a change in the power supply voltage supplied to the operation circuit, at a predetermined compensation speed, and a low-speed compensating section compensating for the change in the power supply voltage supplied to the operation circuit, at a predetermined compensation speed lower than that of the high-speed compensating section.

Abstract: A suite of novel structures and methods is provided to reduce power consumption in a wide array of electronic devices and systems. Some of these structures and methods can be implemented largely by reusing existing bulk CMOS process flows and manufacturing technology, allowing the semiconductor industry as well as the broader electronics industry to avoid a costly and risky switch to alternative technologies. As will be discussed, some of the structures and methods relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced ?VT compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having dopants in the channel region to be set much more precisely. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors.

Abstract: A semiconductor device according to an exemplary aspect of the invention is capable of being selectively switched between an oscillation circuit and a signal input-output circuit, and includes first and second external connecting terminals that are connectable to an oscillation device; an inverting amplifier an input side of which is electrically connected to the first external connecting terminal through a coupling capacitor and an output side of which is electrically connected to the second external connecting terminal; a feedback resistor connected to the input side and the output side of the inverting amplifier; a bias stabilization circuit that stabilizes a bias applied to the coupling capacitor; a first signal input-output portion connected to the first external connecting terminal; and a second signal input-output portion connected to the second external connecting terminal.

Abstract: The determination of the signal modulation format for a channel is an important aspect of the operation of a signal receiver. A method (700) is described including the steps of receiving (710) a signal, comparing (720) a sample of the received signal to a first threshold value and a second threshold value, creating (720) a signal profile based on the comparison, and selecting (750) a modulation format for the received signal based on the signal profile. An apparatus (500) is also described including a ring counter (510) that receives a sample of an input signal, compares the sample to a first threshold value and a second threshold value, and creates a signal profile for the input signal, a signal profiler (550) that compares the signal profile for the input signal to at least two reference profiles, and a detector (560) that determines a modulation format for the input signal based on the comparison in the signal profiler (550).

Abstract: A demodulator according to the present invention is the demodulator that demodulates a plurality of received symbols having different amplitude of carrier wave. The demodulator includes an amplitude value calculation unit that calculates a received symbol amplitude value by adding an absolute value of in-phase component and an absolute value of quadrature component determined from the amplitude of the carrier wave in the received symbol. Further, the demodulator includes a demodulation unit that detects a change of the received symbol amplitude value calculated by the amplitude value calculation unit, and demodulates the received symbol based on the detection result.

Abstract: The invention relates to an amplifier capable of delivering a plurality of output signals, these output signals being controlled by a plurality of input signals. A multiple-input and multiple-output amplifier of the invention comprises a common input terminal, 4 signal input terminals, 4 signal output terminals, a common terminal amplifier, 4 active sub-circuits and a feedback network. Each active sub-circuit has a sub-circuit input terminal connected to one of the signal input terminals, a sub-circuit output terminal connected to one of the signal output terminals and a sub-circuit common terminal. The feedback network has four C terminals and one R terminal. Each of said C terminals of the feedback network is coupled to the sub-circuit common terminal of one of said active sub-circuits. The output terminal of the common terminal amplifier is coupled to said R terminal of the feedback network.

Abstract: Provided is an operational amplifier capable of correcting an offset voltage of an element to be connected to an input terminal. The operational amplifier includes a main amplifier and an offset correction amplifier, which include input terminals connected in common. The main amplifier includes: a first transconductance amplifier for measurement; a second transconductance amplifier for offset correction; and a first capacitor connected to an input terminal of the second transconductance amplifier. The offset correction amplifier includes: a third transconductance amplifier for measurement; a fourth transconductance amplifier for offset correction; and a second capacitor connected to one input terminal of the fourth transconductance amplifier. An offset voltage adjustment circuit is provided to another input terminal of the fourth transconductance amplifier included in the offset correction amplifier.

Abstract: A multi mode power output module for use with RF signal amplification system. The multi mode power output module includes at least two power sources; a multiple of output power circuits associated with each of the at least two power sources; a first switch to switch between the at least two power sources, where the first switch provides power from at least two power sources to the output power circuit to amplify an RF signal associated with a lowest power output level; and second switch to switch between an RF output and the multiple of output power circuits to select a output power circuit associated with one of the at least two power sources that is also connected to the RF output.

Abstract: An offset voltage calibration method is disclosed, which is utilized for calibrating an offset voltage of an electronic device during a calibration period. The offset voltage calibration method includes generating a control signal according to an output signal of the electronic device, counting a count value and generating an offset indication signal according to the control signal, stopping counting and generating a final count value according to a compensation value after the output signal changes state, generating a calibration signal according to the count value or the final count value, and calibrating the offset voltage according to the offset indication signal and the calibration signal.

Abstract: A method and system are provided for reducing power amplifier induced distortion. Power amplifier induced distortion is iteratively estimated and cancelled. When the difference between the current estimated power amplifier distortion and the previous estimated power amplifier distortion is less than a convergence threshold, particular M-QAM constellation points that are still in error are determined A M-QAM constellation point correction routine is provided that can move the incorrectly estimated M-QAM constellation points that are in error towards their expected quadrants by generating updated M-QAM constellation points. The remaining estimated non-linear power amplifier induced distortion in the received signal can then be estimated and canceled.

Abstract: A Provided is a differential amplifier in which a current flowing into an output transistor may be adjusted to a constant value even when a voltage of a non-inverting input terminal changes. A current flowing through the differential amplifier circuit is controlled by a current source, a current value of which is changed depending on the voltage of the non-inverting input terminal.

Abstract: Provided is a voltage regulator having a structure in which an output terminal of a first differential amplifier circuit is connected to a second differential amplifier circuit to control an output transistor by the second differential amplifier circuit. When low current consumption is required, the first differential amplifier circuit is suspended. When high-speed response is required, the first differential amplifier circuit is activated. The low-current consumption operation and the high-speed operation are switched with a minimum circuit area.

Abstract: Embodiments are directed to capacitance compensation via a compensation device coupled to a gain device to compensate for a capacitance change occurring due to an input signal change, along with a controller coupled to the compensation device to receive the input signal and to control an amount of compensation based on the input signal. In some embodiments, banks may be formed of multiple compensation devices, where each of the banks has a different size and is coupled to receive a different set of bias voltages.

Abstract: Embodiments are described including those pertaining to an input buffer having first and second complementary input terminals. One such input buffer has a symmetrical response to a single input signal applied to the first input terminal by mimicking the transition of a signal applied to the second input terminal in the opposite direction. The aforementioned input buffer includes two amplifier circuits structured to be complementary with respect to each other. Each of the amplifier circuits includes a first transistor having a first input node that receives an input signal transitioning across a range of high and low voltage levels, and a second transistor having a second input node that receives a reference signal.

Abstract: A power transistor for use in an audio application is laid out to minimize hot spots. Hot spots are created by non-uniform power dissipation or overly concentrated current densities. The source and drain pads are disposed relative to each other to facilitate uniform power dissipation. Interleaving metal fingers and upper metal layers are connected directly to lower metal layers in the absence of vias to improve current density distribution. This layout improves some fail detection tests by 17%.

Abstract: A circuit for biasing a gallium arsenide (GaAs) power amplifier includes a reference voltage generator circuit implemented in a gallium arsenide (GaAs) material system, a field effect transistor (FET) bias circuit implemented in the gallium arsenide material system and adapted to receive an output of the reference voltage generator circuit and adapted to provide an output to a radio frequency (RF) amplifier stage.

Abstract: In a dual-band capable voltage-controlled oscillator (VCO) device at least two voltage-controlled oscillator units (VCO1, VCO2) are coupled via a reactive component (A) and each said at least one voltage-controlled oscillator unit (VCO1, VCO2) further being connected to at least a respective external switching device (B1, B2) adapted to control an operating frequency of the A (VCO) device.

Abstract: A frequency measurement circuit includes: a first counter that counts a number of edges of a clock signal; a counter latch circuit that stores a first count value of the first counter in response to a reference edge corresponding to a reference clock; a first delay circuit that includes a plurality of first unit delay circuits coupled in series and receives the clock signal; a plurality of first delay latch circuits that latch a respective output among the plurality of first unit delay circuits; a first edge detection circuit that detects the edge in the first delay circuit based on the outputs of the plurality of first delay latch circuits; and a first calculator that calculates a cycle or a frequency of the clock signal based on the first count value between two reference edges and position information corresponding to a edge detected between the two reference edges.

Abstract: Provided is a piezoelectric resonator having a structure in which the piezoelectric resonator chip is mounted on a silicon substrate without deteriorating a characteristic. The piezoelectric resonator includes a silicon substrate (2), a metal film (3) formed on a front surface of the silicon substrate (2), a pair of mount electrodes (5, 6) formed on the metal film (3), and an AT-cut type piezoelectric resonator chip (7) that is bump-bonded to the pair of mount electrodes (5, 6) to be supported. A linear expansion coefficient of the metal film (3) is 13×10?6 per degrees centigrade or larger, and a product of the linear expansion coefficient and a Young's modulus of the metal film (3) is 1.95 MPa per degrees centigrade or larger.

Abstract: A piezoelectric ceramic composition is provided which contains Perovskite oxides expressed by General Formula 1 below and an aluminum compound, and in which the content ratio of the aluminum compound to the Perovskite oxides is from 1% by mass to 11% by mass, (Pb?-?-?-?M1?M2?Bi?)[Ti{1-(x+y+z)}ZrxMnyNbz]O3??(1) wherein in the General Formula (1), M1 represents at least one kind of element selected from the group consisting of La, Ce, Pr, and Nd, M2 represents at least one kind of element selected from the group consisting of Sr, Ca, and Ba, and ?, ?, ?, ?, x, y, and z satisfy the following numerical conditions: 0.96???1.01 0.03???0.07 0???0.10 0???0.02 0?x?0.24 0.02?y?0.04 0.03?z?0.

Abstract: A hybrid system having a non-MEMS device and a MEMS device is described. The apparatus includes a non-MEMS device and an integrated circuit including a MEMS device, the integrated circuit formed on a substrate. The integrated circuit includes a control circuit for the non-MEMS device and a MEMS control circuit for the MEMS device.

Abstract: A quadrature amplitude modulator is provided. An oscillator generates an in-phase carrier signal having a rectangular wave, a trapezoidal wave or a waveform similar to these, and a quadrature carrier signal, the phase of which is shifted by ¼ cycle relative to the in-phase carrier signal. A multi-level driver generates an in-phase modulated signal by amplitude modulating the in-phase carrier signal with an analog in-phase baseband signal having a discrete voltage level or current level in accordance with the in-phase baseband data. Likewise, the multi-level driver generates a quadrature modulated signal by amplitude modulating the quadrature carrier signal with an analog quadrature baseband signal having a discrete voltage level or current level in accordance with the quadrature baseband data The multi-level driver generates a modulated signal, the amplitude of which takes a discrete level, by combining the modulated signals together.

Abstract: An example of a transmission-line transformer may include a transmission-line assembly and a balun assembly. The transmission-line assembly may include first and second conductors forming at least first and second transmission-line sections. The transmission-line assembly may provide a signal path through the first conductor and second conductor in series to a circuit ground. Balanced lines of the balun assembly may be connected to respective intermediate points on the first and second conductors between the first and second transmission-line sections. The transmission-line transformer may provide a signal path between a first end of the first conductor of the transmission-line assembly and the unbalanced line of the balun assembly.

Abstract: An I/O calibration method and an apparatus are provided for calibrating a driving impedance at an output end of an I/O circuit in a chip. The chip further includes a plurality of basic impedances and a non-volatile memory. The I/O circuit calibration method includes: measuring an impedance value of one basic impedance and recording the measured impedance value in the non-volatile memory; synthesizing a calibration impedance by selectively conducting the basic impedance(s); adjusting the number of the conducted basic impedance(s) in the calibration impedance and estimating an impedance value of the driving impedance according to the measured result and a voltage divided by the calibration impedance and the driving impedance at the output end.

Abstract: A ceramic multilayer construction includes three resonators designed as parallel strip lines that are capacitatively or magnetically coupled to each other. All circuit components are implemented in the form of metallizations in multilayer construction. Capacitative couplings are implemented by coupling capacitors. The strip line resonators are shortened by shunt arms to ground having grounding capacitors arranged therein.

Abstract: Disclosed herein is an intermediate frequency filter having a variable pass band, which is capable of varying a pass band to minimize loss at a plurality of intermediate frequencies. The intermediate frequency (IF) includes a band pass filter unit arranged between a frequency conversion IC and a demodulation unit and configured to filter an IF signal output from the frequency conversion IC and output a resulting signal. A band varying unit is connected to the band pass filter unit and is configured to vary a pass band of the band pass filter unit. A switching unit connects or disconnects the band varying unit to or from the band pass filter unit. A control unit detects the IF signal and controls the switching unit in response to the IF signal so that the band varying unit is connected to or disconnected from the band pass filter unit.

Abstract: An electronic device includes a semiconductor device; and a mounting substrate mounted with the semiconductor device and connected with predetermined voltages. The semiconductor device includes a filter circuit section configured to output a harmonic component of an input signal other than a desired frequency component to the mounting substrate and output the desired frequency component to an output node of the filter circuit section. The filter circuit section includes an inductor which is larger than a parasitic inductance component in the mounting substrate.

Abstract: A vehicle-mounted noise filter which suppresses electric field coupling between input and output terminals in the FM radio band, thereby allowing noise attenuation performance, which should originally be provided to a noise filter circuit, to be exhibited even in the FM radio band. The vehicle-mounted noise filter comprises a coil (1) obtained by winding a conductive wire around a magnetic core, input and output terminals (2, 3) electrically connected to both terminals of the coil, and a shielding member (4). The shielding member (4) is made of a conductive member which is grounded and disposed so as to shield the electric field between the input and output terminals (2, 3). The noise filter can also be configured using a capacitor having one terminal electrically connected to the coil (1) and the other terminal grounded.

Abstract: To pass an ultra high-speed differential signal and make it difficult to pass a common mode noise. Lamped-constant differential delay line DL is formed by arranging inductors Lo, being passive series elements, and capacitors Co, being passive parallel elements, in a differential four terminal network of a ladder shape composed of the passive series elements and the passive parallel elements arranged in differential lines 1 and 3. The lumped-constant differential delay line DL is composed of capacitors Co including two capacitors Co/2 and Co/2, or Co and Co equivalent to the aforementioned capacitors, having equal values, and connected in series. Inductors L1 to L4 for attenuating a common mode noise are connected between connection points of the capacitors Co/2 and Co/2 or Co and Co connected in series, and a ground potential, so that attenuation poles are formed for attenuating the common mode noise together with the capacitors Co/2 and Co.

Abstract: In a multilayer bandpass filter, a first capacitor is defined between a first capacitor electrode and a ground electrode. A second capacitor is defined between a second capacitor electrode and the ground electrode. A first inductor is defined by first and second via electrodes and a first inductor electrode. A second inductor is defined by third and fourth via electrodes and a second inductor electrode. Two LC parallel resonators, one of which includes the first inductor and the first capacitor and the other one of which includes the second inductor and the second capacitor, are provided. The second via electrode included in one of the LC parallel resonators and the fourth via electrode included in the other one of the LC parallel resonators are electrically connected to each other by a via coupling electrode.

Abstract: A bandpass filter includes three resonators of which adjacent two are electromagnetically coupled to each other, and two coupling paths connected in parallel for forming capacitive coupling between non-adjacent two of the resonators. Each of the two coupling paths includes at least one capacitor and an inductor connected in series. The two coupling paths function to form an attenuation pole at a frequency lower than the passband frequencies in the pass attenuation characteristics of the bandpass filter.

Abstract: A radio frequency circuit structure for transmitting radio signals includes a lower guide portion having a plurality of photocurable layers deposited on a substrate and an upper guide portion interfacing with the lower guide portion to define a guiding geometry. The upper guide portion may also include a plurality of photocurable layers deposited on a second substrate. A method for fabricating the radio frequency circuit structure includes depositing the plurality of photocurable layers on the substrate. A portion of each photocurable layer of the plurality of photocurable layers is exposed to ultraviolet light to form a latent image. The plurality of photocurable layers is developed to remove the portions not exposed to ultraviolet light to form a guide portion. The guide portion may be metalized and closed to form a guiding geometry. A lower guide portion may be closed by an upper guide portion formed in substantially the same manner as the lower guide portion.

Abstract: The invention relates to a magnetic strip, the strip having a magnetically easy direction axially parallel to a transverse axis of the strip. The strip is cut to length from a band of a magnetically semi-hard, crystalline alloy along a transverse axis of the band essentially corresponding to a width (b) of the strip. The band has a magnetically easy direction axially parallel to a longitudinal axis of the band.

Abstract: A permanent magnet comprises boron, cobalt, a metallic alloy component, about 28-35 weight percent of mixed rare-earth material, and iron as a balance. The metallic alloy component is selected from the group consisting of aluminum, copper, niobium, gallium, vanadium, chromium, zirconium, and combinations thereof. The mixed rare-earth material comprises light rare-earth material and heavy rare-earth material. The light rare-earth material comprises at least about 50 weight percent of praseodymium and about 5-50 weight percent of neodymium. The heavy rare-earth material comprises dysprosium or a combination of dysprosium and terbium. The mixed rare-earth material comprises about 3-45 weight percent of heavy rare-earth material. A sum of intrinsic coercivity in the unit of kilo Oersted (kOe) and maximum energy product in unit of mega gauss Oersteds (MGOe) of the permanent magnet is at least about 55.

Abstract: Anisotropic rare earth-iron based resin bonded magnet comprises: [1] a continuous phase including: (1) a spherical Sm2Fe17N3 based magnetic material covered with epoxy oligomer where its average particle size is 1 to 10 ?m, its average aspect ratio ARave is 0.8 or more, and mechanical milling is not applied after Sm—Fe alloy is nitrided; (2) a linear polymer with active hydrogen group reacting to the oligomer; and (3) additive; and [2] a discontinuous phase being an Nd2Fe14B based magnetic material coated with the epoxy oligomer where its average particle size is 50 to 150 ?m, and its average aspect ratio ARave is 0.65 or more, further satisfying: [3] the air-gap ratio of a granular compound on the phases is 5% or less; and [4] a composition where crosslinking agent with 10 ?m or less is adhered on the granular compound is formed at 50 MPa or less.

Abstract: A cost effective integrated automotive solution for a charger transformer with minimized fringing flux and core grounding for reducing electromagnetic interference (EMI). The method provides an air gap filled with a mixture of an adhesive and ferrite powder that bonds the ferrite core sections together. In addition, the ground pin of the transformer is exposed through a groove in the pocket of the bobbin on which the core is mounted and an electrical contact is established between the exposed end of the ground pin and the core surface by means of a drop of epoxy.

Abstract: A cost effective solution for construction of high frequency, double ended, isolated, push pull, center tapped power transformers operating in continuous/discontinuous mode with minimized winding proximity losses comprises at least two identical sets of windings with identical coupling coefficients. Each set of windings consists of at least one primary winding and at least one secondary winding tightly coupled to each other. Both the sets of windings are loosely coupled to each other with a magnetic field isolating separator.

Abstract: The invention provides a transformer for a computer tomography gantry (91) for transfering contactlessly electrical energy from a stationary part of the gantry (92) to a rotary part of the gantry (93), wherein the transformer comprises a set of primary windings (103, 105, 203, 204), a set of secondary windings (103, 105, 203, 204), a set of first cores (101, 202, 301), a set of second cores (101, 202, 301), wherein the set of primary windings (103, 105, 203, 204) being arranged at the set of first cores (101, 202, 301) on the stationary part of the gantry (92), such that a winding of the set of primary windings (103, 105, 203, 204) is adapted to induce a magnetic flux into a core of the set of first cores (101, 202, 301), wherein the set of secondary windings (103, 105, 203, 204) being arranged at the set of second cores (101, 202, 301) on the rotary part of the gantry (93), such that a winding of the set of secondary windings (103, 105, 203, 204) is adapted to induce a magnetic flux into a core of the set of

Abstract: A multilayer coil device is formed by alternately stacking a plurality of insulating layers and a plurality of substantially spiral coil patterns. In the multilayer coil device, the number of turns of each of the substantially spiral coil patterns is more than one. Each of the substantially spiral coil patterns has a protrusion protruding toward a center of the substantially spiral coil pattern. The protrusion is located in a specific region where the number of coil pattern portions that cross a virtual line extending radially outward from the center of the coil pattern is smaller than that in another region of the substantially spiral coil pattern. The protrusion is provided as an additional part of a coil pattern portion that is closest to the center of the substantially spiral coil pattern in the specific region.

Abstract: An electronic device which includes an electronic component having a substrate and a plurality of metal interconnection layers, the plurality of metal interconnection layers having a top surface. It further comprises a dielectric layer situated above said metal interconnection layers, a conductive layer situated above said dielectric layer, an inductor coil and a ground shield, the inductor coil being formed in the conductive layer and the ground shield being formed in a layer of said plurality of metal interconnection layers.

Abstract: An electronic component having a coil includes a laminated body formed by laminating a plurality of magnetic body layers. The coil is formed by connecting coil electrodes in the laminated body. Nonmagnetic body layers are disposed on the laminated body to have a gap with the coil when seen in a plan view from a coil axis direction of the coil. The embodiment of an electronic component has a stair-like direct-current superposition characteristic.

Abstract: An electrical fuse structure is disclosed. The electrical fuse structure includes: a fuse element disposed on surface of a semiconductor substrate; an anode electrically connected to one end of the fuse element; and a cathode electrically connected to another end of the fuse element, wherein no silicide is formed on at least part of the cathode of the electrical fuse structure.

Abstract: A variable resistance element capable of increasing stability of a resistance changing operation and reducing a current necessary for changing, to a low resistance state for the first time, the variable resistance element in an initial state immediately after manufacture. The variable resistance element includes: a first electrode (101); a memory cell hole (150) formed above the first electrode (101); a first variable resistance layer (201) covering a bottom of the memory cell hole (150) and an upper surface of the first electrode (101); a second variable resistance layer (202) formed on the first variable resistance layer (201); and a second electrode (102) formed on the memory cell hole (150), in which a thickness of the first variable resistance layer (201) at the bottom of the memory cell hole (150) gradually decreases toward an edge area of the memory cell hole (150) and has a local minimum value around the edge area of the memory cell hole (150).

Abstract: A control system for controlling interfaces of an electronic device. The electronic device includes a display device. The control system includes a storage module stores a plurality of human face images and desktop media files. A detecting module detects whether a face of a user is within a determined range and accordingly outputs a detection signal in response to the face being within the determined range. An image capture module captures a face image of the user according to the detection signal and outputs the face image. An identify module receives the face image and compares the face image with the plurality of stored human face images in the storage module, for identifying the age of the user, and output an identification result. A control module reads a corresponding desktop media file from the storage module according to the identification result and displays the media file on the display device.

Abstract: The present disclosure describes a system for managing a plurality of lockers proximate a theme park attraction, the system having an electronically actuated lock disposed on the plurality of lockers, a guest identifier carriable on the guests person, the identifier usable as an electronic key configured to lock and unlock the lock, an egress sensor positioned at an exit of the theme park attraction and a processor in communication with the lock and the egress sensor and configured to unlock the lock subsequent to being signaled by the egress sensor. A method for using and managing a plurality of lockers is also described.

Abstract: A remote monitoring and control system includes a monitoring and control device operated to control loads; and a load control device for controlling the loads based on the operation of the monitoring and control device. The monitoring and control device includes: a display unit for displaying an operation screen including operation keys for controlling corresponding loads; an input receiving unit for receiving an input through the displayed operation keys; a reading unit for reading out a user ID; a storage unit for storing load-identifying information identifying loads and control information having control contents of the loads; and a determining unit for searching the storage unit if a user ID is read out, and determining the load-identifying information and the control information which correspond to the user ID, and the load control device controls the loads identified based on the load-identifying information, depending on the control contents of the control information.

Abstract: Apparatus and methodology for providing electronic access control are disclosed. In an exemplary configuration, a retrofittable electronic lock can be used to provide secure storage to an enclosure. A user interface and LCD visual display can be provided to permit convenient adjustment of system operational parameters. In certain embodiments, the electronic access control system includes master-slave control capabilities. In other embodiments, the electronic access control system includes inventory management capability. In still other embodiments, apparatus and methodologies provide the secure storage of the enclosure when the enclosure is being moved or otherwise transported from one location to another location. Various alternative arrangements may provide various alert features, as well as battery features which facilitate rapid replacement and/or reconfiguration.

Abstract: A method of detecting touch events on a touch panel includes identifying sets of coordinate locations based on at least one signal from at least one sensor. The at least one signal is responsive to at least one touch event, and the coordinate locations represent matches with respect to template fingerprints. Consecutive ones of the sets of coordinate locations are compared based on a first distance threshold to form streams of spatially continuous coordinate locations that satisfy the first distance threshold. A touch event is identified corresponding to one of the streams of spatially continuous coordinate locations, the stream having a minimum number of spatially continuous coordinate locations.