Abstract: The present invention comprises compositions and methods for making monoclonal antibodies. The present invention further comprises vectors that replicate the immune system components, particularly an antigen-presenting cell (APC) element of the immune synapse. Additionally, the present invention may further comprise synthetic T-cells.

Abstract: One embodiment is a method for fabricating ICs from a semiconductor wafer. The method includes performing a first process on the semiconductor wafer; taking a first measurement indicative of an accuracy with which the first process was performed; and using the first measurement to generate metrology calibration data, wherein the metrology calibration data includes an effective portion and a non-effective portion. The method further includes removing the non-effective portion from the metrology calibration data and modeling the effective portion with a metrology calibration model; combining the metrology calibration model with a first process model to generate a multi-resolution model, wherein the first process model models an input-output relationship of the first process; and analyzing a response of the multi-resolution model and second measurement data to control performance a second process.

Abstract: A blank wafer is placed in an etch chamber. A layer is deposited over the blank wafer, comprising providing a deposition gas, forming the deposition gas into a deposition plasma, and stopping the deposition gas. The blank wafer with the deposited layer is removed from the etch chamber. The thickness of the deposited layer is measured. Wafer temperature accuracy is calculated from the measured thickness of the deposited layer. The etch chamber is compensated according to the calculated wafer temperature accuracy. A wafer with an etch layer over the wafer and a patterned mask over the etch layer is placed into the etch chamber. The etch layer is etched in the etch chamber.

Abstract: An object of the present invention is to provide a group III nitride semiconductor stacked structure having a high-quality A-plane group III nitride semiconductor layer on an R-plane sapphire substrate. The inventive group III nitride semiconductor stacked structure comprises a substrate composed of R-plane sapphire (?-Al2O3), a buffer layer composed of aluminum gallium nitride (AlxGa1-xN: 0?X?1) formed on said substrate and an underlying layer composed of an A-plane group III nitride semiconductor (AlxGayInzN1-aMa: 0?X?1, 0?Y?1, 0?Z?1, and X+Y+Z=1; wherein, M represents a group V element other than nitrogen (N), and 0?a?1) formed on said buffer layer, wherein the pit density of the surface of said underlying layer is 1×1010 cm?2 or less.

Abstract: The present invention is related to a luminescent material generated by polymerization of a pyrromethene complex by glow discharge. The polymer material of the present invention exhibits semi-conductive properties and has a luminescence maximum in a spectrum region in the range of about 540 nm to about 585 nm with a half-width of the luminescence band in the range of about 55 nm to about 75 nm, a quantum yield of photoluminescence in the range of about 0.6 to about 0.8, and an electric conductivity at a temperature of about 20° C. in the range of about 1×10?10 S/cm to about 5×10?10 S/cm. The resultant polymer layer has a thickness in the range of about 0.01 ?m to about 10 ?m on a substrate placed between or on any of the electrodes. The starting pyrromethene complex may be a 1,3,5,7,8-pentamethyl-2, 6-diethylpyrromethene difluoroborate complex (pyrromethene 567).

Abstract: Some embodiments include methods of forming diodes. The methods may include oxidation of an upper surface of a conductive electrode to form an oxide layer over the conductive electrode. In some embodiments, the methods may include formation of an oxidizable material over a conductive electrode, and subsequent oxidation of the oxidizable material to form an oxide layer over the conductive electrode. In some embodiments, the methods may include formation of a metal halide layer over a conductive electrode. Some embodiments include diodes that contain a metal halide layer between a pair of diode electrodes.

Abstract: The present invention generally relates to organic light emitting diode (OLED) structures and methods for their manufacture. To increase the lifetime of an OLED structure, an encapsulating layer may be deposited over the OLED structure. The encapsulating layer may fully enclose or “encapsulate” the OLED structure. The encapsulating layer may have a substantially planar surface opposite to the interface between the OLED structure and the encapsulating layer. The planar surface permits successive layers to be evenly deposited over the OLED structure. The encapsulating layer reduces any oxygen penetration into the OLED structure and may increase the lifetime of the OLED structure.

Abstract: An LED chip package structure with high-efficiency light-emitting effect includes a substrate unit, a light-emitting unit, and a package colloid unit. The substrate unit has a substrate body, and a positive electrode trace and a negative electrode trace respectively formed on the substrate body. The light-emitting unit has a plurality of LED chips arranged on the substrate body. Each LED chip has a positive electrode side and a negative electrode side respectively and electrically connected with the positive electrode trace and the negative electrode trace of the substrate unit. The package colloid unit has a plurality of package colloids respectively covered on the LED chips. Each package colloid has a colloid cambered surface and a colloid light-emitting surface respectively formed on a top surface and a front surface thereof.

Abstract: A method of making a semiconductor chip assembly includes providing a thermal post, a signal post and a base, mounting an adhesive on the base including inserting the thermal post into a first opening in the adhesive and the signal post into a second opening in the adhesive, mounting a conductive layer on the adhesive including aligning the thermal post with a first aperture in the conductive layer and the signal post with a second aperture in the conductive layer, then flowing the adhesive into and upward in a first gap located in the first aperture between the thermal post and the conductive layer and in a second gap located in the second aperture between the signal post and the conductive layer, solidifying the adhesive, then providing a conductive trace that includes a pad, a terminal, the signal post and a selected portion of the conductive layer, mounting a semiconductor device on a heat spreader that includes the thermal post and the base, electrically connecting the semiconductor device to the conduct

Abstract: The present invention relates to a process for producing an optical semiconductor device, the process including: disposing a sheet for optical-semiconductor-element encapsulation including a resin sheet A and a plurality of resin layers B discontinuously embedded in the resin sheet A and a plurality of optical semiconductor elements mounted on a substrate in such a way that each of the plurality of optical semiconductor elements faces either one of the plurality of resin layers B; and followed by embedding each of the plurality of optical semiconductor elements in either one of the plurality of resin layers B. According to the process of the invention, optical semiconductor elements can be embedded at once. As a result, an optical semiconductor device which is excellent in LED element protection and durability can be easily obtained. Consequently, the optical semiconductor device obtained can have a prolonged life.

Abstract: A method of manufacturing light emitting diode has steps of providing a package base, providing a light emitting structure and bonding the light emitting structure on the package base. The package base has a first metal layer and a second metal layer respectively formed on a top and a bottom thereon. The light emitting structure has a substrate, a light emitting lamination and a reflective metal layer. The light emitting lamination is formed on the substrate and has an n-type semiconductor layer, a light emitting layer, a p-type semiconductor layer and a transparent electrode layer deposited on the substrate in sequence. The reflective metal layer is formed on a bottom of the substrate. The first metal layer is connected to the reflective metal layer by an ultrasonic thermal press technique. Therefore, the thermal resistance of the finished LED reduces.

Abstract: In a semiconductor light emitting device, light is lost from a side surface of a substrate; therefore, if a substrate side surface occupies a large area, it decreases light extraction efficiency. The area of the substrate side surface may be reduced by reducing a thickness of the substrate. However, a thin substrate has low mechanical strength and is cracked by a stress during work process, and that decreases the yield. A light emitting layer is formed on a substrate. After fixed to a grinding board with wax, the substrate is ground to thin. A support substrate is then bonded to the substrate for reinforcement. The substrate is fixed to an electrode and others, with the support substrate bonded to the substrate. The support substrate is lastly removed.

Abstract: The present invention relates to a light emitting device and a method of manufacturing the light emitting device. According to the present invention, the light emitting device comprises a substrate, an N-type semiconductor layer formed on the substrate, and a P-type semiconductor layer formed on the N-type semiconductor layer, wherein a side surface including the N-type or P-type semiconductor layer has a slope of 20 to 80° from a horizontal plane.

Abstract: An organic electroluminescent device including an organic thin-film transistor element having at least an active layer made of an organic material; and an organic electroluminescent element driven by the organic thin-film transistor element.

Abstract: A pixel structure includes a substrate, a first and a second patterned conductive layers, and a pixel electrode. The first patterned conductive layer, disposed on the substrate, includes at least one scan line, at least one gate, and at least one common electrode line. The second patterned conductive layer, disposed on the first patterned conductive layer, includes at least one data line, at least one source/drain, and at least one first patterned layer partly disposed on the common electrode line. The pixel electrode, disposed on the second patterned conductive layer, includes at least one first part and one second part. The first part partly covers the first patterned layer and the common electrode line. The second part, connected to the source/drain, covers the other part of the first patterned layer. The first and second patterned layers compose at least one first capacitance.

Abstract: A method of manufacturing a pixel structure is provided. A first patterned conductive layer including a gate and a data line is formed on a substrate. A gate insulating layer is formed to cover the first patterned conductive layer and a semiconductor channel layer is formed on the gate insulating layer above the gate. A second patterned conductive layer including a scan line, a common line, a source and a drain is formed on the gate insulating layer and the semiconductor channel layer. The scan line is connected to the gate and the common line is located above the data line. The source and drain are located on the semiconductor channel layer, and the source is connected to the data line. A passivation layer is formed on the substrate to cover the second patterned conductive layer. A pixel electrode connected to the drain is formed on the passivation layer.

Abstract: The present invention provides a method of fabricating a light emitting diode chip having an active layer between an N type semiconductor layer and a P type semiconductor layer. The method comprises the steps of preparing a substrate; laminating the semiconductor layers on the substrate, the semiconductor layers having the active layer between the N type semiconductor layer and the P type semiconductor layer; and forming grooves on the semiconductor layers laminated on the substrate until the substrate is exposed, whereby inclined sidewalls are formed by the grooves in the semiconductor layers divided into a plurality of chips. According to embodiments of the present invention, a sidewall of a semiconductor layer formed on a substrate of a light emitting diode chip is inclined with respect to the substrate, whereby its directional angle is widened as compared with a light emitting diode chip without such inclination.

Abstract: A halftone mask includes a transparent substrate, a light-blocking layer, a first semi-transparent layer and a second semi-transparent layer. The transparent substrate includes a light-blocking area, a light-transmitting area, a first halftone area transmitting first light, and a second halftone area transmitting second light that is less than the first light. The light-blocking layer is formed in the light-blocking area to fully block light from being transmitted. The first and second semi-transparent layers are formed on the transparent substrate. At least one of the first and second semi-transparent layers is formed in the first halftone area, and the first and second semi-transparent layers are overlapped with each other on the second halftone area.

Abstract: An optical device and method is disclosed for forming the optical device within the wide-bandgap semiconductor substrate. The optical device is formed by directing a thermal energy beam onto a selected portion of the wide-bandgap semiconductor substrate for changing an optical property of the selected portion to form the optical device in the wide-bandgap semiconductor substrate. The thermal energy beam defines the optical and physical properties of the optical device. The optical device may take the form of an electro-optical device with the addition of electrodes located on the wide-bandgap semiconductor substrate in proximity to the optical device for changing the optical property of the optical device upon a change of a voltage applied to the optional electrodes. The invention is also incorporated into a method of using the optical device for remotely sensing temperature, pressure and/or chemical composition.

Abstract: A light emitting diode (LED) and a method of making the same are disclosed. The present invention uses a metal layer of high conductivity and high reflectivity to prevent the substrate from absorbing the light emitted. This invention also uses the bonding technology of dielectric material thin film to replace the substrate of epitaxial growth with high thermal conductivity substrate to enhance the heat dissipation of the chip, thereby increasing the performance stability of the LED, and making the LED applicable under higher current.

Abstract: A MEMS device such as an interferometric modulator includes an integrated ESD protection element capable of shunting to ground an excess current carried by an electrical conductor in the MEMS device. The protection element may be a diode and may be formed by depositing a plurality of doped semiconductor layers over the substrate on which the MEMS device is formed.

Abstract: The invention relates to a method for the compensation of deviations occurring as a result of manufacture in the manufacture of micromechanical elements and their use which should be deflected at a resonant frequency. It is therefore the object of the invention to compensate deviations which occur due to manufacture and which have an influence on the resonant frequency of micromechanical elements in a simple and cost-effective manner. In accordance with the invention, a procedure is followed such that additional trenches and/or recesses are formed at the deflectable element simultaneously with the forming of the trenches by dry etching with which at least one spring element, a deflectable element and optionally also a frame element of micromechanical elements are formed. The trenches and recesses can thereby be formed under the same respective process parameters at the respective micromechanical element or at all micromechanical elements of a batch.

Abstract: A micro-electro-mechanical system (MEMS) device includes a substrate, having a first side and second side, the second side has a cavity and a plurality of venting holes in the substrate at the second side with connection to the cavity. However, the cavity is included in option without absolute need. A structural dielectric layer has a dielectric structure and a conductive structure in the dielectric structure. The structural dielectric layer has a chamber in connection to the cavity by the venting holes. A suspension structure layer is formed above the chamber. An end portion is formed in the structural dielectric layer in fix position. A diaphragm has a first portion of the diaphragm fixed on the suspension structure layer while a second portion of the diaphragm is free without being fixed.

Abstract: Embodiments of the invention contemplate the formation of a high efficiency solar cell using novel methods to form the active doped region(s) and the metal contact structure of the solar cell device. In one embodiment, the methods include the steps of depositing a dielectric material that is used to define the boundaries of the active regions and/or contact structure of a solar cell device. Various techniques may be used to form the active regions of the solar cell and the metal contact structure.

Abstract: A method is disclosed for making a textured surface on a solar cell. At first, there is provided a solar cell with a P-type layer and an N-type layer. Then, a silicon quantum dot-silicon nitride film is provided on the solar cell by chemical vapor deposition. Then, the silicon quantum dot-silicon nitride film is etched. In a first phase, the etching of the silicon nitride is faster than that of the silicon quantum dots so that the silicon quantum dots are exposed, thus forming a transient textured surface on the silicon quantum dot-silicon nitride film. In a second phase, the etching of the silicon nitride is slower than that of the silicon quantum dots so that some of the silicon quantum dots are removed, thus leaving cavities in the silicon quantum dot-silicon nitride film, i.e., forming a final textured surface on the silicon quantum dot-silicon nitride film.

Abstract: A growth method is proposed for high quality zinc oxide comprising the following steps: (1) growing a gallium nitride layer on a sapphire substrate around a temperature of 1000° C.; (2) patterning a SiO2 mask into stripes oriented in the gallium nitride <1 100> or <11 20> direction; (3) growing epitaxial lateral overgrowth of (ELO) gallium nitride layers by controlling the facet planes via choosing the growth temperature and the reactor; (4) depositing zinc oxide films on facets ELO gallium nitride templates by chemical vapor deposition (CVD). Zinc oxide crystal of high quality with a reduced number of crystal defects can be grown on a gallium nitride template. This method can be used to fabricate zinc oxide films with low dislocation density lower than 104/cm?2, which will find important applications in future electronic and optoelectronic devices.

Abstract: Solar cells fabricated without gasification of metallurgical-grade silicon. The substrates are prepared by: melting metallurgical grade silicon in a furnace; solidifying the melted metallurgical grade silicon into an ingot; slicing the ingot to obtain a plurality of wafers; polishing and cleaning each wafer; depositing aluminum layer on backside of each wafer; depositing a layer of hydrogenated silicon nitride on front surface of each wafer; annealing the wafers at elevated temperature; removing the hydrogenated silicon nitride; and, removing the aluminum layer. The front surface may be textured prior to forming the solar cell. The solar cell structure comprises a metallurgical grade doped silicon substrate and a thin-film structure formed over the substrate to form a p-i-n junction with the substrate. The substrate may be doped p-type, and the thin film structure may be an intrinsic amorphous layer formed over the substrate and an n-type amorphous layer formed over the intrinsic layer.

Abstract: An improved lead foil operation procedure for photovoltaic module manufacture is disclosed. The procedure includes lift, cut, and fold lead foil.

Abstract: Materials, devices, and methods for enhancing performance of electronic devices such as solar cells, fuels cells, LEDs, thermoelectric conversion devices, and other electronic devices are disclosed and described. A diamond-like carbon electronic device can include a conductive diamond-like carbon cathode having specified carbon, hydrogen and sp2 bonded carbon contents. In some cases, the sp2 bonded carbon content may be sufficient to provide the conductive diamond-like carbon material with a visible light transmissivity of greater than about 0.70. A charge carrier separation layer can be coupled adjacent and between the diamond-like carbon cathode and an anode. The conductive diamond-like carbon material of the present invention can be useful for any other application which can benefit from the use of conductive and transparent electrodes which are also chemically inert, radiation damage resistance, and are simple to manufacture.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a base substrate; attaching a base device over the base substrate; attaching a leadframe having a leadframe pillar adjacent the base device over the base substrate; applying a base encapsulant over the base device, the base substrate, and the leadframe; and removing a portion of the base encapsulant and a portion of the leadframe providing the leadframe pillar partially exposed.

Abstract: A semiconductor device and a method for fabricating the same, including: a substrate having a mounting surface formed with a plurality of bonding fingers and covered with an insulating layer, the insulating layer having an opening formed therein for exposing the bonding fingers; and a chip coupled to the substrate and including a body, a self-adhesive protective layer, and a plurality of bumps protruding from the self-adhesive protective layer. The self-adhesive protective layer is formed on the chip but leaves the bumps exposed. The self-adhesive protective layer is made of a photosensitive adhesive, thermosetting adhesive, or dielectric material. The chip is coupled to the substrate via the self-adhesive protective layer, thus allowing the bumps to be electrically connected to the bonding fingers and at least an end of the opening to be exposed. The method enables a more streamlined manufacturing process and lower fabrication costs by dispensing with adhesive dispensing.

Abstract: A power module with low thermal resistance buffers the stress put on a substrate during a package molding operation to virtually always prevent a fault in the substrate of the module. The power module includes a substrate, a conductive adhesive layer formed on the substrate, a device layer comprising a support tab, a power device, and a passive device which are formed on the conductive adhesive layer, and a sealing material hermetically sealing the device layer. The support tab is buffers the stress applied by a support pin to the substrate, thereby virtually always preventing a ceramic layer included in the substrate from cracking or breaking. As a result, a reduction in the isolation breakdown voltage of the substrate is virtually always prevented and the failure of the entire power module is do to a reduction in the breakdown voltage of the substrate is virtually always prevented.

Abstract: A method and apparatus for improving the laminate performance of the solder balls in a BGA package. Specifically, the ball pads on the substrate are configured to increase the shear force necessary to cause delamination of the solder balls. Conductive traces extending planarly from the pads and arranged in specified configurations will increase the shear strength of the pad.

Abstract: An integrated circuit structure includes a bottom semiconductor chip; a top die bonded onto the bottom semiconductor chip; a protecting material encircling the bottom die and on the bottom semiconductor chip; and a planar dielectric layer over the top die and the protecting material. The protecting material has a top surface leveled with a top surface of the top die.

Abstract: A process comprises forming a first electrical interconnect structure on a surface of a singulated semiconductor chip having an alignment pattern, which is scanned and stored in a scanning device prior to application of a curable underfill coating to the surface of the singulated semiconductor chip. A curable underfill coating is applied to the surface of the singulated semiconductor chip to produce a coated semiconductor chip. The scanned and stored alignment pattern is delivered to an alignment and joining device positioned adjacent to and operatively associated with a substrate having a second electrical interconnect structure alignable to make electrical contact with the first electrical interconnect structure.

Abstract: The invention relates to the collective fabrication of n 3D module. It comprises a step of fabricating a batch of n dies i at one and the same thin plane wafer (10) of thickness es comprising silicon, covered on one face with electrical connection pads (20), called test pads, and then with a thin electrically insulating layer (4) of thickness ei, forming the insulating substrate provided with at least one silicon electronic component (11) having connection pads (2) connected to the test pads (20) through the insulating layer.

Abstract: Thermal management is provided for a device. The device may include a substrate having a mounting area on a first surface of the substrate. The device may also include first thermal vias extending from the mounting area to at least an interior of the substrate. The device may also include at least one thermal plane substantially parallel to the first surface of the substrate, the at least one thermal plane being in thermal contact with at least one of the first thermal vias. The device may also include a heat sink attachment area, and second thermal vias extending from the heat sink attachment area to the interior of the substrate, the at least one thermal plane being in thermal contact with the second thermal vias.

Abstract: A DFN semiconductor package includes a leadframe having a die bonding pad formed integrally with a drain lead, a gate lead and a source lead, a die coupled to the die bonding pad, a die source bonding area coupled to the source lead and a die gate bonding area coupled to the gate lead, and an encapsulant at least partially covering the die, drain lead, gate lead and source lead.

Abstract: Provided are a mask layout method and a semiconductor device and a method for fabricating the same. The semiconductor device can include a main pattern, a first dummy pattern, and a second dummy pattern. The main pattern can be disposed on a substrate. The first dummy pattern and the second dummy pattern can be disposed around a side of the main pattern. The first dummy pattern can have an inner open region. The second dummy pattern can be disposed on the inner open region of the first dummy pattern, such that the first dummy pattern surrounds the second dummy pattern.

Abstract: A method of manufacturing a semiconductor device includes preparing a substrate on which a fuze line containing copper is formed. The method further includes cutting the fuze line by emitting a laser beam, and applying a composition for etching copper to the substrate to finely etch a cutting area of the fuze line and to substantially remove at least one of a copper residue and a copper oxide residue remaining near the cutting area. The composition for etching copper includes about 0.01 to about 10 percent by weight of an organic acid, about 0.01 to 1.0 percent by weight of an oxidizing agent, and a protic solvent.

Abstract: A semiconductor device is fabricated by forming a first crystalline region by irradiating a laser beam to a first region of an amorphous semiconductor film by relatively moving the laser beam with respect to the first region of the amorphous semiconductor film. A second crystalline region is formed by irradiating the laser beam to a second region of the amorphous semiconductor film including a portion of the first crystalline region by relatively moving the laser beam with respect to the second region of the amorphous semiconductor film. The wavelength of the laser beam falls in a range of 370 rim through 650 nm. In general, crystalline performance of the first crystalline region, the second crystalline region, and a region of overlap between the first crystalline region and the second crystalline region are the same.

Abstract: A method for fabricating a semiconductor device comprises: performing a thermal process to expanding a local doped region formed between gate patterns on a semiconductor substrate; and etching a central region of an expanded local doped region so that the expanded local doped region remains at the total area of sidewalls of floating bodies isolated from each other.

Abstract: A stack including at least an insulating layer, a first electrode, and a first impurity semiconductor layer is provided over a supporting substrate; a first semiconductor layer to which an impurity element imparting one conductivity type is added is formed over the first impurity semiconductor layer; a second semiconductor layer to which an impurity element imparting the one conductivity type is added is formed over the first semiconductor layer under a condition different from that of the first semiconductor layer; crystallinity of the first semiconductor layer and crystallinity of the second semiconductor layer are improved by a solid-phase growth method to form a second impurity semiconductor layer; an impurity element imparting the one conductivity type and an impurity element imparting a conductivity type different from the one conductivity type are added to the second impurity semiconductor layer; and a gate electrode layer is formed via a gate insulating layer.

Abstract: Disclosed are embodiments of a method of forming, on an SOI wafer, a planar FET with embedded and faceted source/drain stressors. The method incorporates a directional ion implant process to create amorphous regions at the bottom surfaces of source/drain recesses in a single crystalline semiconductor layer of an SOI wafer. Then, an etch process selective to different crystalline planes over others and further selective to single crystalline semiconductor material over amorphous semiconductor material can be performed in order to selectively adjust the shape (i.e., the profile) of the recess sidewalls without increasing the depth of the recesses. Subsequently, an anneal process can be performed to re-crystallize the amorphous regions and an epitaxial deposition process can be used to fill the recesses with source/drain stressor material. Also disclosed are embodiments of a planar FET structure and a design structure for the planar FET.

Abstract: A method for manufacturing a diode-connected transistor includes forming a silicon layer on a substrate, a first insulation film on the silicon layer, and a gate electrode on the first insulation film. The method also includes forming a source region, a channel region, and a drain region in the silicon layer and forming a second insulation film on the gate electrode. A source electrode and a drain electrode are formed on the second insulation film and are coupled to the source region and the drain region, respectively. The method further includes coupling the drain electrode to the gate electrode through a contact hole that is vertically above the channel region.

Abstract: A method of forming a microelectronic device comprising, on a same support: at least one semi-conductor zone strained according to a first strain, and at least one semi-conductor zone strained according to a second strain, different to the first strain, comprising: the formation of semi-conductor zones above a pre-strained layer, then trenches extending through the thickness of the pre-strained layer, the dimensions and the layout of the semi-conductor zones as a function of the layout and the dimensions of the trenches being so as to obtain semi-conductor zones having a strain of the same type as that of the pre-strained layer and semi-conductor zones having a strain of a different type to that of the pre-strained layer.

Abstract: A method for fabricating a metal-oxide-semiconductor device structure. The method includes introducing a dopant species concurrently into a semiconductor active layer that overlies an insulating layer and a gate electrode overlying the semiconductor active layer by ion implantation. The thickness of the semiconductor active layer, the thickness of the gate electrode, and the kinetic energy of the dopant species are chosen such that the projected range of the dopant species in the semiconductor active layer and insulating layer lies within the insulating layer and a projected range of the dopant species in the gate electrode lies within the gate electrode. As a result, the semiconductor active layer and the gate electrode may be doped simultaneously during a single ion implantation and without the necessity of an additional implant mask.

Abstract: A semiconductor device includes a device isolation structure having a grounded conductive layer to define an active region, and a gate formed over the active region and the device isolation structure.

Abstract: A method of fabricating a strained silicon transistor is provided. Amorphous silicon is formed below the transistor region before the transistor is formed. By using the tensile/compressive strainer, amorphous silicon is recrystallized to form a strained silicon layer. In addition, the dopants in the well can be driven in and activated by using the same annealing process with the amorphous silicon recrystallization.

Abstract: A semiconductor device is made by forming a smooth conductive layer over a substrate. A first insulating layer is formed over a first surface of the smooth conductive layer. A first conductive layer is formed over the first insulating layer. A second insulating layer is formed over the first insulating layer and first conductive layer. The substrate is removed. A second conductive layer is formed over a second surface of the smooth conductive layer opposite the first surface of the smooth conductive layer. A third insulating layer is formed over the second conductive layer. The second conductive layer, smooth conductive layer, first insulating layer, and first conductive layer constitute a MIM capacitor. A portion of the second conductive layer includes an inductor. The smooth conductive layer has a smooth surface to reduce particles and hill-locks which decreases ESR, increases Q factor, and increases ESD of the MIM capacitor.