Abstract: The present invention provides an isolated regulating power converter with opto-coupled feedback of output (Vo) with respect to a reference level (Vset) for regulation to a converter controller. The sense of the feedback signal is such that the opto-coupler LED is ON when Vo<Vset and OFF when Vo>Vset with the effect that the LED current and power loss is zero during the times when Vo>Vset, as is normal case for many controllers at low or no load. This saves power under such circumstances. Additionally, as the LED does not load the output during this time, the proportion of time for which Vo>Vset is increased, meaning that the timing at which the switch must again be on to meet demand is extended, producing a further power saving.

Abstract: In a direct-current power supply device that includes a smoothing capacitor C1, which performs a DC/DC converter operation, a transformer T1, a switching element Q1, a diode D2, a smoothing capacitor C2, a reactor L1, which performs a PFC operation, a fast recovery diode D1 and a switching element Q1, when compared with the case of a rated load, the voltage of the smoothing capacitor C1 of a PFC circuit rises at a time when a load is light. Therefore, the following has been required: a capacitor having a sufficient withstanding voltage rating, or an operation of connecting a plurality of capacitors in series or any other operation to secure a voltage-withstanding capability.

Abstract: System and method for providing control for switch-mode power supply. According to an embodiment, the present invention provides a system for regulating a power converter. The system comprises a signal processing component that is configured to receive a first voltage and a second voltage, to process information associated with the first voltage and the second voltage, to determine a signal based on at least information associated with the first voltage and the second voltage, and to send the signal to a switch for a power converter. The switch is regulated based on at least information associated with the signal. The signal processing component is further configured to determine the signal to be associated a first mode, if the first voltage is higher than a first threshold.

Abstract: A three-phase power converter includes a converter configured to convert a three phase AC power input to a DC power output, the DC power output being provided to high and low sides of a DC bus, and an inverter coupled to the DC bus and configured to convert the DC power to a three phase AC output. The inverter comprises three legs and each leg comprises a pair of solid state switches and a respective output therebetween. The power converter further includes a common mode voltage control filter comprising three filter inputs and two filter outputs, each filter input coupled to an output of a respective leg of the inverter and each filter output coupled to a respective side of the DC bus.

Abstract: Variable frequency motor drives and control techniques are presented in which filter capacitor faults are detected by measuring filter neutral node current and/or voltages and detecting changes in the fundamental frequency component of the measured neutral condition at the fundamental frequency of the input power and/or based on input current unbalance.

Abstract: The present application discloses methods, circuits and systems for power conversion, using a universal multiport architecture. When a transient appears on the power input (which can be, for example, polyphase AC), the input and output switches are opened, and a crowbar switch shunts the inductance which is used for energy transfer. This prevents this inductance from creating an overvoltage when it is disconnected from outside lines.

Abstract: System and method for protecting a power converter. A system includes a threshold generator configured to generate a threshold signal, and a first comparator configured to receive the threshold signal and a first signal and to generate a comparison signal. The first signal is associated with an input current for a power converter. Additionally, the system includes a pulse-width-modulation generator configured to receive the comparison signal and generate a modulation signal in response to the comparison signal, and a switch configured to receive the modulation signal and adjust the input current for the power converter. The threshold signal is associated with a threshold magnitude as a function of time. The threshold magnitude increases with time at a first slope during a first period, and the threshold magnitude increases with time at a second slope during a second period. The first slope and the second slope are different.

Abstract: Systems and devices for reduction of total harmonic distortion in power supply circuits are presented. Example embodiments of the disclosed systems of total harmonic distortion reduction reduce a low frequency output voltage ripple seen by the voltage control loop by adding a compensating ripple voltage to the output feedback signal. The compensating signal may be scaled by the user to optimize the degree of ripple reduction, and may be automatically adjusted by monitoring circuitry to scale with a power factor control circuit output power level.

Abstract: In a power conversion device that includes a PWM converting means for generating a PWM pulse by comparing three-phase voltage commands with a triangular wave carrier signal, a power converter for converting between a DC voltage and a three-phase AC voltage by driving a switching element according to the PWM pulse, a current detecting means for detecting a pulsed current flowing through a DC bus conductor of a main circuit, and a voltage command correcting means for correcting three-phase voltage commands, which corrects the three-phase voltage commands so that a line voltage value between the maximum phase and an intermediate phase and a line voltage value between the intermediate phase and the minimum phase are each equal to or larger than a predetermined value, the maximum phase, intermediate phase, and minimum phase being determined in correspondence to momentary values of the three-phase voltage commands arranged in descending order, if the voltage command is outside an allowable upper limit or lower limi

Abstract: A method and apparatus for power conversion. In one embodiment, the apparatus comprises a DC-AC conversion stage; an intermediate capacitor coupled across the DC-AC conversion stage; and a burst mode controller coupled to the intermediate capacitor and the DC-AC conversion stage, wherein the burst mode controller (i) maintains a voltage of the intermediate capacitor below a preset limit during a storage period and (ii) drives the DC-AC conversion stage to convert DC input to AC output during a burst period, wherein the storage and burst periods occur during a burst mode operation.

Abstract: A synchronous rectifying circuit for a switching power converter is provided. The synchronous rectifying circuit includes a power transistor, a diode, and a control circuit. The power transistor and the diode are coupled to a transformer and an output of the power converter for rectification. The control circuit generates a drive signal to switch on the power transistor once the diode is forward biased. The control circuit includes a monitor circuit. The monitor circuit generates a monitor signal an off signal to switch off the power transistor in response to a pulse width of the drive signal for generating an off signal to switch off the power transistor. The monitor circuit further reduces the pulse width of the drive signal in response to a change of a feedback signal. The feedback signal is correlated to an output load of the power converter.

Abstract: A new class of Single-Stage AC-DC converters with built-in Isolation and PFC feature is introduced along with the companion hybrid switching conversion method. Several different converter topologies are introduced, which all feature three switches only, single magnetic component and low voltage stresses on all switches.

Abstract: A power supply topology is used in which a transistor is provided on the side of an output node of a rectifying circuit. An inductor is provided on the side of a reference node, a resistor is inserted between the transistor and the inductor, and one end of the resistor is coupled to a ground power supply voltage of a PFC circuit. The PFC circuit includes a square circuit which squares a result of multiplication of an input voltage detection signal and feedback information (output voltage of an error amplifier circuit). The PFC circuit drives on the transistor when a detection voltage developed at the resistor reaches zero, and drives off the transistor when the detection signal reaches an output signal of the square circuit.

Abstract: A method and apparatus for regulating an input voltage to a power conversion module. In one embodiment, the method comprises computing a voltage regulation threshold based on an output voltage for the power conversion module; comparing an input voltage of the power conversion module to the voltage regulation threshold; and generating, when the input voltage satisfies the voltage regulation threshold, an average input voltage less than the voltage regulation threshold, wherein the average input voltage is generated from the input voltage.

Abstract: A direct current regulated power supply includes a switch power supply, a power connector, and a control switch. The switch power supply is configured for receiving a main power and converting the received main power into direct current power to supply an electronic device. The power connector is electrically coupled to the switch power supply, and includes an enable pin. The control switch includes an input electrically coupled to the enable pin of the power connector, and an output that is grounded.

Abstract: A semiconductor memory apparatus includes: a memory cell array including a plurality of memory cells; a bit line sense amplifier (BLSA) coupled to the memory cells in the memory cell array through a bit line; a plurality of local input/output lines coupled to the BLSA; and a switching unit coupled to the local input/output lines and configured to select a part of the local input/output lines.

Abstract: A three-dimensional (3D) semiconductor device may include a stack of chips, including a master chip and one or more slave chips. I/O connections of slave chips need not be connected to channels on a motherboard, and only electrode pads of a master chip may be connected to the channels. Only the master chip may provide a load to the channels. A through-substrate via (TSV) boundary may be set on a data input path, a data output path, an address/command path, and/or a clock path of a semiconductor device in which the same type of semiconductor chips are stacked.

Abstract: A semiconductor device includes a sense amplifier circuit. The sense amplifier circuit includes a cross-coupled first transistor and second transistor that perform amplification. The sources of the cross-coupled transistors are respectively connected in series with a third transistor and a fourth transistor, and electrical current supply capability of the third and fourth transistors is controlled by a control voltage given to control electrodes of the third and fourth transistors. In a data retaining period, a minimum sub-threshold current necessary for retaining the data is flowed to the third and fourth transistors according to the control voltage, and bit line potential is maintained.

Abstract: A semiconductor device includes a first and a second ROMs; and a first control circuit having an input node and sets a first and a second addresses that are different each other to be respectively recorded in the first and second ROMs from a plurality of input addresses supplied sequentially into the input node, on the basis of a setting signal, the plurality of input addresses including the first and second addresses, wherein the first control circuit being configured to set an input address as the first address based on the setting signal, and the first control circuit further being configured to set an input address as the second address on the basis of the setting signal when the first and second addresses are different each other in a predetermined portion of bits after the first address is set to the first ROM.

Abstract: Techniques for encoding and decoding fuse data to reduce sense current are disclosed. An embodiment to encode fuse sense data includes inverting each of the bits of the fuse data and using an individual fuse as a flag bit to record the data inversion. The states of the respective fuses may represent different logic states. A fuse may be blown to indicate a logic one and likewise, an unblown fuse may indicate a logic zero. A blown fuse and an unblown fuse may have different current consumption. An unblown fuse may consume more sensing current compared to a blown fuse. Another embodiment to decode the encoded fuse data includes embedded logic circuits and a separate fuse as a flag bit. Encoding and decoding fuse data may reduce fuse sensing current.

Abstract: A method for reading a memory element within a crossbar array, the method including selecting a column line connected to a target memory element of the crossbar array by applying a supply voltage to a source follower, a gate terminal of the source follower connected to the column line; applying bias voltages to row lines of the crossbar array; storing an output voltage of the source follower in a storage element; applying a sense voltage to a row line connected to the target memory element; and outputting a difference between the voltage stored in the storage element and an output voltage of the source follower while the sense voltage is applied to the row line.

Abstract: A method for reading a memory element within a crossbar array includes switching a column line connected to a target memory element of the crossbar array to connected to an input of a current mirror; applying an error voltage to unselected rows of the crossbar array; applying a sense voltage to a row line connected to the target memory element; and measuring an output current of the current mirror.

Abstract: An apparatus and method of programming a spin-torque magnetoresistive memory array includes a metal reset line positioned near each of a plurality of magnetoresistive bits and configured to set the plurality of magnetoresistive memory elements to a known state by generating a magnetic field when an electrical current flows through it. A spin torque transfer current is then applied to selected ones of the magnetoresistive bits to switch the selected bit to a programmed state. In another mode of operation, a resistance of the plurality of bits is sensed prior to generating the magnetic field. The resistance is again sensed after the magnetic field is generated and the data represented by the initial state of each bit is determined from the resistance change. A spin torque transfer current is then applied only to those magnetoresistive bits having a resistance different from prior to the magnetic field being applied.

Abstract: A semiconductor memory device includes a memory cell array in which a plurality of memory cells is aligned in a matrix shape, each memory cell including a two-terminal memory element and a transistor for selection connected in series; a first voltage applying circuit that applies a writing voltage pulse to first bit lines; and a second voltage applying circuit that applies a pre-charge voltage to the first bit lines and second bit lines, wherein in a writing of a memory cell, after the second voltage applying circuit has pre-charged both ends of the memory cell to a same voltage, the first voltage applying circuit applies the writing voltage pulse via the first bit line that is directly connected to the transistor for selection, and the second voltage applying circuit applies the pre-charge voltage to the second bit line directly connected to the memory element.

Abstract: Apparatus and associated method for asymmetric write current compensation for resistive sense memory (RSM) cells, such as but not limited to spin-torque transfer random access memory (STRAM) or resistive random access memory (RRAM) cells. In accordance with some embodiments, an RSM cell includes an RSM element coupled to a switching device. The switching device has a plurality of terminals. A control circuit compensates for asymmetric write characteristics of the RSM cell by limiting a range of voltage differentials across the terminals so as to be equal to or less than a magnitude of a source voltage applied to the switching device, thereby providing bi-directional write currents of substantially equal magnitude through the RSM element.

Abstract: A semiconductor device may include, but is not limited to: a first memory cell; a first line; a second line; and a first capacitor. The first line is coupled to the first memory cell. The first line supplies a first voltage to the first memory cell. The second line is supplied with a fixed voltage. The first capacitor is coupled between the first and second lines.

Abstract: A non-volatile logic circuit includes an input section, a control section and an output section. The input section has perpendicular magnetic anisotropy and has a ferromagnetic layer whose magnetization state is changeable. The control section includes a ferromagnetic layer. The output section is provided in a neighborhood of the input section and the control section and includes a magnetic tunnel junction element whose magnetization state is changeable. The magnetization state of the input section is changed based on the magnetization state. A magnetization state of the magnetic tunnel junction element of the output section which state is changed based on the magnetization state of the ferromagnetic material of the control section and the magnetization state of the ferromagnetic material of the input section.

Abstract: A phase-change memory device includes: a cell array including at least one unit cell; a current sensing unit sensing data stored in the at least one unit cell; and a power generation circuit supplying a power source voltage to the current sensing unit, in which the power generation circuit is activated while the current sensing unit is performing a sensing operation.

Abstract: A phase-change memory device includes: a unit cell including a phase-change resistor; a sense amplifier applying a sensing current to the phase-change resistor; and a switching unit operating in a standby mode or a read mode according to a global line signal and controlling passing presence of the sensing current passing through the phase-change resistor according to an active signal in the standby mode.

Abstract: The leakage current and power consumption of phase change memories may be reduced using adaptive word line biasing. Depending on the particular voltage applied to the bitline of a programmed cell, the word lines of unselected cells may vary correspondingly. In some embodiments, the word line voltage may be caused to match the bitline voltage of the programmed cell.

Abstract: A highly reliable large capacity phase change memory module is realized. A semiconductor device according to the present invention includes a memory array having a structure in which a storage layer using a chalcogcnidc material and a memory cell constituted of a diode are stacked, and an initialization condition and a rewriting condition are changed in accordance with the layer where a selected memory cell is located. A current mirror circuit is selected in accordance with an operation, and at the same time, the initialization condition and the rewriting condition (here, reset condition) are changed in accordance with the operation by a control mechanism of the reset current in a voltage selection circuit and a current mirror circuit.

Abstract: The present invention discloses a DRAM cell utilizing floating body effect and a manufacturing method thereof. The DRAM cell includes a P type semiconductor region provided on a buried oxide layer, an N type semiconductor region provided on the P type semiconductor region, a gate region provided on the N type semiconductor region, and an electrical isolation region surrounding the P type semiconductor region and the N type semiconductor region. A diode of floating body effect is taken as a storage node. Via a tunneling effect between bands, electrons gather in the floating body, which is defined as a first storage state; via forward bias of PN junction, electrons are emitted out from the floating body or holes are injected into the floating body, which is defined as a second storage state.

Abstract: Nonvolatile memory devices, memory systems and related methods of operating nonvolatile memory devices are presented. During a programming operation, the nonvolatile memory device is capable of using bit line forcing, and is also capable of selecting a verification mode for use during a verification operation from a group of verification modes on the basis of an evaluated programming condition.

Abstract: A programming method for a nonvolatile memory device includes performing a LSB programming operation programming all LSB logical pages, and thereafter performing a MSB programming operation programming all MSB logical pages, wherein during the LSB programming operation a selected MLC is programmed to a negative intermediate program state. A program sequence for the LSB and MSB programming operations may be sequential or non-sequential in relation to an order arranged of word lines.

Abstract: Provided are a nonvolatile memory device and a read method of the same. The read method applying one of a plurality of unselected read voltages to unselected wordlines adjacent to a selected word line. The voltage applied to the unselected word lines being based on which of a plurality of selected read voltages is applied to the selected wordline.

Abstract: An electrically alterable non-volatile multi-level memory device and a method of operating such a device, which includes setting a status of at least one of the memory cells to one state selected from a plurality of states including at least first to fourth level states, in response to information to be stored in the one memory cell, and reading the status of the memory cell to determine whether the read out status corresponds to one of the first to fourth level states by utilizing a first reference level set between the second and third level states, a second reference level set between the first and second level states and a third reference level set between the third and fourth level states.

Abstract: A reading method for a multi-level cell (MLC) memory includes the following steps. A number of word line voltages are sequentially provided to an MLC memory cell. A number of bit line voltages corresponding to the word line voltages are sequentially provided to the MLC memory cell. One of the word line voltages is higher than another one of the word line voltages, and one of the bit line voltages corresponding to the one of the word line voltages is lower than another one of the bit line voltages corresponding to the another one of the word line voltages.

Abstract: A method of controlling a non-volatile memory device includes comparing the number of banks that are in operating states with a threshold value. If the number of the banks is smaller than the threshold value, data stored in a standby bank is read. If there is no bank having data to be read, a standby bank is programmed. If the number of the banks is equal to or greater than the threshold value or if the reading or the programming is performed, it is determined whether there is a reading or programming command to be performed. If there is the reading or programming command to be performed, the process is repeated from the comparing step. The programming may include programming of a most significant bit (MSB) page or a least significant bit (LSB) page.

Abstract: Various embodiments of a semiconductor integrated circuit apparatus are disclosed. In one exemplary embodiment, the apparatus may include a memory cell array having a plurality of memory cell blocks, a plurality of word line selection sections corresponding to the plurality of memory cell blocks, a block selection unit configured to provide a driving signal to the plurality of word line selection sections for driving the plurality of memory cell blocks, and a plurality of global line groups, each corresponding to one of the plurality of word line selection sections. Each of the global line groups may include a plurality of signal lines configured to provide a voltage signal to the corresponding word line selection section.

Abstract: Nonvolatile memory devices include an electrically insulating layer on a semiconductor substrate and a NAND-type string of nonvolatile memory cells on an upper surface of the electrically insulating layer. The NAND-type string of nonvolatile memory cells includes a plurality of vertically-stacked nonvolatile memory cell sub-strings disposed at side-by-side locations on the electrically insulating layer. A string selection transistor is provided, which includes a gate electrode extending between the electrically insulating layer and the semiconductor substrate and source and drain regions in the semiconductor substrate. A ground selection transistor is provided, which includes a gate electrode extending between the electrically insulating layer and the semiconductor substrate and source and drain regions in the semiconductor substrate.

Abstract: A NAND Flash memory device reduces circuitry noise during program operations. The memory includes bit lines that are electrically coupled together to charge share their respective voltage potentials prior to performing a discharge operation on the bit lines. A NAND flash cell is programmed by coupling a first memory array bit line to a program voltage to program the memory cell, biasing a second memory array bit line to a ground potential, wherein the second memory array bit line is located adjacent to the first memory array bit line, activating at least one first transistor to electrically coupling the first and second memory array bit lines together, and activating at least one second transistor to electrically couple the first and second memory array bit lines to a discharge potential.

Abstract: A programmable CMOS device includes a PFET and an NFET that have a common floating gate. Depending on the configuration, the programmable CMOS device can be programmed, erased, and re-programmed repeatedly. The programming, erasure, and/or reprogramming can be effected by injection of electrons and/or holes into the floating gate. The programmable CMOS device can be employed as a fuse or an antifuse, to program a floating gate of another device, and/or to function as a latch. The programmable CMOS device can be formed employing standard logic compatible processes, i.e., without employing any additional processing steps.

Abstract: A method of programming a semiconductor device includes performing an initial program operation on all memory cells included in a selected memory cell block to set threshold voltages of all the memory cells to a voltage equal to or greater than 0 Volts, erasing memory cells of a selected page in the selected memory cell block, and programming the memory cells of the selected page.

Abstract: A nonvolatile memory device includes one or more reference cell transistors, one or more memory cell transistors, and a current source circuit including three or more field effect transistors that have gates thereof connected together, the three or more field effect transistors including two or more field effect transistors and another field effect transistor, currents flowing through the two or more field effect transistors being combined to flow through the one or more reference cell transistors, and another field effect transistor having a drain thereof connected to one of the one or more memory cell transistors.

Abstract: According to one embodiment, a semiconductor memory device includes a plurality of memory cells in which data can be rewritable, a plurality of bit lines connected to the plurality of memory cells, and a plurality of sense circuits that are connected to the plurality of bit lines, respectively, sense data written in the memory cells to perform a verify operation with the bit lines charged to first potentials, and charge a bit line, which is connected to a memory cell determined to be defective as a result of the verify operation, to the first potential in the verify operation.

Abstract: A nonvolatile memory apparatus includes: a plurality of drain selection switches coupled to a plurality of memory cell strings, respectively; and a drain selection switch controller configured to selectively drive a drain selection switch coupled to an even bit line or a drain selection switch coupled to an odd bit line, in response to a page address and a global drain selection signal.

Abstract: A NAND-based NOR flash memory array has a matrix of NAND-based NOR flash cells arranged in rows and columns. Every two adjacent NAND-based NOR flash cells in a column share a common source node which is connected to a common source line through a diode. The source line may be made of a metal layer and is in contact directly with the source node or through an ohmic contact to form a Schottky barrier diode. The source line may also be made of a polysilicon or metal layer and connected to the source node through a pillar-structured polysilicon diode and a conduction layer. The diode may also be formed in the source node by enclosing a P/N+ junction diode in a heavily N+ doped region of the source node.

Abstract: A semiconductor memory device includes a data alignment unit configured to align data, which are sequentially inputted, in response to a data strobe signal, a latching operation control unit configured to receive the data strobe signal, and generate a latching control signal after an interval between a write operation and a next write operation elapses, a data latching unit configured to latch output signals of the data alignment unit in response to the latching control signal, and a data synchronization output unit configured to synchronize output signals of the data latching unit in response to a data input strobe signal, and output the synchronized signals to a plurality of data lines.

Abstract: A semiconductor device includes a data alignment unit configured to align serial input data in response to a data strobe signal, a data latching unit configured to latch an output signal of the data alignment unit in response to first and second synchronization pulse signals which are activated according to BL information during a write operation, and a data output unit configured to output an output signal of the data latching unit to a plurality of global data lines in response to a data input strobe signal corresponding to the BL information.

Abstract: A memory apparatus includes a plurality of first bit columns for constructing a common memory space and at least one reserve second bit column. A column address of a damaged first bit column is recorded as a predetermined column address. When a byte column is accessed, data recorded in the first bit columns and the second bit columns are respectively latched in a first latching device and a second latching device. In the event that the latched access data is accessed, data is outputted by comparing the predetermined column address of each first bit column and an access column address, and when the access column address matches with the predetermined column address, data is outputted via the second latching device; otherwise, the data is outputted via the first latching device.