Patents Issued in March 6, 2012
  • Patent number: 8129825
    Abstract: In one embodiment of the present invention, an IC chip mounting package includes a film base member and an IC chip connected via an interposer. Connecting terminals on the film base member side of the interposer are provided so as to have a pitch larger than that of connecting terminals of the IC. A device hole is opened to the film base member, and the IC chip is provided in the device hole. A distance between an inner lead leading end and a periphery of the device hole is set as not less than 10 ?m.
    Type: Grant
    Filed: November 30, 2007
    Date of Patent: March 6, 2012
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Satoru Kudose, Tomokatsu Nakagawa, Tatsuya Katoh
  • Patent number: 8129826
    Abstract: Provided is a semiconductor package apparatus having a redistribution layer. The apparatus includes at least one or more semiconductor chips, a packing part protecting the semiconductor chips, and a support part supporting the semiconductor chips. The apparatus also includes external terminals extending outside the packing part, redistribution layers installed between the semiconductor chips and the support part and including redistribution paths, first signal transmitting units, and second signal transmitting units. The first signal transmitting units transmitting electrical signals generated from the semiconductor chips to the redistribution paths of the redistribution layers, and the second signal transmitting units transmit the electrical signals from the redistribution paths to the external terminals. Therefore, a size and a thickness of the semiconductor package apparatus can be reduced, and processes can be simplified to improve productivity.
    Type: Grant
    Filed: January 16, 2009
    Date of Patent: March 6, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Wook Park, Min-Young Son, Hyeong-Seob Kim
  • Patent number: 8129827
    Abstract: An integrated circuit package system includes: forming an external interconnect; connecting an integrated circuit die and the external interconnect; forming a package encapsulation, having a recess, covering the integrated circuit die with a portion of the external interconnect exposed by the recess; and connecting an integrated circuit device and the external interconnect in the recess.
    Type: Grant
    Filed: September 13, 2007
    Date of Patent: March 6, 2012
    Assignee: Stats Chippac Ltd.
    Inventors: Zigmund Ramirez Camacho, Jeffrey D. Punzalan, Jairus Legaspi Pisigan, Abelardo Jr Hadap Advincula
  • Patent number: 8129828
    Abstract: A wiring substrate assembly includes a resin wiring substrate and a reinforcement member. The resin wiring substrate does not have a core substrate, and includes a substrate main surface, a substrate back surface, a laminate structure comprised of resin insulation layers and conductive layers, and connection terminals disposed on the substrate main surface, to which a chip component is connectable. The reinforcement member is bonded to the substrate main surface and defines an opening portion extending through the reinforcement member so as to expose the main-surface-side connection terminals. The reinforcement member comprises a composite material including a resin material containing an inorganic material.
    Type: Grant
    Filed: September 28, 2009
    Date of Patent: March 6, 2012
    Assignee: NGK Spark Plug Co., Ltd.
    Inventor: Shinnosuke Maeda
  • Patent number: 8129829
    Abstract: A packaging substrate with an embedded photosensitive semiconductor chip and a method for fabricating the same are provided. The method includes the steps of: disposing the semiconductor chip in an through cavity of a core board with the photosensitive portion of the semiconductor chip being exposed from the through cavity; forming a first circuit layer on the core board at a side opposite to the photosensitive portion so as to electrically connect the electrode pads of the semiconductor chip; and forming a light-permeable layer on the core board at the same side with the photosensitive portion via an adhesion layer so as to allow light to penetrate through the light-permeable layer and reach the photosensitive portion of the semiconductor chip. When fabricated by the method, the packaging substrate dispenses with conductive wires and a surrounding dam and thus is efficiently downsized.
    Type: Grant
    Filed: June 12, 2009
    Date of Patent: March 6, 2012
    Assignee: Unimicron Technology Corp.
    Inventors: Shin-Ping Hsu, Kan-Jung Chia
  • Patent number: 8129830
    Abstract: An electronic component package, includes a package substrate portion constructed by a silicon substrate in which a through hole is provided, an insulating layer formed on both surface sides of the silicon substrate and an inner surface of the through hole, and a through electrode filled in the through hole, and a frame portion provided upright on a peripheral portion of the package substrate portion to constitute a cavity on the silicon substrate, wherein an upper surface of the through electrode in the cavity is planarized such that a height of the through electrode is set equal to a height of the insulating layer. The frame portion is joined to the package substrate portion by the low-temperature joining utilizing the plasma process after the through electrode is planarized.
    Type: Grant
    Filed: May 1, 2008
    Date of Patent: March 6, 2012
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventor: Kei Murayama
  • Patent number: 8129831
    Abstract: A chip arrangement includes semiconductor chips coupled to opposing sides of an insulating layer. The arrangement includes a first semiconductor chip having a first chip surface presenting a first chip conductive region. An electrically insulating layer includes a first layer surface presenting a first layer conductive region, and a second, opposing surface presenting a second layer conductive region. The electrically insulating layer is coupled to the first semiconductor chip by applying the first layer conductive region to the first chip conductive region. The electrically insulating layer is then coupled to the second chip conductive region by applying the second layer conductive region to the second chip conductive region.
    Type: Grant
    Filed: February 16, 2007
    Date of Patent: March 6, 2012
    Assignee: Infineon Technologies AG
    Inventors: Joachim Mahler, Alfred Haimerl, Michael Bauer
  • Patent number: 8129832
    Abstract: A mountable integrated circuit package system includes: providing a carrier; mounting a first integrated circuit device over the carrier; mounting a substrate over the first integrated circuit device with the substrate having a conductor-free recess; connecting a first electrical interconnect under the conductor-free recess electrically connecting the carrier and the first integrated circuit device; and forming a package encapsulation over the carrier, the first integrated circuit device, the first electrical interconnect, the conductor-free recess, and partially exposing the substrate.
    Type: Grant
    Filed: October 29, 2007
    Date of Patent: March 6, 2012
    Assignee: Stats Chippac Ltd.
    Inventors: Flynn Carson, In Sang Yoon, SeongMin Lee, JoHyun Bae
  • Patent number: 8129833
    Abstract: Microelectronic packages are fabricated by stacking integrated circuits upon one another. Each integrated circuit includes a semiconductor layer having microelectronic devices and a wiring layer on the semiconductor layer having wiring that selectively interconnects the microelectronic devices. After stacking, a via is formed that extends through at least two of the integrated circuits that are stacked upon one another. Then, the via is filled with conductive material that selectively electrically contacts the wiring. Related microelectronic packages are also described.
    Type: Grant
    Filed: October 27, 2009
    Date of Patent: March 6, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Pil-kyu Kang, Jung-Ho Kim, Jong-Wook Lee, Seung-woo Choi, Dae-Lok Bae
  • Patent number: 8129834
    Abstract: A plurality of FPGA dice is disposed upon a semiconductor substrate. In order to supply the immense power required by the plurality of FPGA dice, power is routed through the semiconductor substrate vertically from thick metal layers and large integral metal structures located on the other side of the semiconductor substrate. Because the semiconductor substrate has a different coefficient of thermal linear expansion than metal layers in contact with the substrate, delamination may occur when the structure is subject to changes in temperature. To prevent delamination of metal layers connected to the semiconductor substrate and in electrical contact with the integral metal structures, the integral metal structures are manufactured with an array of post portions. During changes in temperature, the post portions of the integral metal structures bend and slide relative to metal layers connected to the semiconductor substrate and prevent linear stresses that may otherwise cause delamination.
    Type: Grant
    Filed: January 26, 2009
    Date of Patent: March 6, 2012
    Assignee: Research Triangle Institute
    Inventor: Robert O. Conn
  • Patent number: 8129835
    Abstract: A package substrate having a semiconductor component embedded therein and a method of fabricating the same are provided, including: providing a semiconductor chip with electrode pads disposed on an active surface thereof; forming a passivation layer on the active surface and the electrode pads; forming on the passivation layer metal pads corresponding in position to the electrode pads, respectively, so as for the semiconductor chip to be fixed in position to an opening of a substrate body; forming a first dielectric layer on the semiconductor chip and the substrate body; forming dielectric layer openings by laser and preventing the electrode pads from being penetrated by the metal pads; removing the metal pads and the passivation layer in the dielectric layer openings so as to expose the electrode pads therefrom; and forming a first wiring layer on the first dielectric layer for electrical connection with the electrode pads.
    Type: Grant
    Filed: September 4, 2009
    Date of Patent: March 6, 2012
    Assignee: Unimicron Technology Corp.
    Inventor: Kan-Jung Chia
  • Patent number: 8129836
    Abstract: A semiconductor device is composed of a pair of semiconductor chips (402, 404) arranged parallel on the same flat plane; a high voltage bus bar (21) bonded on the surface on the collector side of one semiconductor chip (402); a low voltage bus bar (23) connected to the surface on the emitter side of the other semiconductor chip (404) with a bonding wire (27); a first metal wiring board (24-1) connected to the surface on the emitter side of the semiconductor chip (402) with a bonding wire (26); a second metal wiring board (24-2) bonded on the surface on the collector side of the semiconductor chip (404); a third metal wiring board (24-3) connected to the first metal wiring board (24-1); a fourth metal wiring board (24-4) connected by being bent from an end portion of the second metal wiring board (24-2); and an output bus bar (24) having output terminals (405) extending from each end portion of the third metal wiring board (24-3) and that of the fourth metal wiring board (24-4).
    Type: Grant
    Filed: May 17, 2007
    Date of Patent: March 6, 2012
    Assignee: Honda Motor Co., Ltd.
    Inventors: Fumitomo Takano, Shinya Watanabe, Tsukasa Aiba, Hiroshi Otsuka, Joji Nakashima
  • Patent number: 8129837
    Abstract: A flip chip interconnect pad layout has the die signal pads are arranged on the die surface near the perimeter of the die, and the die power and ground pads arranged on the die surface inboard from the signal pads; and has the signal pads on the corresponding package substrate arranged in a manner complementary to the die pad layout and the signal lines routed from the signal pads beneath the die edge away from the die footprint, and has the power and ground lines routed to vias beneath the die footprint. Also, a flip chip semiconductor package in which the flip chip interconnect pad layouts have the die signal pads situated in the marginal part of the die and the die power and ground pads arranged on the die surface inboard from the signal pads, and the corresponding package substrates have signal pads arranged in a manner complementary to the die pad layout and signal lines routed from the signal pads beneath the die edge away from the die footprint.
    Type: Grant
    Filed: April 29, 2009
    Date of Patent: March 6, 2012
    Assignee: STATS ChipPac, Ltd.
    Inventor: Rajendra D. Pendse
  • Patent number: 8129838
    Abstract: A microstructured component with microsensors or other active microcomponent is provided. The microstructured component includes a substrate and at least one housing arranged on the substrate with one or more active microstructures situated on it.
    Type: Grant
    Filed: May 14, 2008
    Date of Patent: March 6, 2012
    Assignee: Fraunhofer-Gesellschaft Zur
    Inventor: Wolfgang Reinert
  • Patent number: 8129839
    Abstract: A sealing layer is provided on a surface of a substrate, such as a semiconductor wafer. The sealing layer includes apertures which expose external contact locations for semiconductor dice formed on the wafer. Solder paste is deposited in the apertures and reflowed to form discrete conductive elements for attachment of electronic devices to higher level circuit structures. The wafer is then divided or “singulated” to provide individual semiconductor dice having their active surfaces covered by the sealing layer. In this manner, the sealing layer initially acts as a stencil for forming the discrete conductive elements and subsequently forms a chip scale package structure to protect the semiconductor dice from the environment.
    Type: Grant
    Filed: July 19, 2005
    Date of Patent: March 6, 2012
    Assignee: Micron Technology, Inc.
    Inventor: Warren M. Farnworth
  • Patent number: 8129840
    Abstract: A semiconductor package and a method of manufacturing the semiconductor package. The semiconductor package include a substrate including a plurality of pads and a plurality of bumps evenly disposed on an entire region of the substrate regardless of an arrangement of the plurality of pads. According to the present invention, a simplification of a process can be accomplished, a cost of a process can be reduced, reliability can be improved and an under-filling can become easy.
    Type: Grant
    Filed: July 15, 2009
    Date of Patent: March 6, 2012
    Assignee: SAMSUNG Electronics Co., Ltd.
    Inventors: Chajea Jo, Uihyoung Lee, Jae-hyun Phee, Jeong-Woo Park, Ha-Young Yim
  • Patent number: 8129841
    Abstract: A flip chip interconnect has a tapering interconnect structure, and the area of contact of the interconnect structure with the site on the substrate metallization is less than the area of contact of the interconnect structure with the die pad. Also, a bond-on-lead or bond-on-narrow pad or bond on a small area of a contact pad interconnection includes such tapering flip chip interconnects. Also, methods for making the interconnect structure include providing a die having interconnect pads, providing a substrate having interconnect sites on a patterned conductive layer, providing a bump on a die pad, providing a fusible electrically conductive material either at the interconnect site or on the bump, mating the bump to the interconnect site, and heating to melt the fusible material.
    Type: Grant
    Filed: November 24, 2009
    Date of Patent: March 6, 2012
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Rajendra D. Pendse, KyungOe Kim, TaeWoo Kang
  • Patent number: 8129842
    Abstract: The present invention provides a semiconductor interconnect structure with improved mechanical strength at the capping layer/dielectric layer/diffusion barrier interface. The interconnect structure has Cu diffusion barrier material embedded in the Cu capping material. The barrier can be either partially embedded in the cap layer or completely embedded in the capping layer.
    Type: Grant
    Filed: January 19, 2009
    Date of Patent: March 6, 2012
    Assignee: International Business Machines Corporation
    Inventors: Chih-Chao Yang, Mukta Ghate Farooq, Keith Kwong Hon Wong, Haining Yang
  • Patent number: 8129843
    Abstract: Plasma damage in ultra low k dielectric materials during formation of a dual damascene metal interconnect structure is reduced by providing a protective spacer on sidewalls of a line trench. A densified trench bottom region may be additionally formed directly beneath an exposed horizontal surface of the line trench. The protective spacer and/or the densified trench bottom region protects an ultra low k intermetal dielectric layer from plasma damage during a plasma strip process that is used to remove a disposable via fill plug employed in the dual damascene metal interconnect structure.
    Type: Grant
    Filed: August 10, 2010
    Date of Patent: March 6, 2012
    Assignee: International Business Machines Corporation
    Inventors: John C. Arnold, Sampath Purushothaman, Muthumanickam Sankarapandian, Hosadurga K. Shobha, Terry A. Spooner
  • Patent number: 8129844
    Abstract: Electronic devices and design structures of electronic devices containing metal silicide layers. The devices include: a thin silicide layer between two dielectric layers, at least one metal wire abutting a less than whole region of the silicide layer and in electrical contact with the silicide layer.
    Type: Grant
    Filed: June 20, 2008
    Date of Patent: March 6, 2012
    Assignee: International Business Machines Corporation
    Inventors: Felix Patrick Anderson, Zhong-Xiang He, Thomas Leddy McDevitt, Eric Jeffrey White
  • Patent number: 8129845
    Abstract: A semiconductor wafer includes a plurality of semiconductor die. Contact pads are formed on an active area of the semiconductor die and non-active area of the semiconductor wafer between the semiconductor die. Solder bumps are formed on the contact pads in both the active area of the semiconductor die and non-active area of the semiconductor wafer between the semiconductor die. The I/O terminal count of the semiconductor die is increased by forming solder bumps in the non-active area of the wafer. An encapsulant is formed over the solder bumps. The encapsulant provides structural support for the solder bumps formed in the non-active area of the semiconductor wafer. The semiconductor wafer undergoes grinding after forming the encapsulant to expose the solder bumps. The semiconductor wafer is singulated to separate the semiconductor die. The semiconductor die is mounted to a package substrate with solder paste or socket.
    Type: Grant
    Filed: September 9, 2008
    Date of Patent: March 6, 2012
    Assignee: STATS ChipPAC, Ltd.
    Inventors: TaeHoan Jang, JaeHun Ku, XuSheng Bao
  • Patent number: 8129846
    Abstract: A board adapted to mount an electronic device includes an insulating resin layer, a wiring layer of a predetermined pattern provided on one surface of the insulating resin layer, a bump electrode provided on an insulating-resin-layer-side surface of the wiring layer, and a covering, formed of a metal layer, which covers a top surface of the bump electrode and a region, at a side surface of the bump electrode, continuous with the top surface excluding a region in contact with the wiring layer.
    Type: Grant
    Filed: November 7, 2008
    Date of Patent: March 6, 2012
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Tetsuya Yamamoto, Yoshio Okayama, Yasuyuki Yanase
  • Patent number: 8129847
    Abstract: An interconnect for mounting an electronic device to a substrate includes a base layer between the electronic device and the substrate in electrical communication with integrated circuits on the electronic device, a phase change layer on the base layer made of a material which is liquid at normal operating temperatures of the electronic device and a retaining layer surrounding the phase change layer, and configured to retain the phase change layer in liquid form on the base layer.
    Type: Grant
    Filed: November 10, 2009
    Date of Patent: March 6, 2012
    Inventor: Warren M. Farnworth
  • Patent number: 8129848
    Abstract: Disclosed are a light emitting device having a plurality of light emitting cells connected in series and a method of fabricating the same. The light emitting device includes a buffer layer formed on a substrate. A plurality of rod-shaped light emitting cells are located on the buffer layer to be spaced apart from one another. Each of the light emitting cells has an n-layer, an active layer and a p-layer. Meanwhile, wires connect the spaced light emitting cells in series or parallel. Accordingly, arrays of the light emitting cells connected in series are connected to be driven by currents flowing in opposite directions. Thus, there is provided a light emitting device that can be directly driven by an AC power source.
    Type: Grant
    Filed: April 30, 2010
    Date of Patent: March 6, 2012
    Assignee: Seoul Opto Device Co., Ltd.
    Inventor: Chung Hoon Lee
  • Patent number: 8129849
    Abstract: Disclosed are a semiconductor package and a method of making the same. In the semiconductor package, a substrate and a semiconductor die are covered with and encapsulated by vertically pressing thermosetting resin having fluidity in a predetermined temperature range and denaturalizing itself in gel. Thus, it is possible to reduce a thickness of the semiconductor package and prevent wire sweeping.
    Type: Grant
    Filed: October 28, 2009
    Date of Patent: March 6, 2012
    Assignee: Amkor Technology, Inc.
    Inventors: Youn Sang Kim, Bong Chan Kim, Yoon Joo Kim
  • Patent number: 8129850
    Abstract: A solar wind chime having a structure that supports a solar energy system, a electrical subsystem, a cage, and a chime. The solar energy system includes a rechargeable electrical power source conductively coupled to a solar energy collection system. The rechargeable electrical power source powers one or more electrical subsystems. The electrical subsystem having at least one light for illuminating the solar wind chime. The cage is configured for protecting an ornamental object. The chime includes a bracket disposed within the chime. A wire extends through the chime and is at least partially supported by the bracket.
    Type: Grant
    Filed: January 16, 2009
    Date of Patent: March 6, 2012
    Assignee: World Factory, Inc.
    Inventors: Gregory G. Kuelbs, Gustav P. Kuelbs
  • Patent number: 8129851
    Abstract: In a wind power generation system, an energy consuming unit is connected to a DC part of a generator-side converter. A shunt circuit is connected between the generator-side converter and a rotor of an AC-excited power generator. In the event of system failure, the switching operation of the converter is stopped, the shunt circuit is put into operation, and the energy consuming unit is put into operation so that DC voltage (voltage of the DC part) is maintained within a prescribed range.
    Type: Grant
    Filed: June 2, 2008
    Date of Patent: March 6, 2012
    Assignee: Hitachi, Ltd.
    Inventors: Masaya Ichinose, Motoo Futami, Hiromitsu Sakai, Kojiro Yamashita
  • Patent number: 8129852
    Abstract: A wave and wind power generation system including a platform and one or more oscillating water columns (OWC's). Included is an airflow control mechanism, a controller and a motion sensor for detecting motion of the platform. Additionally, the controller controls the airflow control mechanism so as to at least partially arrest undesirable motion of the platform.
    Type: Grant
    Filed: October 2, 2007
    Date of Patent: March 6, 2012
    Assignee: ITI Scotland Limited
    Inventors: James Ian Edwards, Peter Thomas Diver
  • Patent number: 8129853
    Abstract: In one embodiment, the present invention includes a turbine to generate mechanical energy from kinetic energy, a generator coupled to the turbine to receive the mechanical energy and to output multiple isolated supply powers, and multiple power stages each coupled to the generator. Each of the power stages may receive at least one of the isolated supply powers.
    Type: Grant
    Filed: June 30, 2010
    Date of Patent: March 6, 2012
    Assignee: TECO-Westinghouse Motor Company
    Inventors: Mehdi Abolhassani, Thomas Keister, Haran Karmaker, Ryan Edwards, Enrique Ledezma, Alex Skorcz
  • Patent number: 8129854
    Abstract: An ocean wave energy extractor includes a first flotation device that contains a second flotation device and a mechanism for extracting energy. The wave energy extractor floats in seawater and extracts energy from waves. A propagating wave rotates the first flotation device relative to the second flotation device. The mechanism is connected to both flotation devices and generates energy from this relative rotation. In one example, a first flotation device includes a spherical chamber with a flotation collar, and a second flotation device supported by a joint at a center of the chamber. A wave approaching from any direction rotates the first flotation device relative to the second flotation device, and a mechanism for extracting energy generates electrical energy from the relative rotation. The chamber shields inner components from seawater and adverse ocean conditions. The wave energy extractor need not be moored to a location to extract energy from waves.
    Type: Grant
    Filed: November 18, 2010
    Date of Patent: March 6, 2012
    Inventor: Kenneth Sykes Patten
  • Patent number: 8129855
    Abstract: Novel apparatus and techniques for harnessing wind and/or moving-liquid energy using one or more portable turbine systems are disclosed. One embodiment includes a portable stream turbine system having a hub with many paddles, held by an axle in a housing. The system further includes a disk fixed to the hub and extended out of the housing to be also fixed to a gear structure, which is connected to a generator. The output of the generator can be connected to electronics to perform different functions. Another embodiment includes a number of portable turbine systems removably attached together to form an array. In one example, the number of portable turbine systems in an array can be adjustable, depending on needs. The different embodiments regarding a stream turbine system can further include a floatation mechanism to keep the different embodiments afloat or partially afloat in a fluid.
    Type: Grant
    Filed: December 2, 2008
    Date of Patent: March 6, 2012
    Inventors: Lucas Tong, Cameron Smith
  • Patent number: 8129856
    Abstract: One aspect of the invention relates to a method of supplying power to a sensor arrangement including a first sensor and at least one second sensor which in each case have a first and a second supply terminal, and which can be operated in a first and a second operating mode. The first and at least one second sensor can be connected via their supply terminals to a voltage supply arrangement in the first operating mode. The first and at least one second sensor can be connected in series with one another via their supply terminals in the second operating mode and the series circuit with the first and at least one second sensor is connected in series with a current source.
    Type: Grant
    Filed: August 2, 2006
    Date of Patent: March 6, 2012
    Assignee: Infineon Technologies AG
    Inventor: Axel Reithofer
  • Patent number: 8129857
    Abstract: A first signal processing circuit performs predetermined signal processing on a first signal to provide a change to a characteristic value thereof, and then outputs a second signal. A second signal processing circuit performs predetermined signal processing on the second signal to provide a change to a characteristic value thereof, and then outputs a third signal. A first and a second switching power supplies respectively supply power supply voltages to the first and second signal processing circuits. An amount of change provided to the characteristic value of the first signal by the first signal processing circuit, and an amount of change provided to the characteristic value of the second signal by the second signal processing circuit, are dependent on the respective power supply voltages.
    Type: Grant
    Filed: March 24, 2009
    Date of Patent: March 6, 2012
    Assignee: Advantest Corporation
    Inventors: Shoji Kojima, Toshiyuki Okayasu
  • Patent number: 8129858
    Abstract: A remote controlled extension cord. The extension cord has a wire attached to a plug with an integrated base. The base serves to cradle a remote control, which is used to turn power on/off to the extensions on the cord. The remote control can snap inside the base and can be easily pushed out. The base thereby serves as a convenient storage for the remote control in order to discourage the remote from getting misplaced.
    Type: Grant
    Filed: February 3, 2010
    Date of Patent: March 6, 2012
    Inventor: Mike McClurkan
  • Patent number: 8129859
    Abstract: In an extension cord with wireless timing function, there are included a receptacle housing having more than one flush plug receptacles and internally including a current converter, a power switch and a plurality of electronic relays corresponding to the receptacles; a programmable logic controller in the receptacle housing for controlling the ON/OFF state of the receptacles; a wireless transmission module in the receptacle housing for receiving a wireless signal from a remote device; a power cord connected at an end to the power switch; and an operation and control module located on the receptacle housing and connected to the controller. Thus, timed power supply by each of the receptacles can be set and recorded at the remote device. When the power switch is turned to off, the controller automatically resets the receptacles to ON; and when the power switch is turned to on again, the receptacles will remain to “ON”.
    Type: Grant
    Filed: August 24, 2009
    Date of Patent: March 6, 2012
    Assignee: Hurco Automation, Ltd.
    Inventor: Jacob Pien
  • Patent number: 8129860
    Abstract: Methods and systems for providing electrical power over a network configured to facilitate digital communications are described herein. In different aspects, the methods and systems may include a service provider network module configured to facilitate digital communications and having an autonomous power supply, and a network connection device operably connected to the service provider network module. The network connection device may include at least one network connection port configured to receive electrical power; and a power switching module coupled to the at least one network connection port and configured to switch from a primary power source to enable the network connection device to receive electrical power from the service provider network module via the at least one network connection port when electrical power from the primary power source is interrupted.
    Type: Grant
    Filed: December 18, 2009
    Date of Patent: March 6, 2012
    Assignee: AT&T Intellectual Property I, L.P.
    Inventor: Mounire El Houmaidi
  • Patent number: 8129861
    Abstract: A voltage supply has a plurality of voltage sources to supply output connections. To achieve closed-loop control of the output voltage at the output connections, a closed-loop control circuit is provided that has an actuating element for each voltage source, and each respective actuating element has a current path via which a connection of the respective voltage source can be connected to an output connection. Each actuating element has an actuating signal input for setting the electrical conductivity of its current path. The closed-loop control circuit has a closed-loop controller to which the output voltage and a desired voltage signal are supplied. When a deviation occurs between the output voltage and the desired voltage signal, the closed-loop controller interacts with at least one actuating signal input in order to reduce the deviation.
    Type: Grant
    Filed: October 21, 2009
    Date of Patent: March 6, 2012
    Assignee: Micronas GmbH
    Inventors: Matthias Kuhl, Claas Müller, Yiannos Manoli, Gilbert Erdler
  • Patent number: 8129862
    Abstract: A scalable highest available voltage selector circuit determines the highest of n input voltages and connects the highest voltage to an output. The circuit has at least n circuit branches, each of which comprises n?1 “comparator” FETs connected between an input voltage and an output node, and a diode-connected FET connected between the output node and a current source. The junction of the diode-connected transistor and current source provides a control signal used by the other branches. Each of a branch's comparator FETs have their gates connected to a respective one of the other branches' control signals, such that they are driven on regeneratively when the applied input voltage is the highest of the n input voltages. Each branch also includes n?1 “shorting” FETs connected across the diode-connected transistor, arranged to be driven off when the applied input voltage is the highest, but which are otherwise driven on.
    Type: Grant
    Filed: October 23, 2009
    Date of Patent: March 6, 2012
    Assignee: Analog Devices, Inc.
    Inventor: Jonathan Mark Audy
  • Patent number: 8129863
    Abstract: In an apparatus for connecting two generators to run in parallel, having plugs connectable to each generator output socket, an output socket connected to an electrical load, conductive paths that connect the plugs to the output socket while merging to a common path at a junction before the output socket, and a switching circuit that opens/closes the conductive paths, there are equipped with a connecting path that interconnects the conductive paths before the junction, a dummy load installed at the connecting path and current sensors installed at each conductive path. Disconnection of the plug from the socket is detected from the detected currents and the conductive paths are opened not to connect the generators to the electrical load, thereby preventing an output of the other of the generators from appearing at the terminals of the disconnected plug, and further preventing misjudging current change of the instantaneous no load condition as plug disconnection.
    Type: Grant
    Filed: June 22, 2009
    Date of Patent: March 6, 2012
    Assignee: Honda Motor Co., Ltd.
    Inventors: Junichi Eguchi, Yoshinori Masubuchi
  • Patent number: 8129864
    Abstract: An inductive power supply that maintains resonance and adjusts duty cycle based on feedback from a secondary circuit. A controller, driver circuit and switching circuit cooperate to generate an AC signal at a selected operating frequency and duty cycle. The AC signal is applied to the tank circuit to create an inductive field for powering the secondary. The secondary communicates feedback about the received power back to the primary controller. The power transfer efficiency may be optimized by maintaining the operating frequency substantially at resonance, and the amount of power transferred may be controlled by adjusting the duty cycle.
    Type: Grant
    Filed: January 7, 2009
    Date of Patent: March 6, 2012
    Assignee: Access Business Group International LLC
    Inventors: David W. Baarman, Scott A. Mollema, Joshua K. Schwannecke, Thomas Jay Leppien, Kenneth Michael Burns
  • Patent number: 8129865
    Abstract: An inductive rotary joint for non-contact transmission of electrical energy between a stationary part and a rotating part of the rotary joint comprises a power generator for generating an alternating voltage or an alternating current, which feeds a load by means of a rotatable power transmitter. An electrical parameter on the primary side of the power transmitter is determined with a measurement means, and from this, the condition of another electrical parameter at the load is approximated by means of a functional unit. Regulation of the power generator is effected with this approximated value.
    Type: Grant
    Filed: May 5, 2009
    Date of Patent: March 6, 2012
    Assignee: Schleifring und Apparatebau GmbH
    Inventors: Nils Krumme, Georg Lohr, Herbert Weithmann, Michael Bley
  • Patent number: 8129866
    Abstract: A circuit for a fill-level measuring device is for the fast switching-on of a high-frequency element on a ground port is disclosed. The circuit comprises a switching unit with a circuit mass; a high-frequency element with a high-frequency mass; and a coupling element that couples the two masses together and at the same time insulates them from each other in a direct-current manner. In this way the switching unit can be arranged on the GND port of the HF-element, without influencing the HF characteristics of said HF element.
    Type: Grant
    Filed: March 6, 2008
    Date of Patent: March 6, 2012
    Assignee: Vega Grieshaber KG
    Inventor: Christoph Mueller
  • Patent number: 8129867
    Abstract: A system and method for overcoming the parasitic elements associated with off the shelf or general purpose solid-state devices configured to operate as RF AC/DC signal coupling networks. An AC/DC signal coupling network may comprise a general purpose solid-state relay device and two inductors having values carefully chosen to compensate for the imperfections and intrinsic parasitic elements associated with the solid-state relay. The inductors may also have values carefully chosen to compensate for the parasitic elements of the neighboring or coupled circuit, and for the capacitance that is associated with the printed circuit board bond pad that is directly dependent upon the area of the pad and distance to the neighboring conductors. The inductors may cause the input path to become inductive as the signal frequency increases, and also improve the input return loss over the RF input range.
    Type: Grant
    Filed: March 24, 2009
    Date of Patent: March 6, 2012
    Assignee: National Instruments Corporation
    Inventors: Zaher G. Harb, Mark Whittington
  • Patent number: 8129868
    Abstract: The present invention relates to a shock-proof electrical output device, which comprises a voltage converter, a current monitoring relay device, a latching relay device, and a changeover relay device.
    Type: Grant
    Filed: October 3, 2007
    Date of Patent: March 6, 2012
    Assignee: International Safety & Development, LLC
    Inventor: Paul Cruz
  • Patent number: 8129869
    Abstract: To provide an electret having high stability with time and thermal stability of retained electric charge and having excellent charge retention performance, and an electrostatic induction conversion device comprising such an electret. This has been done by providing an electret obtained from a composition comprising a compound (A) having a molecular weight of from 50 to 2000 and having at least two polar functional groups, and a polymer (B) having a number average molecular weight of more than 2000 and having reactive functional groups reactive with the above polar functional groups and an electrostatic induction conversion device comprising such an electret.
    Type: Grant
    Filed: March 16, 2011
    Date of Patent: March 6, 2012
    Assignee: Asahi Glass Company, Limited
    Inventor: Kimiaki Kashiwagi
  • Patent number: 8129870
    Abstract: An asymmetric folded spring flexure suspension system can enable an ultra-compact linear reciprocative device wherein a reciprocative mass suspended from a base by a single folded flexure assembly extends in a single generally radial direction perpendicular to the intended travel path. The folded flexure assembly can be configured as three side-by-side stacks of flexure strips of spring material, tied together at a “yoke-idler” end; at the opposite “working” end, a central stack of nominal width is tied to the mass, and, flanking the central stack, a pair of half-width stacks are tied to opposite sides of the base. In an embodiment for active vibration control, a cylindrical enclosure, of magnetically-permeable material and attached to the working end of the flexure assembly, contains a driver system including an internally-mounted pair of permanent magnets that provide a magnetic flux gap and also constitute the main portion of the mass.
    Type: Grant
    Filed: August 4, 2009
    Date of Patent: March 6, 2012
    Inventor: Kenneth E. Pusl
  • Patent number: 8129871
    Abstract: An electromagnetic vibrator is composed of vibration sheet, suspension edge, basin frame and magnetic return path system. The electromagnetic vibrator is prepared as connecting back surface of vibration sheet to voice coil being set in magnetic return path system, injecting the vibration sheet and suspension edge to be an integral unit, connecting suspension edge with basin frame by ultrasonic mode and connecting vice coil wire to terminal sheet on basin frame after the wire is connected by vibration sheet.
    Type: Grant
    Filed: September 29, 2007
    Date of Patent: March 6, 2012
    Inventor: Hsin Min Huang
  • Patent number: 8129872
    Abstract: An impeller and at least a portion of a cooperating peripheral volute may be integrated are integrally injection molded with, concentric outer rotor and inner stator assemblies, respectively, to achieve a low profile precision impeller mechanism based on an improved brushless D.C. motor with low length to diameter ratio and suitable for use in a variety of other applications. A rotating cap has an inner circumference which is molded about an outer ferromagnetic back ring that in turn supports a rotor magnet having a number of poles of alternating polarity and separated by a relatively small cylindrical air gap from a fixed stator assembly. The fixed stator assembly is integrally molded into a base housing having a bearing support that extends upwardly through the center of the stator assembly and that is rotatably coupled to a rotating shaft that extends downwardly from the center of the rotating cap.
    Type: Grant
    Filed: September 27, 2010
    Date of Patent: March 6, 2012
    Assignee: Resmed Motor Technologies Inc.
    Inventors: Leslie C. Hoffman, Barton J. Kenyon, David B. Sears
  • Patent number: 8129873
    Abstract: A coolant flow reduction monitoring system for a rotary electric machine having stator coils within a plurality of slots of a stator thereof is provided. The stator coils are cooled by a coolant flowing in a plurality of passages provided in the stator coils. The system includes an outlet temperature sensor for measuring a coolant outlet temperature of the coolant in an outlet of at least one of the plurality of passages, a slot temperature sensor for measuring a temperature in at least one slot at a location along a length of each slot and outside of the stator coils, and an inlet temperature sensor for measuring a coolant inlet temperature of the coolant. A coolant flow reduction monitor generates an alarm indicating a coolant flow reduction based on the at least one coolant outlet temperature, the at least one slot temperature and the coolant inlet temperature.
    Type: Grant
    Filed: April 5, 2010
    Date of Patent: March 6, 2012
    Assignee: General Electronic Company
    Inventors: Sudhanshu Rai, Nicola Piccirillo, Subrat Kumar Sahoo, Ravikumar Sandrana
  • Patent number: 8129874
    Abstract: A system for cooling an electrical machine is disclosed. The electrical machine includes a stator including a plurality of coils, an exterior housing, and an end cap. During operation of the electrical machine, a fluid is sprayed from the end cap onto the plurality of coils to carry away heat generated by the electrical machine.
    Type: Grant
    Filed: June 17, 2009
    Date of Patent: March 6, 2012
    Inventors: Carolyn Lambka, Eric Richard Anderson