Abstract: A booster circuit includes a pump circuit having a plurality of charge pump circuits for outputting a boosted voltage to a first output terminal. The booster circuit also includes a clock adjusting circuit that generates, from a first clock signal, a second clock signal for operating the charge pump circuits. A pump controlling circuit outputs the first clock signal for operating the pump circuit. A first comparator outputs a first output signal. A second comparator outputs a second output signal. A third comparator outputs a third output signal. A gradient of the boosted voltage is decreased when the first output signal is output. A frequency of the first clock signal is reduced when the second output signal is output. The third output signal is output when the boosted voltage is higher than a set value of the boosted voltage.

Abstract: An apparatus and method for the dynamic detection and compensation of performance variations within an integrated circuit (IC) is provided to detect performance variations within the IC at any stage of test or operation. An arbitrary reference signal is utilized in conjunction with an internal oscillation device to establish a speed reference that may be used to characterize the IC. Dynamic detection and compensation may also be configured within a plurality of geographic locations within the IC, so that performance variations may be detected and compensated. Test data that is indicative of the IC's performance may be dynamically generated continuously, or at programmable intervals, so that performance variations caused by virtually any source may be substantially detected and compensated at any point in time of the IC's life cycle.

Abstract: A CMOS charge pump with improved latch-up immunity is provided. The CMOS charge pump includes a blocking transistor that disconnects first and second boost nodes from a bulk node in response to a blocking control signal, such that a bulk voltage can be maintained at a predetermined level or higher. The CMOS charge pump in a power-up period first precharges the bulk voltage before the main pump performs a boosting operation and prevents a latch-up phenomenon.

Abstract: A switching circuit for switchably connecting an input node and an output node. The switching circuit comprises a switch operable to switchably connect the input node to the output node in response to a switching signal. A sensor is provided for sensing the voltage between the input and output nodes and providing a sense signal in response thereto. A driver coupled to the sensor adjusts the switching signal in response to the sense signal.

Abstract: A method includes controllably generating a first bias voltage from a supply voltage to be within an upper tolerable limit of an operating voltage of an IO receiver, and controllably generating a second bias voltage from an external voltage supplied through an IO pad to be within the upper tolerable limit of the operating voltage of the IO receiver. The method also includes deriving an output voltage from the first bias voltage during a normal condition and a tolerant condition, and deriving the output voltage from the second bias voltage during a failsafe condition. The tolerant condition is a mode of operation where the external voltage supplied through the IO pad varies from zero to a value higher than the supply voltage, and the failsafe condition is a mode of operation where the supply voltage is zero.

Abstract: Examples of the present invention include a metamaterial comprising a plurality of resonators disposed on a substrate, the substrate comprising a dielectric support layer and a relatively thin semiconductor layer, having a Schottky junction between at least one conducting resonator and the semiconductor layer. The properties of the resonator may be adjusted by modifying the physical extent of a depletion region associated with the Schottky junction.

Abstract: The invention relates to systems and methods for high-sensitivity detection of input bias current. The invention more particularly relates to platforms and techniques for the calibration and measurement of input bias current in op amps or other devices. In embodiments, the platform can incorporate a servo loop connected to a high-sensitivity test amplifier, such as an instrumentation amplifier. The test amplifier can complete a switchable circuit with the servo loop and detect a calibration input bias current for the test platform, without a production device in place. The device under test can be switched into the servo loop, and the total bias current measured with both the device under test and test amplifier in-circuit. The difference between the measured current with the device inserted and the previously measured calibration current represents the bias current for the subject device, without attaching external meters or requiring reference parts of the production type.

Abstract: Disclosed are embodiments of an integrated circuit device, method and design structure for selectively amplifying one of multiple received input signals. The embodiments incorporate at least two first stage transistors and a single second stage transistor. The first stage transistors are adapted to receive input signals from the same or different input signal sources and are each electrically coupled to the second stage transistor. A control circuit design is adapted to individually turn on a selected first stage transistor in conjunction with the second stage transistor, thereby activating a corresponding one of the cascode amplifiers and allowing the input signal received by the selected first stage transistor to be separately amplified.

Abstract: A rail-to-rail amplifier includes an NMOS type amplification unit configured to perform an amplification operation on differential input signals in a domain in which DC levels of the differential input signals are higher than a first threshold value, a PMOS type folded-cascode amplification unit configured to perform an amplification operation on the differential input signals in a domain in which the DC levels of the differential input signals are lower than a second threshold value which is higher than the first threshold value, the PMOS type folded-cascode amplification unit being cascade-coupled to the NMOS type amplification unit, and an adaptive biasing unit configured to interrupt a current path of the PMOS type folded-cascode amplification unit in a domain in which the DC levels of the differential input signals are higher than the second threshold value in response to the differential input signals.

Abstract: A selectable gain amplifier includes two or more selectable gain stages, each gain stage having a first input coupled to receive an input signal, a second input, and an output. The amplifier further includes and two or more feedback paths coupled between the outputs and the second inputs of the selectable gain stages.

Abstract: A circuit provides a first current corresponding to the differential input Inn and Inp, and a second current corresponding to the common mode input Vcm. The circuit then mirrors the differential current and the common mode current to a third current and a fourth current. Based on the difference between the mirrored differential current and the mirrored common mode current, the circuit pulls up or pulls down these currents to balance the corresponding difference between the differential input and the common mode input. In effect, the circuit adjusts the input common mode voltage to a desired level, without providing an opportunity for it to rise to an unwanted level.

Abstract: An input bias current cancellation circuit includes reference transistors placed in series and a current summation network. The current summation network can be configured to sum the base currents of the reference transistors to produce a summed current. A current mirror can be provided to attenuate the summed current to produce input bias cancellation currents. The input bias cancellation currents can be provided to the base inputs of an input bipolar differential pair, thereby reducing input current noise.

Abstract: A class AB operational amplifier includes: a first transistor, for generating a first current; a second transistor, where a second source voltage of the second transistor is equal to a first source voltage of the first transistor, for generating an output stage quiescent current; and an output stage quiescent current controller, coupled to a gate and a source of the first transistor, for controlling a first drain-to-source voltage of the first transistor to be equal to a second drain-to-source voltage of the second transistor. A ratio of the output stage quiescent current to the first current is equal to a ratio of a second W/L ratio of the second transistor to a first W/L ratio of the first transistor.

Abstract: An RF power amplifier includes a first amplifier module comprising a first push-pull amplifier including a first plurality of field effect transistors and a first output transformer. An output impedance of the first amplifier module is 25 ohms. A second amplifier module includes a second push-pull amplifier including a second plurality of field effect transistors and a second output transformer. An output impedance of the second amplifier module is 25 ohms. A combiner is connected to the first amplifier module and the second amplifier module. The combiner combines an output from the first amplifier module and an output from the second amplifier module into a combined signal. An output impedance of the combiner is 50 ohms.

Abstract: Methods to implement low cost, high efficiency, low loss power combiner with novel matching circuits are disclosed. A narrow band power combiner enables a high power and high efficiency radio frequency power amplifier to be realized using multiple low voltage CMOS transistors or micro power amplifiers. The power combiner may be printed on a package substrate and realized either using single layer substrate through edge coupling or multiple layers substrate through broadside coupling. The micro power amplifiers may be fabricated using low voltage CMOS technology and electrical connections between the outputs from the micro power amplifiers and the power combiner may be provided through stud bumps in a flip chip technology. With the tunable matching circuits, the present invention allows the narrow band power combiner to be tuned to different frequencies.

Abstract: Provided is a power amplifier device. The power amplifier device includes: a cutoff unit cutting off a direct current (DC) component of a signal delivered from a signal input terminal; a circuit protecting unit connected to the cutoff unit and stabilizing a signal delivered from the cutoff unit; and an amplification unit connected to the circuit protecting unit and amplifying a signal delivered from the circuit protecting unit, wherein the amplification unit comprises a plurality of transistors connected in parallel to the circuit protecting unit and the circuit protecting unit comprises resistors connected to between bases of the plurality of transistors.

Abstract: Methods and devices for leakage current reduction are described. A regulator transistor is connected to a switch to bias the transistor with a first voltage during an ON state and a second voltage during the OFF state of the transistor. The switchable bias allows leakage current decrease and “on” resistance increase of the transistor.

Abstract: A multi-stage RF/Microwave power amplifier circuit is provided that is capable of operating efficiently at multiple output power levels. The amplifier comprises first and second amplifying stages, an output impedance matching network connected to the output of first amplifying stage and an interstage impedance matching network connected between the outputs of said first and second amplifying stages. In a high power mode, the first amplifying stage is enabled and the second amplifying stage is disabled and the output and interstage impedance matching networks present a first value of the output impedance that improves the efficiency of the first amplifying stage. In a low power mode, the first amplifying stage is disabled and the second amplifying stage is enabled, and output and interstage impedance matching networks present a second value of the output impedance that improves the efficiency of the second amplifying stage.

Abstract: Configurable phase-locked loop circuitry is provided. The phase-locked loop circuitry may include a buffer having a buffer output and a multiplexer having inputs and an output. The phase-locked loop circuitry may include multiple voltage-controlled oscillators. The phase-locked loop circuitry may be configured to switch a desired one of the voltage-controlled oscillators into use. Each voltage-controlled oscillator may be controlled by control signals applied to a control input for that voltage-controlled oscillator. The control input of each voltage-controlled oscillator may be connected to the buffer output. The output of each voltage-controlled oscillator may be connected to a respective one of the multiplexer inputs. Power-down transistors may be used to disable unused voltage-controlled oscillators to conserve power. The power-down transistors and the multiplexer may be controlled by signals from programmable elements.

Abstract: A process that provides the ability to incorporate a self exciting loop (SEL) algorithm into a digital LLRF system. The present digital SEL provides for conversion from the Cartesian domain to the Polar domain, wherein most signal processing is accomplished, and back to Cartesian. By handling most signal processing in the Polar (phase & amplitude) domain, a perfect amplitude limiter can be realized and simpler logic operations can be used. When operational, cavity recovery from faults will be tuner-less. At high gradients, ˜20 MV/m, like those needed for the upgraded cryomodules, the Lorentz detuning will be many bandwidths, making cavity turn-on problematic with out some tuner based compensation or other algorithmic solution. The present SEL solves this problem and allows cavity recovery from cryogenic trips, wherein cavities have been known to detune 1000's of Hz. Other applications such has He processing can also be implemented in situ without additional electronics.

Abstract: A wireless communication device incorporating a set of comparators and logic interrupt into the local oscillator generation circuit block is described. In one design, the local oscillator circuit block includes a RF VCO with coarse and fine frequency tuning. The RF VCO fine frequency tuning signal is monitored continuously to determine if the control voltage is within specified limits. If the RF VCO fine frequency tuning voltage is too low or too high for the RF VCO to meet system requirements or lock on the current desired frequency, an interrupt signal is asserted. In response to the interrupt signal, a wireless communications processor or a hardware state machine initiates coarse frequency calibration of the RF VCO at the desired frequency. After coarse frequency calibration has completed, the RF VCO fine frequency tuning voltage is within specified limits and is continuously monitored.

Abstract: In many types of wireless applications (like wireless modems), it is important that the phase locked loops (PLLs) be able to synthesize clock frequencies in a wide tuning range. Because of the complexity of many conventional PLLs (which were deigned to cover wide tuning ranges), there was often a significant delay to achieve phase and frequency lock. Here, an open loop calibration system is provided to coarse tune a PLL very rapidly. Generally, this calibration system employs binary searches to coarsely adjust a voltage controlled oscillator (VCO) from a VCO bank to within a predetermined range around a target frequency.

Abstract: Equal numbers of variable capacitance elements, capacitance values of which are separately controlled according to a logic value of a corresponding bit of a delay control signal that is in a one-to-one relation with an oscillation frequency, are connected in parallel among differential outputs of all delay circuits excluding a differential non-inverting delay circuit at the end, which extracts a frequency signal to the outside. Bits of the delay control signal are connected in a one-to-one relation to the equal numbers of variable capacitance elements arranged on output sides of all the delay circuits, in a relation in which delay control signals continuous in terms of frequency are not connected to the equal number of variable capacitance elements arranged on an output side of one of the delay circuits.

Abstract: Generation of Terahertz range (300 GHz to 3 THz) frequencies is increasingly important for communication, imaging and spectroscopic systems, including concealed object detection. Apparatus and methods describe generating multiple phase signals which are phase-locked at a fundamental frequency, which are then interleaved into an output which is a multiple of the fundamental frequency. By way of example phase generators comprise cross-coupling transistors (e.g., NMOS) and twist coupling transistors (NMOS) for generating a desired number of phase-locked output phases. A rectifying interleaver comprising a transconductance stage and Class B amplifiers provides superimposition of the phases into an output signal. The invention allows frequency output to exceed the maximum frequency of oscillation of a given device technology, such as CMOS in which a 324 GHz VCO in 90 nm digital CMOS with 4 GHz tuning was realized.

Abstract: Dual table temperature compensation for a voltage controlled crystal oscillator is achieved by sensing the temperature of the voltage controlled crystal oscillator (VCXO), retrieving from a first table the frequency error with variations in the temperature sensed, retrieving from a second table the oscillator control voltage corresponding to the frequency error from the first table and applying the oscillator control voltage to the VCXO.

Abstract: Aspects of a method and system for varactor linearization are provided. In this regard, a relationship between control voltage and capacitance of a variable capacitor may be controlled utilizing a plurality of bias voltages communicatively coupled to a corresponding plurality of bias terminals of said variable capacitor. The variable capacitor may comprise a plurality of two-terminal unit varactors and a first terminal of each unit varactor may be coupled to an RF terminal of the variable capacitor, a second terminal of one of the unit varactors may be coupled to the control voltage, and a second terminal of each of the remaining unit varactors may be coupled to one of the bias voltages. The bias voltages may be generated via a resistor ladder and/or via the resistive nature of a portion of semiconductor substrate. The bias voltages may linearize the relationship between the control voltage and the capacitance.

Abstract: The present invention is intended to efficiently implement noise countermeasures for a semiconductor circuit board and for a semiconductor circuit. The present invention is constituted by a control substrate, and a semiconductor circuit connected to the control substrate. The semiconductor circuit includes a substrate, an integrated circuit group, and a noise countermeasure, and is separated from the control substrate. The integrated circuit group includes an integrated circuit as a noise source. The substrate has a stacked multilayer structure, and shifts the frequency of a noise generated by the integrated circuit group to the high frequency side. The noise countermeasure is connected between the integrated circuit group and the control substrate. The noise countermeasure is a filter for attenuating the high frequency of a noise.

Abstract: A tuning method and circuit for an LC tank resonant circuit, including an inductor and a variable capacitor, are described. In a tuning mode, an RF input signal is applied to an input port of the circuit, and the RF output signal is monitored as a variable capacitor control input is varied. A peak output is detected, and the corresponding variable capacitor control input is stored, and applied to the variable capacitor in an operating mode. In one embodiment, the variable capacitor control input is adjusted for delay in the peak detection process. In one embodiment, the variable capacitor comprises a coarse capacitor and a fine capacitor; the tuning procedure is repeated for each capacitor; and both coarse and fine variable capacitor control inputs are stored and applied to the respective capacitors in operating mode.

Abstract: The present invention relates to a frequency-adjustable radio frequency (RF) isolator that may operate as a bandpass filter when processing RF signals in a forward direction and may operate as a notch filter when processing RF signals in a reverse direction. The notch filter has a notch frequency, which is adjustable to provide adequate isolation from reflected signals at a specific operating frequency. The frequency-adjustable RF isolator may include an electro-magnetic gyrator coupled to a variable impedance circuit, which may present a variable impedance to the electro-magnetic gyrator. The notch frequency may be dependent on the variable impedance. The notch filter may be a single-notch filter or may be a multiple-notch filter.

Abstract: A high-frequency device having a high-frequency circuit comprising a high-frequency amplifier, and an output-matching circuit receiving high-frequency power output from the high-frequency amplifier, in and on a multilayer substrate obtained by laminating pluralities of dielectric layers, the output-matching circuit comprising a first transmission line transmitting the high-frequency power from the high-frequency amplifier side to the output terminal side, and at least part of the first transmission line being formed by series-connecting pluralities of conductor patterns formed on pluralities of dielectric layers in a laminate direction.

Abstract: Techniques are disclosed that allow for programmable attenuation using thermometer code steps. By thermometer coding the attenuator structure, monotonicity is guaranteed or otherwise greatly improved, which eliminates instability problems with automatic gain control loops and without the need for compensation or trimming. In addition, the thermometer coding technique also greatly reduces phase discontinuity between adjacent gain states.

Abstract: The present invention relates to a lumped cross-coupled Wilkinson circuit having a pair of magnetically cross-coupled inductive elements coupled to an isolation network. By magnetically cross-coupling the inductive elements, which have a mutual inductance, the inductance of each inductive element will be significantly less than the inductance of each inductive element in an equivalent lumped traditional Wilkinson combiner. Since the inductance of each inductive element is less, the size of each inductive element may be significantly smaller and the resistive loss of the each inductive element may be significantly smaller. In one embodiment of the present invention, the lumped cross-coupled Wilkinson circuit operates as a lumped cross-coupled Wilkinson combiner. In an alternate embodiment of the present invention, the lumped cross-coupled Wilkinson circuit operates as a lumped cross-coupled Wilkinson splitter.

Abstract: An acoustic resonator includes a first electrode, a second electrode, and a barium strontium titanate (BST) dielectric layer disposed between the first electrode and the second electrode, where the acoustic resonator is switched on as a resonator with a resonant frequency if a DC (direct current) bias voltage is applied across the BST dielectric layer. The acoustic resonator is also switched off if no DC bias voltage is applied across the BST dielectric layer. Furthermore, the resonant frequency of the acoustic resonator can be tuned based on a level of the DC bias voltage, with the resonant frequency increasing as the level of the DC bias voltage applied to the BST acoustic resonator increases.

Abstract: An on-chip slow-wave structure that uses multiple parallel signal paths with grounded capacitance structures, method of manufacturing and design structure thereof is provided. The slow wave structure includes a plurality of conductor signal paths arranged in a substantial parallel arrangement. The structure further includes a first grounded capacitance line or lines positioned below the plurality of conductor signal paths and arranged substantially orthogonal to the plurality of conductor signal paths. A second grounded capacitance line or lines is positioned above the plurality of conductor signal paths and arranged substantially orthogonal to the plurality of conductor signal paths. A grounded plane grounds the first and second grounded capacitance line or lines.

Abstract: In a circuit arrangement (1) for detuning a resonant circuit formed of an inductively acting electric circuit (14) and a capacitively acting discharging device (15), a detuning device (16) is arranged at least partially in series to the discharging device (15). The resonant circuit can be detuned in wide ranges by means of such a detuning device (16).

Abstract: A filter being small and having a narrowband filter characteristic is achieved using interdigital-coupled resonators. A first resonator and a second resonator are configured using interdigital-coupled quarter-wavelength resonators respectively. In addition, the first resonator and the second resonator are disposed so as to extend along directions intersecting with each other at a predetermined angle ?. Thus, coupling between the resonators is reduced compared with, for example, a case that the first resonator and the second resonator are, as a whole, disposed in parallel to each other. The angle ?, with which the first resonator and the second resonator are disposed respectively, is adjusted, thereby coupling between the resonators may be made into a desired state. Thus, a desired narrowband filter characteristic is obtained.

Abstract: A microstripline filter that includes principal-surface lines, a ground electrode, and input/output electrodes. A first principal-surface line is capacitively coupled to a second principal-surface line. The second principal-surface line is inductively coupled to a third principal-surface line. The third principal-surface line is capacitively coupled to a fourth principal-surface line. The first through fourth principal-surface lines include open-end-side electrodes, short-circuit-end-side electrodes, and end-opened electrodes. A first pair of the end-opened electrodes are adjacent to each other, whereas a first pair of the short-circuit-end-side electrodes are separate from each other. A second pair of end-opened electrodes are adjacent to each other, whereas a second pair of short-circuit-end-side electrodes are separate from each other.

Abstract: A waveguide bandpass filter for use in microwave and millimeter-wave satellite communications equipment is presented. The filter is based on a substrate integrated waveguide (SIW) having several cascaded oversized SIW cavities. The filter is implemented in a printed circuit board (PCB) or a ceramic substrate using arrays of standard metalized via holes to define the perimeters of the SIW cavities. Transmission lines of a microstrip line, a stripline or coplanar waveguide are used as input and output feeds. The transmission lines have coupling slots for improved stopband performance. The filter can be easily integrated with planar circuits for microwave and millimeter wave applications.

Abstract: The invention is directed to a switch assembly which can be used in situation in which the switch accommodates the flow of high voltage current. An actuator assembly with moveable contacts is moved by a motor driven armature. The moveable contacts are in electrical engagement with the stationary contacts when the armature is in the first position, and the moveable contacts are spaced from the stationary contacts when the armature is in the second position. By angling the stationary contacts and moveable contacts, the linear motion of the armature causes the moveable contacts to move across the surface of the stationary contacts as the armature approaches the first position. As all of the movements of the assembly are in a direction parallel to the axis of the armature, the assembly can be manufactured and operated reliably in a relatively small space. In addition, the linear movement on the angled contact provides for a positive electrical connection even in adverse environments.

Abstract: The present invention discloses an electromagnetic coil device including a coil body having a connection terminal portion projecting from a circumferential surface of the coil body, a buckle having a positioning flat plate portion and an inserting flat plate portion fixedly connected to the positioning flat plate portion. The inserting flat plate portion is pottedly connected to the connection terminal portion with potting material. The electromagnetic coil device can, on the one hand, reduce the manufacturing cost and improve the reliability of the connection between the coil body and the buckle, and on the other hand, prevent the coil body from being damaged by welding and thus improve the life thereof.

Abstract: Wire-holders are provided that confine a single wire over a limited arc section and that are interspersed with ferrite ingots that provide wire-ways for several wires are utilized in the winding of the coils of a transformer. A method for consistently producing windings having accurate wire placement on rotors, stators, and other electrical componentry is also provided.

Abstract: A semiconductor transformer provides high frequency operation by forming the primary windings of the transformer around a section of magnetic material that has a hard axis that lies substantially parallel to the direction of the magnetic field generated by the primary windings. The core can also be formed to have a number of sections where the magnetic flux follows the hard axis through each section of the core.

Abstract: [Problems] To provide a planar inductor that can be easily designed in any size without restricting coil characteristics, that supplies the necessary power corresponding to the area when a pair of inductors are placed facing each other to carry out non-contact power transmission, and that has greater design flexibility that allows for setting separation cut-off lines with relative freedom.

Abstract: The invention comprises an electrical system including at least an inductor configured to carry a magnetic field of less than about thirty Gauss/Oersted. The inductor comprises an inductor core having a plurality of coated particles, each of a majority of the coated particles comprising: at least three layers, a first set of substantially magnetic alternating layers composed of an alloy, and a second set of substantially non-magnetic alternating layers, where the coated particles are about evenly distributed in the inductor core. Optionally, a thermal transfer agent is used to cool the inductor, where the thermal transfer agent includes at least one of: a thermally conductive potting material and a substantially non-conductive liquid coolant in direct contact with the inductor. Optionally, a cooling coil passes through the potting material and/or the liquid coolant.

Abstract: A multiple fuse device for a vehicle includes a circuit board with a battery-side bus bar portion and an alternator-side bus bar portion connected together by a temporary joint portion at a position apart from a fusing portion that provides charging current protection. An insulator housing is placed over the circuit board but the temporary joint portion is left uncovered by the insulator housing. A temporary joint portion is then at least partially removed. This partial removal may leave behind two temporary joint portion remnants, one on the battery-side bus bar portion, and one on the alternator-side bus bar portion. The temporary joint portion thus enhances the strength of the circuit board while the fuse device is being manufactured, which prevents the fusing portion from being accidentally deformed or broken during the device's assembly.

Abstract: A varistor includes a ceramic base body having a surface. The varistor also includes an insulating layer on at least a portion of the surface of the ceramic base body. The insulating layer includes a base glass and filler. The filler includes 3Al2O32SiO2.

Abstract: A temperature probe includes a substrate, a cantilever body portion formed on the substrate, having an anchor portion held in contact to the substrate and a free end portion extending out of the surface of the substrate, and a sputter-deposited thermistor sensor portion located at the free end portion of the cantilever body portion.

Abstract: A push-button switch test device having a flexible tab fixedly attached to a pushing member. The flexible tab is made of a flexible material and includes a deformation sensitive resistor mounted on a surface. The push-button switch test device may be used to test a push-button by imposing a known force on the flexible tab while receiving a signal level across the deformation sensitive resistor. As the known force pushes on the flexible tab, the signal level indicates when the push-button has engaged. The force may then be reversed to permit sensing of the disengagement of the switch. Configurations of a plurality of push-button switch test devices may be arranged in a test frame that mirrors a configuration of push-button switches.

Abstract: The technology described relates to management of data packets and buffers comprising segments of data packets in a mobile communication system. Information associated with data packet segments is analyzed by a Base Station System (BSS) housing a data buffer. Based on this information analysis, the BSS can identify those segments in the buffer that constitute a complete data packet. Once identified, the segments can be discarded from the buffer. The information can include size information, whereby the analysis comprises pairwise comparing the size of a current segment with the size of a next consecutive segment. This size comparison enables identification of a first segment and a last segment of the complete data packet. The information could also, or alternatively, include a notification provided in the header of the segment. This notification identifies the associated segment as the first or last segment of the data packet or an intermediate segment.

Abstract: Systems and methods for touchscreen security gateways are described, wherein a mechanical lock simulation is presented and operated by the user of a touchscreen interface. Comparisons between entered and stored combinations may be processed and/or stored utilizing local or remote processing and/or storage resources. The mechanical lock aspect of the user interface may comprise simulated rotating elements that may be operated by user-induced sliding interactions upon the user interface. Several aspects of the mechanical lock simulation may be customized or programmed by the user, and the presentation of the user interface operation to the user may include audible and/or haptic feedback.