Abstract: An occupant detection system includes a controller, a sensing electrode, and a shield electrode, the electrodes disposed in a vehicle seat. The controller is electrically coupled to the sensing electrode and shield electrode by a sensing circuit. The controller is configured to send an input signal to the sensing electrode, the shield electrode, or both and measures current, impedance, or capacitance values to determine the presence of an object on the seat, to classify the object, or both.

Abstract: A test structure may characterize the properties of a transistor including a DC test structure for testing DC properties of the transistor, and an AC test structure for testing AC properties of the transistor. The DC and AC test structures may have common test pads.

Abstract: A device and method for limiting damage to a semiconductor device under test when the semiconductor device fails during a high current, or high power test is provided. The occurrence of a failure of the device under test is detected, and power applied to the semiconductor device is diverted through a parallel path element upon detection of failure of the semiconductor device.

Abstract: An apparatus includes a predetermined function circuit board having a primary area for accepting an electronic module to be tested, a secondary area coupled electrically with the primary area, and one cooperation electronic module installed on the secondary area and coupled electrically to the electronic module to define a predetermined function circuit. A thermal insulation device is installed in the primary area and is formed with a thermal insulation chamber for accepting the electronic module and thermally insulating the electronic module from the cooperation electronic module. A thermal control chip is disposed to control a testing temperature of the insulation chamber TIC, thereby providing a testing environment.

Abstract: In techniques for testing and calibrating an ablator, a tissue probe emulator is connectable to a tissue ablator being tested. The emulator includes a temperature sensor, a thermoelectric unit operative to vary a temperature sensed by the temperature sensor, an adjustable electrical load, electrical control circuitry connected to the thermoelectric unit and the electrical load and operative to independently adjust the electrical load and an output of the thermoelectric unit. The emulator conveys signals emitted by the temperature sensor to the tissue ablator and conveys an ablation energy output of the tissue ablator to the electrical load.

Abstract: The invention generally relates to a method and device for contacting contact areas (22) with probe tips (18) in a tester. The contact areas (22), which are arranged on a substrate (6), and the probe tips (18) are positioned relative to each other and then brought in contact with each other by an advancing motion. In order to detect a secure contact for each of the probe tips (18), the contacting between the probe tips (18) and the contact areas (22) is observed from at least two observation directions (34), which include an observation angle ? in a range of 0 to 180°.

Abstract: A testing apparatus includes a tester and a probe card system that includes a probe card connected to the tester, and an active interposer connected to the probe card and wirelessly coupled with a device to be tested. The active interposer includes pads positioned on its free surface facing the device. The pads are positioned with respect to pads of the device so that each pad of the active interposer faces a pad of the device and is separated therefrom by a dielectric. Each pair of facing pads forms an elementary wireless coupling element which allows a wireless transmission between the active interposer and the device. The active interposer also includes an amplifier circuit configured to amplify wireless signals from the device before forwarding them to the tester. The probe card system includes a transmission element able to transmit a power voltage from the tester to the device.

Abstract: A probing apparatus for semiconductor devices comprises a primary circuit board and a signal-adapting board positioned on the primary circuit board. The primary circuit board includes an inner area having a plurality of first contacts and an outer area having a plurality of first terminals and second terminals, and the first contacts are electrically connected to the first terminals via first conductive members in the primary circuit board. The signal-adapting board includes a plurality of second contacts electrically connected to the first contacts via second conductive members in the signal-adapting board.

Abstract: An integrated circuit on a substrate including at least one peripheral portion that surrounds an active area and is realized close to at least one scribe line providing separation with other integrated circuits realized on a same wafer. The integrated circuit includes at least one conductive structure that extends in its peripheral portion on different planes starting from the substrate and realizes an integrated antenna for the circuit.

Abstract: A voltage test device used in liquid crystal display (LCD) panels, including test solder pads and test lines, is proposed. The test solder pads are connected to an LCD panel through the test lines. Each of the test lines includes a switch test line and a signal-inputting test line. The voltage test device further includes a first connector. The switch test line includes a first portion of the switch test line and a second portion of the switch test line. The first portion of the switch test line is connected to the second portion of the switch test line through the first connector. The first connector is used for preventing the electric current in excess of a predetermined threshold from flowing inside the LCD panel. Meanwhile, a voltage testing system used in LCD panels is proposed.

Abstract: The present disclosure provides an apparatus testing a semiconductor device. The apparatus includes a plurality of testing pads. The apparatus includes a plurality of testing units. The apparatus includes a switching circuit coupled between the testing pads and the testing units. The switching circuit contains a plurality of switching devices. The apparatus includes a control circuit coupled to the switching circuit. The control circuit is operable to establish electrical coupling between a selected testing unit and one or more of the testing pads by selectively activating a subset of the switching devices.

Abstract: An apparatus for detecting pattern alignment error includes a first conductive pattern disposed over a first insulation member with a power source applied of the first conductive pattern; a second insulation member for covering the first conductive pattern; a second conductive pattern disposed on the second insulation member; a conductive via connected to the second conductive pattern and passing through the second insulation member; and an insulation pattern disposed in the first to conductive pattern for detecting an alignment error in response to a position of the conductive via.

Abstract: A fault in a DC power source, such as a battery string or a string of photovoltaic cells, is identified by detecting a change in an AC component of a residual current of the DC power source. In some embodiments, the DC power source is coupled to at least one DC bus and he methods further include generating an AC voltage on the at least one DC bus. For example, the DC power source may be coupled to a modulated DC bus of an uninterruptible power supply (UPS) system comprising an inverter having an input coupled to the DC bus. The inverter may be configured to generate an AC output voltage and the AC component has a frequency that is a harmonic of a fundamental frequency of the AC output voltage, such as a third harmonic of the fundamental frequency of the AC output voltage.

Abstract: A method for wireless power transmission includes obtaining, via a Q-value circuit, first and second voltages at respective first and second nodes of a resonance circuit. The first and second voltages are effective to determine if foreign matter is present in a space affecting wireless power transmission. The method includes controlling a switching section between the Q-value circuit and the resonance circuit such that at least a part of the electric power transmission process occurs at a different time than when the first and second voltages are obtained.

Abstract: Providing for a field programmable gate array (FPGA) utilizing resistive random access memory (RRAM) technology is described herein. By way of example, the FPGA can comprise a switching block interconnect having parallel signal input lines crossed by perpendicular signal output lines. RRAM memory cells can be formed at respective intersections of the signal input lines and signal output lines. The RRAM memory cell can include a voltage divider comprising multiple programmable resistive elements arranged electrically in series across a VCC and VSS of the FPGA. A common node of the voltage divider drives a gate of a pass gate transistor configured to activate or deactivate the intersection. The disclosed RRAM memory can provide high transistor density, high logic utilization, fast programming speed, radiation immunity, fast power up and significant benefits for FPGA technology.

Abstract: A programmable logic device includes: a logic block unit including logic blocks which are programmably connectable and perform a logical operation on an input data stream; and a configuration control circuit configured to control a logical operation configuration of the logic blocks in response to configuration information, wherein the configuration control circuit controls the logical operation configuration of the logic blocks based on first configuration information for a logical operation of a first input data stream included in the input data stream, receives second configuration information for a logical operation of a second input data stream included in the input data stream, while the first input data stream is supplied to the logic block unit, and controls a logical operation configuration of the second data stream based on the second configuration information in response to termination of the logical operation of the first input data stream.

Abstract: Providing for a field programmable gate array (FPGA) utilizing resistive random access memory (RRAM) technology is described herein. By way of example, the FPGA can comprise a switching block interconnect having parallel signal input lines crossed by perpendicular signal output lines. RRAM memory cells can be formed at respective intersections of the signal input lines and signal output lines. The RRAM memory cell can include a voltage divider comprising multiple programmable resistive elements arranged electrically in series across a VCC and VSS of the FPGA. A common node of the voltage divider drives a gate of a pass gate transistor configured to activate or deactivate the intersection. The disclosed RRAM memory can provide high transistor density, high logic utilization, fast programming speed, radiation immunity, fast power up and significant benefits for FPGA technology.

Abstract: A voltage level shifter for translating a binary input signal representing a binary sequence to a binary output signal representing the same binary sequence. The voltage level shifter comprises an input port for receiving the binary input signal as an input voltage varying between a first input voltage level and a second input voltage level. An output port is connected to a node for outputting the binary output signal as an output voltage varying between a first output voltage level and a second output voltage level. A supply voltage node connectable to a voltage supply, can provide the second output voltage level. A first switch is arranged to couple the supply voltage node to the node and to decouple the supply voltage node from the node based on a voltage at the node. A feedback voltage loop is connected to the node for providing a feedback voltage based on the voltage at the node.

Abstract: A semiconductor integrated circuit device includes cells A-1, B-1, and C-1 that have the same logic. Cell B-1 has cell width W2 larger than a cell width of cell A-1, but gate length L1 of a MOS transistor is equal to that of cell A-1. Cell C-1 has cell width W2 equal to a cell width of cell B-1, but has a MOS transistor having large gate length L2. A circuit delay of cell C-1 becomes large as compared with that of cells A-1 and B-1, but leak current becomes small. Therefore, by replacing cell A-1 adjacent to a space area with cell B-1, and by replacing cell B-1 in a path having room in timing with cell C-1, for example, leak current can be suppressed without increasing a chip area.

Abstract: Methods and apparatus for decoding of binary addresses and scanning rows and columns of an addressable array. In one example, an address decode circuit includes a first decoder circuit configured to partition an N-bit address into a plurality of address segments, each address segment including fewer than N bits, and N being a positive integer, the first decoder circuit configured to provide a plurality of first-stage decoded address outputs, and a second orthogonal decoder circuit coupled to the first decoder circuit and configured to receive the first-stage decoded address outputs and to produce 2N unique addresses from unique combinations of the plurality of first-stage decoded address outputs.

Abstract: A circuit comprises an inverter, a first transistor, a second transistor, and at least one switching circuit. The inverter has a first node and a second node. The first transistor has a first terminal, a second terminal, and a third terminal. The second transistor has a fourth terminal, a fifth terminal, and a sixth terminal. The at least one switching circuit is configured to switch a connection of at least one of the first transistor and the second transistor to the inverter. The second terminal and the fifth terminal are coupled to the first node. The third terminal and the sixth terminal are coupled to the second node. The first transistor and the second transistor are configured to cause a plurality of time delays at the second node.

Abstract: A charge pump includes a first current source unit and a second current source unit. The first current source unit is connected between a first voltage terminal and the control node. The second current source unit is connected between the control node and a second voltage terminal. According to a phase comparing signal, the first current source unit provides a first switching current to the control node. The second current source unit includes a first sub-switching current generator, a second sub-switching current generator and a select circuit. According to a voltage level of the phase comparing signal, the first sub-switching current generator generates a first sub-switching current. According to the voltage level of the phase comparing signal, the second sub-switching current generator generates a second sub-switching current. By the select circuit, the first sub-switching current or the second sub-switching current is provided to the control node.

Abstract: In accordance with an embodiment, a controller includes a comparator, a delay element, and a timer. The delay element is connected to an input terminal of the comparator and the timer is connected to an output terminal of the comparator. The delay element may include a switch having a control electrode coupled for receiving a control signal. In accordance with another embodiment, a detection signal is generated in response to a comparison signal transitioning to a first level.

Abstract: A circuit design configured to process a differential input signal is provided. A first floating capacitor ladder is configured to receive the positive of the differential input signal and is connected to a first switched capacitor network through phase one controlled switches. A second floating capacitor ladder configured to receive the negative of the differential input signal and is connected to a second switched capacitor network through other phase one controlled switches. A reference resistor ladder is connected to the first switched capacitor network through phase two controlled switches to provide voltage references and connected to the second switched capacitor network through other phase two controlled switches to provide the voltage references.

Abstract: An apparatus comprises a supply voltage divider, a state machine, two comparators and a threshold selector. The supply voltage divider divides a VCC into N states SK, and acquires the border voltages VK and VK+1 corresponding to the SK through a resistor divider. The threshold selector acquires a corresponding voltage VK from the supply voltage divider according to the current state SK outputted by the state machine and then sends the acquired VK as VH to a first comparator, and acquires a corresponding voltage VK+1 and sends the acquired VK+1 as VL to a second comparator. The state machine determines whether or not the VH and the VL are matched with the current state SK. If matched, the OSC of the state machine will be turned off, otherwise, the next state Sk+1 or Sk?1 of the SK will be outputted.

Abstract: Peak power reduction in transmit chains of multi-band radiocommunication devices is performed. By using knowledge of the phase transformations which occur at the upconverter to determine how baseband signal samples will combine at the higher (upconverted) frequency, peak prediction and corresponding baseband signal modification can be performed in a way that reduces peak power of the combined signal.

Abstract: A control circuit for a sensing electrode array is described. The control circuit for the sensing electrode array includes a signal intensity analyzer, an intensity-to-phase frequency converter, and a phase frequency analyzing unit. The signal intensity analyzer obtains an intensity signal corresponding to a sensing signal of each sensing line of the sensing electrode array, wherein each intensity signal is a direct-current signal. The intensity-to-phase frequency converter generates a phase frequency signal based on the intensity signal. At least the phase or the frequency of the phase frequency signal is related to the level of the corresponding intensity signal. The phase frequency analyzing unit obtains a signal magnitude of the corresponding sensing line according to each phase frequency signal. The control circuit for the sensing electrode array enhances the operating speed and the signal-to-noise ratio of the touch control sensing system without increasing the manufacturing cost.

Abstract: A digital output driver is disclosed. In accordance with some embodiments of the present disclosure, a digital output driver may comprise at least one of an output-source PMOS configured to source current during at least a portion of a low-to-high transition of a digital output, wherein the output-source PMOS is configured to mirror a reference PMOS configured to be driven at its gate by a first amplifier and to be biased by a first reference current, and an output-sink NMOS configured to sink current during at least a portion of a high-to-low transition of the digital output, wherein the output-sink NMOS is configured to mirror a reference NMOS configured to be driven at its gate by a second amplifier and to be biased by a second reference current.

Abstract: One embodiment provides a phase-locked loop (PLL), in which a sequencer controls a loop filter such that, when a signal indicating turning-off of a power supply of the PLL is input thereto, or when a signal indicating turning-on of the power supply of the PLL is input thereto, a resistance value of a first resistance change device in the loop filter is a first resistance value, and that, after the PLL is stabilized, the resistance value of the first resistance change device is a second resistance value which is higher than the first resistance value.

Abstract: Disclosed is a triangular wave generator which includes a square wave signal generating unit configured to output a first signal transitioning to a high level from a low level via an output terminal in response to a first transition of a clock signal and to transition the first signal to a low level from a high level in response to a reset signal; a resistance unit configured to adjust a voltage level of a the square wave signal; and a capacitance unit configured to receive an output signal of the resistance unit to generate a second signal rising to a high level from a low level with a slope, to provide the reset signal to the square wave signal generating unit, and to output a triangular signal by falling the second signal to a low level from a high level with a slope.

Abstract: A semiconductor integrated circuit includes a command generating unit configured to generate a plurality of second commands in response to a first command, each second command for indicating an operation sections of a corresponding anti-fuse circuit, and a plurality of anti-fuse circuits, each comprising an anti-fuse and configured to receives a corresponding second command and perform a rupture operation of the anti-fuse in response to the received corresponding second command.

Abstract: System and circuitry controlling characteristics of periodic signals. In one embodiment adjustment circuitry modifies periodic signal characteristic. A phase detector generates analog input signals indicative of a phase difference between the periodic signal and a reference signal. Conversion circuitry translates the analog input signals into digital signals. Signal driving circuitry, comprising a current source, provides control signals to the signal driving circuitry based on the digital signals. First input circuitry provides a first adjustment signal to the adjustment circuitry. Second input circuitry provides a second adjustment signal to the adjustment circuitry in response to the control signal. The first adjustment signal is based on input of analog signals to a circuit element in the first input circuitry to control the first adjustment signal. The second input circuitry is responsive to the control signal to provide the second adjustment signal with the digital version of the input signals.

Abstract: System and method providing multiple circuit paths to control characteristics of periodic signals. In one embodiment first and second detector signals are indicative of a phase and frequency differences between the output signal and a reference signal. A first input signal based on the first detector signal adjusts the phase difference. A first control signal based on the second detector signal has frequency content in high and low frequency ranges. A second input signal based on the control signal reduces the frequency difference. A second control signal based on the second detector signal has relatively low frequency content in the high frequency range. A third input signal based on the second control signal reduces the frequency difference.

Abstract: A system incorporating and method of operating phase locked loop circuitry. In one embodiment, having programmable circuitry for adjustment of loop dynamics, a VCO has a first input terminal for selecting phase and frequency characteristics of an output signal and an output terminal on which the output signal is provided. A detector generates first VCO input signals indicative of phase and frequency differences between the VCO output signal and a reference signal. Circuitry digitizes the first VCO input signals and generates an integral path input signal therefrom. Slow integral path circuitry comprising, a first transistor device and a programmable low pass filter: receives the integral path input signal, and provides a low pass filtered version of the integral path input signal to control conduction through the first transistor device and provide a first adjustment signal for adjustment of the frequency of the VCO output signal.

Abstract: Systems, methods and circuitry useful for adjusting a periodic signal such as with a voltage controlled oscillator or a delay line. In one series of embodiments, circuits and methods are provided for controlling current flow through first and second parallel paths where an impedance device in one path emulates the impedance characteristics of a different device in the other path. A phase or frequency characteristic of the periodic signal may be adjusted by alternate switching of current through the two paths.

Abstract: Circuits and methods for controlling a VCO output signal. A filtered version of an integral path input signal controls current flow through a proportional path. An exemplary embodiment generates an integral path input signal from a digital to analog converter. First integral path circuitry includes a first transistor device and a low pass filter which provides a filtered version of the integral path input signal to a first transistor device to control conduction through the device, providing a first VCO input signal for frequency adjustment of the output signal. Proportional path switching circuitry between a supply terminal and VCO input terminal includes a second transistor device which receives the first VCO input signals to control conduction between the supply terminal and the first VCO input terminal to provide a second signal for adjustment of the phase of the VCO output signal relative to the reference signal.

Abstract: A method for generating a signal is provided. A control signal is generated in response to a comparison between a reference signal and a feedback signal. Then, charge is provided to first and second low pass filters (LPFs). The first and second LPFs have first and second bandwidths, respectively, and the second bandwidth is greater than the first bandwidth. First and second gains are then applied to the outputs from the first and second LPFs, respectively, so as to generate first and second voltages, respectively. The first gain is also greater than the second gain. The feedback signal is then generated from the sum of the first and second voltages.

Abstract: A digital fractional PLL introduces an accumulated phase offset before the digital VCO to achieve the fractional part of the division ratio. To provide this phase offset, the digital accumulator can integrate a fractional component ?n. By forcing ?n to zero, the PLL becomes an integer-N PLL. A de-skew timing configuration can be used to remove any time mismatch between integer and fractional counters of the PLL. A digital PLL can merge the function of frequency generation (DVCO) and that of fractional frequency counting into the same circuit block by reusing various phases of the frequency output to generate a fractional frequency count. A digital integer PLL can include a comparator, wherein the feedback loop of this PLL forces the phase difference between the reference clock and feedback signals to approach zero. By changing the duty cycle of feedback signal, the frequency tracking behavior of the loop can be varied.

Abstract: A delay line of individually selectable delay elements can operate as an oscillator in an open loop mode to track process variation or drive a clock signal that varies with temperatures and voltages in the system. The delay line oscillator can also operate in a closed loop mode to match a frequency given by a tuner ratio and a reference clock. The delay line can also be used for measuring clock jitter or duty cycle.

Abstract: An object of the present invention is to provide a level shift IC with a reduced number of input signals over the conventional case. A level shift IC includes an amplitude converting unit including four level shifters; and a different-phase signal generating unit at a stage previous to the amplitude converting unit, including delay circuits. The different-phase signal generating unit generates, by the delay circuits, first and second delayed input signals from first and second input signals of different phases. Therefore, four input signals of different phases are obtained, and the amplitude converting unit increases the amplitudes of the input signals by the amplitude converting unit and thereby generates first to fourth output signals with different phases and increased amplitudes.

Abstract: A non-overlap circuit includes a first delay circuit configured to receive a first input signal and output a first control signal to a driver circuit, sensing circuitry configured to sense a current generated in response to the first control signal coupled through bulk semiconductor of a semiconductor substrate and produce a feedback signal response, and a second delay circuit. The second delay circuit configured to receive the feedback signal from the sensing circuitry and a second input signal and output a second control signal to the driver circuit based on the sensed feedback signal and the second input signal.

Abstract: A power control circuit includes a voltage output terminal, a control chip, a converter, and a comparator. A voltage input pin of the control chip is connected to a first power source. A voltage pin of the converter is connected to a second power source. A pulse input pin of the converter is connected to a pulse output pin of the control chip. An output pin of the converter is connected to the voltage output terminal. An inverting input terminal of a comparator is connected to a voltage output pin of the control chip. A non-inverting input terminal of the comparator is connected to the second power source through a first resistor and grounded through a second resistor. An output terminal of the comparator is connected to a detecting pin of the control chip and connected to the non-inverting input terminal of the comparator through a third resistor.

Abstract: In one embodiment a signal conversion circuit includes; first hysteresis comparator configured to receive a differential signal having first and second input signal components, to compare in magnitude between voltages of the first and second input signal components, and to output the comparison result as a first output signal; a second hysteresis comparator configured to receive the first and second input signal components, to compare in magnitude between the voltages of the first and second input signal components, and to output the comparison result as a second output signal that is an inversion signal of the first output signal; and a conversion buffer configured to convert the first and second output signals into a single-end signal.

Abstract: According to one embodiment, a level shift circuit includes a plurality of level shift units which are connected to each other and in which the delay time of the rising edge of an output voltage is different from the delay time of the falling edge of the output voltage. The delay time of the rising edge of the output voltage from the previous level shift unit is compensated by the delay time of the falling edge of the output voltage from the next level shift unit, and the delay time of the falling edge of the output voltage from the previous level shift unit is compensated by the delay time of the rising edge of the output voltage from the next level shift unit.

Abstract: Embodiments of the present invention provide a voltage level shifter used to translate a binary input signal representing a binary sequence to a binary output signal representing the same binary sequence. The input signal is provided by an input voltage varying between a first input voltage level and a second input voltage level. The output signal is provided by an output voltage varying between a first output voltage level and a second output voltage level. The output signal has a delay relative to the input signal, and the voltage level shifter has a leakage current. The voltage level shifter has a first operating mode and a second operating mode. In the second operating mode, the delay is shorter while the leakage current is higher than in the first operating mode.

Abstract: A squaring circuit has current mode triplet metal oxide semiconductor (MOS) devices, including a first MOS device, a second MOS device and a third MOS device each having a source operably coupled to a first current source; and a fourth MOS device, a fifth MOS device and a sixth MOS device each having a source operably coupled to a second current source. The drain of first and fourth MOS device is operably coupled to a first supply, the drain of second and fifth MOS device is operably coupled to a first differential output port and the drain of third and sixth MOS device is operably coupled to a second differential output port. The gate of first, second and sixth MOS device is connected to a first differential input port, and the gate of third, fourth and fifth MOS device is connected to a second differential input port.

Abstract: A multiple-modulus divider and an associated control method are provided. The multiple-modulus divider includes a divisor loader, a multiple-modulus dividing circuit and a modulus controller. The divisor loader downloads a divisor when a download signal indicates a start of a division period. The multiple-modulus circuit includes a plurality of cascaded divisors, and provides an output frequency according to an input frequency and the divisor. The dividers respectively output a plurality of modulus output signals, and each is operable under either a close-loop state or an open-loop state. The modulus controller selects and controls one of the dividers according to the divisor, and ensures the selected divider is maintained at the open-loop state when the division period ends. The download signal corresponds to one of the modulus output signals.

Abstract: This invention relates to an inductor, more particularly, to an inductor with variable inductances.

Abstract: A semiconductor chip includes a power transistor circuit with a plurality of active transistor cells. A first load electrode and a control electrode are arranged on a first face of the semiconductor chip, wherein the first load electrode includes a first metal layer. A second load electrode is arranged on a second face of the semiconductor chip. A second metal layer is arranged over the first metal layer, wherein the second metal layer is electrically insulated from the power transistor circuit and the second metal layer is arranged over an area of the power transistor circuit that comprises at least one of the plurality of active transistor cells.

Abstract: A semiconductor chip includes at least one power semiconductor switch configured to activate and deactivate current conduction from a first supply terminal, which is connected to a first supply line that provides an unstabilized first supply voltage, to the at least one output terminal in accordance with a respective control signal. In operation, the unstabilized first supply voltage is monitored and an under-voltage is signaled when the unstabilized first supply voltage falls below a first threshold value. The first supply terminal is short circuited with a third terminal when the an under-voltage is signaled.