Abstract: An array substrate for a liquid crystal display device comprises: gate and data lines crossing each other on a substrate to define a pixel region; a common line spaced apart from and parallel with the gate line; a thin film transistor in the pixel region and connected to the gate and data lines; a passivation layer on the thin film transistor; and pixel and common electrodes alternately arranged to produce an in-plane electric field, wherein each of the pixel and common electrodes has a double-layered structure of which the lower layer is formed of reflective conductive material and the upper layer is formed of transparent conductive material.

Abstract: A conventional setting voltage was a value with an estimated margin of a characteristic change of a light emitting element. Therefore, a voltage between the source and drain of a driver transistor Vds had to be set high (Vds?Vgs?VTh+a). This caused high heat generation and power consumption because a voltage applied to the light emitting element. The invention is characterized by feedbacking a change in a current value in accordance with the deterioration of a light emitting element and a power source voltage controller which modifies a setting voltage. Namely, according to the invention, the setting voltage is to be set in the vicinity of the boundary (critical part) between a saturation region and a linear region, and a voltage margin for the deterioration is not required particularly for an initial setting voltage.

Abstract: A thin film transistor substrate includes a substrate, a gate electrode on the substrate, an active layer on or below the gate electrode (the active layer at least partially overlapping the gate electrode) including a first active region and a second active region, the first active region and the second active region facing each other and extending beyond the gate electrode, a source electrode electrically connected to the first active region and a drain electrode electrically connected to the second active region, wherein the active layer includes a recess region which is at least partially recessed from a surface of the active layer facing the gate electrode, and the recess region includes a portion extending between the first active region and the second active region.

Abstract: The present invention provides a highly controllable device for exposure from the back side and an exposure method, and also provides a method of manufacturing a semiconductor device using the same. The present invention involves exposure with the use of the back side exposure device of which a reflecting means is disposed on the front side of a substrate, apart from a photosensitive thin film surface by a distance X (X=0.1 ?m to 1000 ?m), and formation of a photosensitive thin film pattern in a self alignment manner, with good controllability, at a position a distance Y away from the end of a pattern. The invention fabricates a TFT using that method.

Abstract: High-voltage solid-state transducer (SST) devices and associated systems and methods are disclosed herein. An SST device in accordance with a particular embodiment of the present technology includes a carrier substrate, a first terminal, a second terminal and a plurality of SST dies connected in series between the first and second terminals. The individual SST dies can include a transducer structure having a p-n junction, a first contact and a second contact. The transducer structure forms a boundary between a first region and a second region with the carrier substrate being in the first region. The first and second terminals can be configured to receive an output voltage and each SST die can a forward junction voltage less than the output voltage.

Abstract: A high linearity bandgap engineered transistor device is provided. In one example configuration, the device generally includes a substrate and an oxide layer formed on the substrate. The device further includes a wide-bandgap body material formed between a portion of the oxide layer and a gate dielectric layer. The wide-bandgap body material has an energy bandgap of 1.35 eV or higher and is lattice matched to the substrate. The device further includes a source-drain material formed on the oxide layer adjacent to the wide-bandgap body material so as to define a hetero-structure interface where the source-drain material contacts the wide-bandgap body material. The wide-bandgap body material is also lattice matched to the source-drain material. The device further includes a gate material formed over the gate dielectric layer. Other features and variations will be apparent in light of this disclosure.

Abstract: A hybrid transistor device is provided. In one example case, the device includes a substrate, an oxide layer formed on the substrate, and a wide-bandgap body material formed between a portion of the oxide layer and a gate dielectric layer. The wide-bandgap body material has an energy bandgap higher than that of silicon. The device includes source-drain/emitter material formed on the oxide layer adjacent to the wide-bandgap body material so as to define a hetero-structure interface where the source-drain/emitter material contacts the wide-bandgap body material. The device includes a gate material formed over the gate dielectric layer, a base material formed over a portion of the source-drain/emitter material, and a collector material formed over a portion of the base material. The source-drain/emitter material is shared so as to electrically combine a drain of a first transistor type portion of the device and an emitter of a second transistor type portion.

Abstract: A high electron mobility transistor includes a source, gate and drain, a first III-V semiconductor region having a two-dimensional electron gas (2DEG) which provides a first conductive channel controllable by the gate between the source and drain, and a second III-V semiconductor region below the first III-V semiconductor region and having a second conductive channel connected to the source or drain and not controllable by the gate. The first and second III-V semiconductor regions are spaced apart from one another by a region of the high electron mobility transistor having a different band gap than the first and second III-V semiconductor regions.

Abstract: A p-type GaN-based semiconductor device is provided. Porivded is a GaN-based semiconductor device including: a first channel layer which is formed from a GaN-based semiconductor, and in which a carrier gas of a first conductivity type occurs; a barrier layer formed on the first channel layer from a GaN-based semiconductor having a higher bandgap than the first channel layer; and a second channel layer which is formed on the barrier layer from a GaN-based semiconductor having a lower bandgap than the barrier layer, and in which a carrier gas of a second conductivity type occurs, wherein the carrier concentration of the carrier gas of the second conductivity type is lower in a region below a first gate electrode than in other regions between a first source electrode and a first drain electrode, and is controlled by the first gate electrode.

Abstract: Systems and methods for preparing freestanding films using laser-assisted chemical etch (LACE), and freestanding films formed using same, are provided. In accordance with one aspect a substrate has a surface and a portion defining an isotropically defined cavity; and a substantially continuous film is disposed at the substrate surface and spans the isotropically defined cavity. In accordance with another aspect, a substrate has a surface and a portion defining an isotropically defined cavity; and a film is disposed at the substrate surface and spans the isotropically defined cavity, the film including at least one of hafnium oxide (HfO2), diamond-like carbon, graphene, and silicon carbide (SiC) of a predetermined phase. In accordance with still another aspect, a substrate has a surface and a portion defining an isotropically defined cavity; and a multi-layer film is disposed at the substrate surface and spans the isotropically defined cavity.

Abstract: A FET includes a first and second set of finger arrays that each include a source, gate and drain. A first source pad is electrically coupled to source electrodes in the first set of finger arrays. A second source pad is electrically coupled to the source electrodes in the second set of finger arrays. A common drain pad is electrically coupled to drain electrodes in the first and second set of finger arrays. A first gate pad is electrically coupled to gate electrodes in the first set of finger arrays. A second gate pad is electrically coupled to gate electrodes in the second set of finger arrays. A substrate is also provided on which are disposed the first and second set of finger arrays, the first and second source pads, the common drain pad, and the first and second gate pads.

Abstract: Provided is a crack-free epitaxial substrate having excellent breakdown voltage properties in which a silicon substrate is used as a base. The epitaxial substrate includes a (111) single crystal Si substrate and a buffer layer including a plurality of first lamination units. Each of those units includes a composition modulation layer formed of a first composition layer made of AlN and a second composition layer made of AlxGa1-xN being alternately laminated, and a first intermediate layer made of AlyGa1-yN (0?y?1). The relationship of x(1)?x(2)? . . . ?x(n?1)?x(n) and x(1)?x(n) is satisfied, where n represents the number of laminations of each of the first and second composition layers, and x(i) represents the value of x in i-th one of the second composition layers as counted from the base substrate side. The second composition layer is coherent to the first composition layer, and the first intermediate layer is coherent to the composition modulation layer.

Abstract: A compound semiconductor device includes: a substrate; a GaN compound semiconductor multilayer structure disposed over the substrate; and a stress relief layer which is AlN-based and which is disposed between the substrate and the GaN compound semiconductor multilayer structure, wherein a surface of the stress relief layer that is in contact with the GaN compound semiconductor multilayer structure includes recesses that have a depth of 5 nm or more and that are formed at a number density of 2×1010 cm?2 or more.

Abstract: The semiconductor device 100 of this invention includes: a semiconductor layer 2 arranged on the principal surface of a substrate 1 and made of a wide bandgap semiconductor; a trench 5 which is arranged in the semiconductor layer 2 and which has a bottom and a side surface; an insulating region 11 arranged on the bottom and side surface of the trench 5; and a conductive layer 7 arranged in the trench 5 and insulated from the semiconductor layer 2 by the insulating region 11. The insulating region 11 includes a gate insulating film 6 arranged on the bottom and the side surface of the trench 5 and a gap 10 arranged between the gate insulating film 6 and the conductive layer 7 at the bottom of the trench 5. The gate insulating film 6 contacts with the conductive layer 7 on a portion of the side surface of the trench 5 but does not contact with the conductive layer 7 at the bottom of the trench 5.

Abstract: Hybrid semiconductor devices including a PIN diode portion and a Schottky diode portion are provided. The PIN diode portion is provided on a semiconductor substrate and has an anode contact on a first surface of the semiconductor substrate. The Schottky diode portion is also provided on the semiconductor substrate and includes a polysilicon layer on the semiconductor substrate and a ohmic contact on the polysilicon layer. Related Schottky diodes are also provided herein.

Abstract: A nitride semiconductor transistor includes a heterojunction layer including a plurality of nitride semiconductor layers having different polarizations, and a gate electrode disposed on the heterojunction layer. An electron current reduction layer having a p-type conductivity is disposed between the heterojunction layer and the gate electrode to pass hole current therethrough and reduce electron current.

Abstract: A light-emitting diode (LED) structure includes a substrate, a plurality of LED chips, a first colloid, a second colloid, and a lens. The substrate is provided with at least one retaining section, and the LED chips are mounted on the substrate and covered by the first colloid. The second colloid is located to one side of the first colloid opposite to the substrate. The lens is provided with at least one catching section correspondingly engaged with the at least one retaining section, so that the lens is connected to the substrate to form a unitary body through engagement of the catching section with the retaining section and closes the LED chips, the first colloid and the second colloid in between the lens and the substrate. With these arrangements, the LED structure can have upgraded lighting efficiency and allows quick change of LED color temperature or LED beam angle.

Abstract: The present invention relates to a light emitting diode package which can reduce a wire length, and can improve heat and light resistance. The light emitting diode package includes a molded portion having a housing, a plurality of light emitting chips housed in the housing, a plurality of main lead portions having the plurality of light emitting chips mounted thereto respectively, at least one sub-lead portion formed spaced from the main lead portions and electrically connected to at least any one of the plurality of main lead portions and the plurality of light emitting chips with a wire for electrically connecting the plurality of light emitting chips each other.

Abstract: The present invention provides an active matrix substrate in which a peripheral can be narrowed or a gap between adjacent wirings increased to improve a yield. The present invention is an active matrix substrate in which a peripheral region is provided outside a display region. In the active matrix substrate, a first, a second, and a third transistor, a floating wiring, a switching wiring, a main wiring, and a branch wiring electrically connected with the main wiring are arranged in the peripheral region. The floating wiring and branch wiring each electrically connect the first and second transistors and comprise an intersecting portion intersecting with the switching wiring, with the third transistor being provided at the intersecting portion. A gate electrode of the third transistor includes the switching wiring, one of a source electrode and a drain electrode thereof includes the branch wiring, and the other of the source electrode and the drain electrode includes the floating wiring.

Abstract: A lighting device with front carrier, rear carrier and plurality of light-emitting diode chips, which when in operation emits light and releases waste heat, wherein rear carrier is covered at least in selected locations by front carrier, light-emitting diode chips are arranged between rear carrier and front carrier to form array, light-emitting diodes are contacted electrically by rear and/or front carrier and immobilized mechanically by rear carrier and front carrier, front carrier is coupled thermally conductively to light-emitting diode chips and includes light outcoupling face remote from light-emitting diode chips, which light outcoupling face releases some of waste heat released by light-emitting diode chips into surrounding environment, each light-emitting diode chip is actuated with electrical nominal power of 100 mW or less when lighting device is in operation and has light yield of 100 lm/W or more.

Abstract: A packaging device for matrix-arrayed semiconductor light-emitting elements of high power and high directivity comprises a metal base, an array chip and a plurality of metal wires. The metal base is of highly heat conductive copper or aluminum, and a first electrode area and at least one second electrode area which are electrically isolated are disposed on the metal base. The array chip is disposed on the first electrode area, on which multiple matrix-arranged semiconductor light-emitting elements and at least one wire bond pad adjacent to the light-emitting elements are disposed. The light-emitting element is a VCSEL element, an HCSEL element or an RCLED element. The metal wires are connected between the wire bond pad and the second electrode area to transmit power signals. Between the bottom surface and the first electrode area is disposed a conductive adhesive to bond and facilitate electrical connection between the two.

Abstract: An organic light emitting diode (OLED) display includes a red pixel, a green pixel, and a blue pixel. The red pixel, the green pixel and the blue pixel each includes: a pixel electrode; a hole auxiliary layer on the pixel electrode; a blue organic emission layer on the hole auxiliary layer; an electron auxiliary layer on the blue organic emission layer; and a common electrode on the electron auxiliary layer. The red pixel and the green pixel include: a red boundary layer and a green boundary layer, respectively; a red resonance assistance layer and a green resonance assistance layer, respectively; and a red organic emission layer and a green organic emission layer formed between the red resonance assistance layer and the blue organic emission layer, and between the green resonance assistance layer and the blue organic emission layer, respectively.

Abstract: A semiconductor light-emitting device (A) having a simple configuration whereby it is possible to easily and accurately confirm whether or not ultraviolet light is being emitted, the semiconductor light-emitting device comprising: a semiconductor light-emitting element (1) for emitting ultraviolet light in an ultraviolet or deep ultraviolet region; a cap part (6) having a through-hole (63) in the top part through which ultraviolet light passes and encircling the semiconductor light-emitting element (1); a translucent cover (7) for transmitting ultraviolet light, the translucent cover being disposed so as to hermetically close up the through-hole (63); and a UV-excited phosphor (8) which is excited by ultraviolet light and which emits visible light, the UV-excited phosphor being disposed inside the cap part (6).

Abstract: A light emitting device includes: a semiconductor multilayer film formed on a principal surface of a substrate, and including an active layer configured to generate light at a first wavelength; and a fluorescent material layer formed on the semiconductor multilayer film, and forming a first two-dimensional periodic structure. The fluorescent material layer generates light at a second wavelength by being excited by the first wavelength light, the semiconductor multilayer film has an optical waveguide through which the first wavelength light and the second wavelength light are guided, and the light radiated from an end face of the optical waveguide includes a higher proportion of light having an electric field oriented in a direction horizontal to the principal surface than a proportion of light having an electric field oriented in a direction perpendicular to the principal surface.

Abstract: An LED module A1 is provided with: a first lead 1 including a die-bonding portion 12 with a mount surface 12a, and a front-end sunk portion 14; a second lead 2 including a wire-bonding portion 22 and spaced apart from the first lead 1; an LED chip 3 mounted on the mount surface 12a and provided with a first electrode terminal 31 and a second electrode terminal 32; a wire 61 connecting the second electrode terminal 32 and the wire-bonding portion 22; and a support member 4 including a protective portion 42 and supporting the leads 1 and 2. The protective portion covers the front-end sunk portion 14 with the mount surface 12a exposed, and includes an inclined portion 42a that becomes thinner as proceeding from the die-bonding portion 12 toward the lead 2. The arrangements provide a longer lifetime and ensures reliability and proper light emission.

Abstract: A light emitting device 10 includes a light emitting element 11, a package 13 in which the light emitting element 11 is accommodated, and a sealing member 14 configured to seal the light emitting element 11. The package 13 includes a base 13B configured to hold the light emitting element 11 and a frame part 13A vertically standing on the base 13B so as to surround the light emitting element 11. The sealing member 14 is embedded in a region surrounded by the frame part 13A. The frame part 13A includes a protruding wall 15 upwardly protruding from an upper end surface 132a of the frame part 13A and provided so as to surround the light emitting element 11.

Abstract: A semiconductor light emitting device, which includes a light transmissive electrode layer formed using a conductive thin film and an insulating thin film to substitute for a transparent electrode layer, comprises a substrate; a first semiconductor layer formed on the substrate; an active layer formed on the first semiconductor layer; a second semiconductor layer formed on the active layer; a light transmissive electrode layer formed on the second semiconductor layer, the light transmissive electrode layer having a structure in which at least one conductive thin film and at least one insulating thin film are deposited; and a first electrode formed on the light transmissive electrode layer, wherein the light transmissve electrode layer includes at least one contact portion for contacting the at least one conductive thin film with the first electrode.

Abstract: A lead 1 includes a die-bonding portion 11 with an opening 11a penetrating in a thickness direction. Another lead 2 is spaced from the lead 1. An LED unit 3 includes an LED chip 30 with a electrode terminal 31 connected to the lead 1 and another electrode terminal 32 connected to the lead 2. The LED unit 3, mounted on a surface of the die-bonding portion 11 on a first side in z direction, overlaps the opening 11a. A wire 52 connects the lead 2 and the electrode terminal 32. A support member 4 supporting the leads 1-2 is held in contact with another surface of the die-bonding portion 11 on a second side in z direction. These arrangements ensure efficient heat dissipation from the LED chip 30 and efficient use of light emitted from the LED chip 3.

Abstract: Apparatuses, such as memory devices, memory cell strings, and electronic systems, and methods of forming such apparatuses are shown. One such apparatus includes a channel region that has a minority carrier lifetime that is lower at one or more end portions, than in a middle portion. Other apparatuses and methods are also disclosed.

Abstract: A method of forming a Fin-FET is provided. A substrate is provided, then a mask layer is formed thereabove. A first trench is formed in the substrate and the mask layer. A semiconductor layer is formed in the first trench. Next, the mask layer is removed such that the semi-conductive layer becomes a fin structure embedded in the substrate and protruded above the substrate. Finally, a gate layer is formed on the fin structure.

Abstract: A semiconductor device, such as a PMOS or NMOS device, having localized stressors is provided. Recesses are formed on opposing sides of a gate electrode. A stress-inducing region is formed along a bottom of the recess, and a stressed layer is formed over the stress-inducing region. By having a stress-inducing region with a larger lattice structure than the stressed layer, a tensile strain may be created in a channel region of the semiconductor device and may be suitable for an NMOS device. By having a stress-inducing region with a smaller lattice structure than the stressed layer, a compressive strain may be created in the channel region of the semiconductor device and may be suitable for a PMOS device. Embodiments may be applied to various types of substrates and semiconductor devices, such as planar transistors and finFETs.

Abstract: The present invention is related to a method for manufacturing a low defect interface between a dielectric material and an III-V compound. More specifically, the present invention relates to a method for manufacturing a passivated interface between a dielectric material and an III-V compound. The present invention is also directed to a device comprising a low defect interface between a dielectric material and an III-V compound that has improved performance.

Abstract: A non-volatile memory device according to an aspect of the present disclosure includes a substrate, a plurality of word lines stacked over the substrate and having a stepwise pattern, wherein the plurality of word lines each have a pad region, and a plurality of contact plugs coupled to the respective pad regions of the word lines, wherein a width of a pad region of a first one of the plurality of word lines is greater than a width of a pad region of a second word line lower than the first word line.

Abstract: The present disclosure provides one embodiment of a motion sensor structure. The motion sensor structure includes a first substrate having an integrated circuit formed thereon; a second substrate bonded to the first substrate from a first surface, wherein the second substrate includes a motion sensor formed thereon; and a third substrate bonded to a second surface of the second substrate, wherein the third substrate includes a recessed region aligned with the motion sensor.

Abstract: An integrated circuit includes a gate electrode disposed over a substrate. A source/drain (S/D) region is disposed adjacent to the gate electrode. The S/D region includes a diffusion barrier structure disposed in a recess of the substrate. The diffusion barrier structure includes a first portion and a second portion. The first portion is adjacent to the gate electrode. The second portion is distant from the gate electrode. An N-type doped silicon-containing structure is disposed over the diffusion barrier structure. The first portion of the diffusion barrier structure is configured to partially prevent N-type dopants of the N-type doped silicon-containing structure from diffusing into the substrate. The second portion of the diffusion barrier structure is configured to substantially completely prevent N-type dopants of the N-type doped silicon-containing structure from diffusing into the substrate.

Abstract: Semiconductor device manufacturing methods and methods of forming insulating material layers are disclosed. In one embodiment, a method of forming a composite insulating material layer of a semiconductor device includes providing a workpiece and forming a first sub-layer of the insulating material layer over the workpiece using a first plasma power level. A second sub-layer of the insulating material layer is formed over the first sub-layer of the insulating material layer using a second plasma power level, and the workpiece is annealed.

Abstract: A fabricating method of a shallow trench isolation structure includes the following steps. Firstly, a substrate is provided, wherein a high voltage device area is defined in the substrate. Then, a first etching process is performed to partially remove the substrate, thereby forming a preliminary shallow trench in the high voltage device area. Then, a second etching process is performed to further remove the substrate corresponding to the preliminary shallow trench, thereby forming a first shallow trench in the high voltage device area. Afterwards, a dielectric material is filled in the first shallow trench, thereby forming a first shallow trench isolation structure.

Abstract: A multiphase ultra low k dielectric process incorporating an organo-silicon precursor including an organic porogen, high frequency radio frequency power just above plasma initiation in a PECVD chamber and energy post treatment. A porous SiCOH dielectric material having a k less than 2.7 and a modulus of elasticity greater than 7 GPa. A graded carbon adhesion layer of SiO2 and porous SiCOH.

Abstract: The present invention discloses a strained channel field effect transistor and a method for fabricating the same. The field effect transistor comprises a substrate, a source/drain, a gate dielectric layer, and a gate, characterized in that, an “L” shaped composite isolation layer, which envelops a part of a side face of the source/drain adjacent to a channel and the bottom of the source/drain, is arranged between the source/drain and the substrate; the composite isolation layer is divided into two layers, that is, an “L” shaped insulation thin layer contacting directly with the substrate and an “L” shaped high stress layer contacting directly with the source and the drain. The field effect transistor of such a structure improves the mobility of charge carriers by introducing stress into the channel by means of the high stress layer, while fundamentally improving the device structure of the field effect transistor and improving the short channel effect suppressing ability of the device.

Abstract: A method for manufacturing a semiconductor device includes forming a contact etch stop layer on an active area of a substrate that has a gate stack formed thereon. The gate stack includes a metal gate and a metal oxide. The contact etch stop layer includes a silicon oxide layer sandwiched between a first and a silicon nitride layers, the second silicon nitride layer is disposed on the active area. The method further includes forming a contact hole extending through an interlayer dielectric layer on the first silicon nitride layer using the first silicon nitride layer as a protection for the active area, removing a portion the first silicon nitride layer disposed at the bottom of the contact hole using the silicon oxide layer as a protection for the active area, and removing the metal oxide using the second silicon nitride layer as a protection for the active area.

Abstract: The present invention provides a method for manufacturing a semiconductor structure, which comprises: providing a substrate, and forming a dielectric layer and a dummy gate layer on the substrate; performing doping and annealing to the dummy gate layer; patterning the dummy gate layer to form a dummy gate, wherein the top cross section of the dummy gate is larger than the bottom cross section of the dummy gate; forming sidewall spacers and source/drain regions; depositing an interlayer dielectric layer and planarizing the same; removing the dummy gate to form an opening within the sidewall spacers; and forming a gate in the opening. Accordingly, the present invention further provides a semiconductor structure.

Abstract: A method of fabricating a semiconductor device includes forming an interlayer dielectric on a substrate, the interlayer dielectric including first and second openings respectively disposed in first and second regions formed separately in the substrate; forming a first conductive layer filling the first and second openings; etching the first conductive layer such that a bottom surface of the first opening is exposed and a portion of the first conductive layer in the second opening remains; and forming a second conductive layer filling the first opening and a portion of the second opening.

Abstract: A device includes a semiconductor substrate and a gate insulation film lining a trench in an active region of the substrate. A gate electrode pattern is recessed in the trench on the gate insulation film and has an upper surface that has a nonuniform height. A dielectric pattern may be disposed on the gate electrode pattern in the trench.

Abstract: In one exemplary embodiment of the invention, a semiconductor structure includes: a substrate; and a plurality of devices at least partially overlying the substrate, where the plurality of devices include a first device coupled to a second device via a first raised source/drain having a first length, where the first device is further coupled to a second raised source/drain having a second length, where the first device comprises a transistor, where the first raised source/drain and the second raised source/drain at least partially overly the substrate, where the second raised source/drain comprises a terminal electrical contact, where the second length is greater than the first length.

Abstract: A method of manufacturing a 3-Dimensional (3-D) non-volatile memory device includes forming first material layers and second material layers alternately, forming at least one first trench by etching the first material layers and the second material layers, forming floating gate regions by recessing the second material layers, exposed to the first trench, forming a first charge blocking layer on surfaces of the first trench and the floating gate regions, forming a first conductive layer on the first charge blocking layer, etching the first conductive layer on the upper side of the first trench, forming a second charge blocking layer on the first charge blocking layer exposed by etching the first conductive layer, and forming floating gates in the respective floating gate regions by etching the first conductive layer.

Abstract: A method of forming a semiconductor structure is provided. A substrate having a cell area and a periphery area is provided. A stacked structure including a gate oxide layer, a floating gate and a first spacer is formed on the substrate in the cell area and a resistor is formed on the substrate in the periphery area. At least two doped regions are formed in the substrate beside the stacked structure. A dielectric material layer and a conductive material layer are sequentially formed on the substrate. A patterned photoresist layer is formed on the substrate to cover the stacked structure and a portion of the resistor. The dielectric material layer and the conductive material layer not covered by the patterned photoresist layer are removed, so as to form an inter-gate dielectric layer and a control gate on the stacked structure, and simultaneously form a salicide block layer on the resistor.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a plurality of gate electrode structures formed on a semiconductor substrate and an insulating film which covers the gate electrode structures and has an air gap in it. Each of the gate electrode structures includes a gate insulting film, a charge storage layer, an intermediary insulating film, and a control gate electrode. The control gate electrode includes a first control gate and a second control gate whose width is greater than that of the first control gate. The air gap is formed so as to be higher than a space between the control gate electrodes and than the control gate electrodes.

Abstract: Each insulating gate portion forms a channel in part of a first well region located between a drift region and source region. A first main electrode forms junctions with part of the drift region exposed in the major surface of the drift region to constitute unipolar diodes and is connected to the first well regions and the source regions. The plurality of insulating gate portions have linear patterns parallel to each other when viewed in the normal direction of the major surface. Between each pair of adjacent insulating gate portions, junction portions in which the first main electrode forms junctions with the drift region and the first well regions are arranged along the direction that the insulating gate portions extend. The channels are formed at least in the normal direction of the major surface.

Abstract: According to example embodiments, a semiconductor device includes a plurality of active pillars protruding from a substrate. Each active pillar includes a channel region between upper and lower doped regions. A contact gate electrode faces the channel region and is connected to a word line. The word line extends in a first direction. A bit line is connected to the lower doped region and extends in a second direction. The semiconductor device further includes a string body connection portion that connects the channel region of at least two adjacent active pillars of the plurality of active pillars.

Abstract: In one embodiment, a source-down vertical insulated gate field effect transistor includes a source contact that is buried within a trench gate structure. Dopant of a first conductivity type is diffused from the conductive source contact into an adjacent semiconductor layer that has a second and opposite conductivity type to form source regions. A self-aligned metal contact is formed within the trench gate structure to short the source contact and the source regions to an underlying substrate.