Abstract: In a semiconductor device, a lead frame made of a copper alloy prevents exfoliation occurring near the surface of the lead frame. A copper oxide layer is formed on the base material made of a copper alloy by immersing the base material into a solution of a strong oxidizer. The copper oxide layer serves as an outermost layer and consists of a copper oxide other than a copper oxide in the form of needle crystals.

Abstract: A first presspin includes a foot, whereby a base of the foot is provided for contacting a contact element of a power semiconductor device, such as within a power semiconductor module including a base plate and at least one power semiconductor device, which is arranged on the base plate and contacted by at least one further presspin. An insulation means is provided for electrically an outer surface of the foot. A power semiconductor module is also provided including a base plate, at least one power semiconductor device arranged on the base plate, and at least one of the aforementioned first presspin provided with the aforementioned insulation means. A power semiconductor module assembly is also provided including multiple power semiconductor modules as specified above, whereby the power semiconductor modules are arranged side by side to each other with electric connections between adjacent power semiconductor modules.

Abstract: A power semiconductor arrangement includes a base plate having a molybdenum layer, and a power semiconductor device mounted to a top side of the base plate and electrically and thermally coupled thereto. The base plate includes a metallic mounting base, which is arranged between the semiconductor device and the molybdenum layer and prevents the molybdenum layer from forming highly resistive intermetallic phases with the semiconductor device. A semiconductor module, such as a power semiconductor module, includes multiple semiconductor arrangements, whereby the base plate of the semiconductor arrangements is a common base plate. A module assembly, such as a power semiconductor module assembly, includes multiple semiconductor modules, whereby the semiconductor modules are arranged side by side to each other with electric connections between adjacent semiconductor modules.

Abstract: A diode structure includes a body, a first electrode, and a second electrode. The body has a longitudinal length and a transverse length. The first electrode has an end extending into the body along the longitudinal length, and has another end extending outwardly and horizontally from the body for a predetermined length. The second electrode lying on another side of the body to oppose the first electrode, has a tail extending into the body, and has another tail extending outward and horizontally from the body for the predetermined length. The predetermined length of the first electrode and the second electrode is no less than the longitudinal length of the body. Therefore, the diode structure features two electrodes with increased exposed surfaces and better heat dissipation.

Abstract: A semiconductor device includes a wiring substrate, a first semiconductor chip mounted on the wiring substrate, and a second semiconductor chip mounted on the wiring substrate. The second semiconductor chip generates less heat than the first semiconductor chip. A heat dissipation plate is arranged on the wiring substrate and partially at a higher location than the first and second semiconductor chips. The heat dissipation plate is connected to the first semiconductor chip and includes an opening formed at a location corresponding to an upper surface of the second semiconductor chip. The upper surface of the second semiconductor chip is entirely exposed from the heat dissipation plate through the opening.

Abstract: A microelectronic package includes a subassembly including a first substrate and first and second microelectronic elements having contact-bearing faces facing towards oppositely-facing first and second surfaces of the first substrate and each having contacts electrically connected with the first substrate. The contact-bearing faces of the first and second microelectronic elements at least partially overlie one another. Leads electrically connect the subassembly with a second substrate, at least portions of the leads being aligned with an aperture in the second substrate. The leads can include wire bonds extending through an aperture in the first substrate and joined to contacts of the first microelectronic element aligned with the first substrate aperture. In one example, the subassembly can be electrically connected with the second substrate using electrically conductive spacer elements.

Abstract: A device includes a metal pad over a substrate. A passivation layer includes a portion over the metal pad. A post-passivation interconnect (PPI) is electrically coupled to the metal pad, wherein the PPI comprises a portion over the metal pad and the passivation layer. A polymer layer is over the PPI. A dummy bump is over the polymer layer, wherein the dummy bump is electrically insulated from conductive features underlying the polymer layer.

Abstract: A package stack structure may an upper package include an upper package substrate having a first edge and a second edge opposite to the first edge. The upper package substrate has a first region arranged near the first edge and a second region arranged near the second edge. A first upper semiconductor device is mounted on the upper package substrate. The package stack structure may also include a lower package having a lower package substrate and a lower semiconductor device. The lower package is connected to the upper package through a plurality of inter-package connectors. The plurality of the inter-package connectors may include first inter-package connectors configured to transmit data signals; second inter-package connectors configured to transmit address/control signals; third inter-package connectors configured to provide a supply voltage for an address/control circuit; and fourth inter-package connectors configured to provide a supply voltage for a data circuit.

Abstract: A semiconductor apparatus, including: a semiconductor component; a Cu stud bump that is formed on the semiconductor component; and a solder bump configured to electrically connect to the Cu stud bump.

Abstract: A method for encapsulating electronic components, including the steps of: forming, in a first surface of a semiconductor wafer, electronic components; forming, on the first surface, an interconnection stack including conductive tracks and vias separated by an insulating material; forming first and second bonding pads on the interconnection stack; thinning down the wafer, except at least on its contour; filling the thinned-down region with a first resin layer; arranging at least one first chip on the first bonding pads and forming solder bumps on the second bonding pads; depositing a second resin layer covering the first chips and partially covering the solder bumps; bonding an adhesive strip on the first resin layer; and scribing the structure into individual chips.

Abstract: Embodiments of the present disclosure provide a package on package arrangement comprising a bottom package and a second package. The first package includes a substrate layer including (i) a top side and (ii) a bottom side that is opposite to the top side. Further, the top side defines a substantially flat surface. The first package also includes a die coupled to the bottom side of the substrate layer. The second package includes a plurality of rows of solder balls, and the second package is attached to the substantially flat surface of the substrate layer via the plurality of rows of solder balls.

Abstract: Semiconductor dice comprise at least one bond pad on an active surface of the semiconductor die. At least one blind hole extends from a back surface of the semiconductor die opposing the active surface, through a thickness of the semiconductor die, to an underside of the at least one bond pad. At least one quantity of passivation material covers at least a sidewall surface of the at least one blind hole. At least one conductive material is disposed in the at least one blind hole adjacent and in electrical communication with the at least one bond pad and adjacent the at least one quantity of passivation material.

Abstract: Disclosed herein are various methods of forming methods of forming a non-planar cap layer above a conductive line on a semiconductor device, and to devices incorporating such a non-planar cap layer. In one illustrative example, the method includes forming a conductive structure in a layer of insulating material, recessing an upper surface of the conductive structure relative to an upper surface of the layer of insulating material such that the recessed upper surface of the conductive structure and the upper surface of the layer of insulating material are positioned in different planes and, after recessing the upper surface of the conductive structure, forming a first cap layer on the conductive structure and the layer of insulating material.

Abstract: The present application discloses a method of manufacturing a semiconductor structure. According to at least one embodiment, a first etch stop layer is formed over a conductive feature and a substrate, and the conductive feature is positioned over the substrate. A second etch stop layer is formed over the first etch stop layer. A first etch is performed to form an opening in the second etch stop layer, and the opening exposes a portion of the first etch stop layer. A second etch is performed to extend the opening downwardly by removing a portion of the exposed first etch stop layer, and the extended opening exposes a portion of the conductive feature.

Abstract: A local interconnect structure is provided in which a tungsten region, i.e., tungsten stud, that is formed within a middle-of-the-line (MOL) dielectric material is not damaged and/or contaminated during a multiple interconnect patterning process. This is achieved in the present disclosure by forming a self-aligned tungsten nitride passivation layer within a topmost surface and upper sidewalls portions of the tungsten region that extend above a MOL dielectric material which includes a first interconnect pattern formed therein. During the formation of the self-aligned tungsten nitride passivation layer, a nitrogen enriched dielectric surface also forms within exposed surface of the MOL dielectric material. A second interconnect pattern is then formed adjacent to, but not connect with, the first interconnect pattern. Because of the presence of the self-aligned tungsten nitride passivation layer on the tungsten region, no damaging and/or contamination of the tungsten region can occur.

Abstract: Disclosed herein are various methods of forming a replacement gate comprised of silicon and various semiconductor devices incorporation such a replacement gate structure. In one example, the method includes removing a sacrificial gate electrode structure to define a gate opening, forming a replacement gate structure in the gate opening, the replacement gate structure including at least one metal layer and a silicon-containing gate structure that is at least partially made of a metal silicide and forming a protective layer above at least a portion of the replacement gate structure.

Abstract: A semiconductor arrangement includes a circuit carrier, a bonding wire and at least N half bridge circuits. N is an integer that amounts to at least 1. The circuit carrier includes a first metallization layer, a second metallization layer, an intermediate metallization layer arranged between the first metallization layer and the second metallization layer, a first insulation layer arranged between the intermediate metallization layer and the second metallization layer, and a second insulation layer arranged between the first metallization layer and the intermediate metallization layer. Each of the half bridge circuits includes a first circuit node, a second circuit node and a third circuit node, a controllable first semiconductor switch and a controllable second semiconductor switch.

Abstract: According to one embodiment, between the mounting substrate and the semiconductor chip, there is a joint support layer including a metal or its alloy selected from the group of Cu, Al, Ag, Ni, Cr, Zr and Ti and a melt layer laminated across the joint support layer, and formed of a metal selected from the group of Sn, Zn and In or of an alloy of at least two metals selected from the same metals. The process of joining the mounting substrate and the semiconductor chip includes intervening a joining layer which is formed, at least for its outermost layer, by the melt layer, maintaining the temperature to be higher than the melting point of the melt layer, then forming an alloy layer which has a higher melting point than the melt layer by liquid phase diffusion.

Abstract: Thermal transfer from a silicon-on-insulator (SOI) die is improved by mounting the die in a bump-on-leadframe manner in a semiconductor package, with solder or other metal bumps connecting the active layer of the SOI die to metal leads used to mount the package on a printed circuit board or other support structure.

Abstract: A method of layout of pattern includes the following processes. A graphic data of a first wiring in a first area of a semiconductor wafer is extracted. The first area is a semiconductor chip forming area. The first area is surrounded by a scribed area of the semiconductor wafer. The first area includes a second area. The second area is bounded with the scribed area. The second area has a second distance from a boundary between the semiconductor chip forming area and the scribed area to an boundary between the first area and the second area. A first dummy pattern in the first area is laid out. The first dummy pattern has at least a first distance from the first wiring. A second dummy pattern in the second area is laid out. The second dummy pattern has at least the first distance from the first wiring. The second dummy pattern has at least a third distance from the first dummy pattern.

Abstract: Some embodiments include methods of forming interconnects. A first circuitry level may be formed, and a first dielectric region may be formed over such first level. A second level of circuitry may be formed over the first dielectric region. An interconnect may be formed to extend through such second level. A second dielectric region may be formed over the second level of circuitry, and a third level of circuitry may be formed over the second dielectric region. The third level of circuitry may be electrically connected to the first level of circuitry through the interconnect. Some embodiments include constructions having interconnects extending from a first level of circuitry, through an opening in a second level of circuitry, and to a third level of circuitry; with an individual interconnect including multiple separate electrically conductive posts.

Abstract: Mechanisms of forming a bond pad structure are provided. The bond pad has a recess region, which is formed by an opening in the passivation layer underneath the bond pad. An upper passivation layer covers at least the recess region of the bond pad to reduce trapping of patterning and/or etching residues in the recess region. As a result, the likelihood of bond pad corrosion is reduced.

Abstract: Chip package processes and chip package structures are provided. The chip package structure includes a substrate, a chip, an insulating layer, a third patterned conductive layer and an electronic element. The substrate has a first patterned conductive layer. The chip is disposed on the substrate. A second patterned conductive layer of the chip is bonded to the first patterned conductive layer of the substrate. The chip has a first through hole. The insulating layer is disposed on the chip and filled into the first through hole. The insulating layer has a second through hole which passes through the first through hole. The third patterned conductive layer is disposed on the insulating layer and filled into the second through hole to electrically connect to the first patterned conductive layer. The electronic element is disposed on the third patterned conductive layer and electrically connects to the third patterned conductive layer.

Abstract: Methods of forming semiconductor devices include providing a substrate including a layer of semiconductor material on a layer of electrically insulating material. A first metallization layer is formed over a first side of the layer of semiconductor material. Through wafer interconnects are foamed at least partially through the substrate. A second metallization layer is formed over a second side of the layer of semiconductor material opposite the first side thereof. An electrical pathway is provided that extends through the first metallization layer, the substrate, and the second metallization layer between a first processed semiconductor structure carried by the substrate on the first side of the layer of semiconductor material and a second processed semiconductor structure carried by the substrate on the first side of the layer of semiconductor material. Semiconductor structures are fabricated using such methods.

Abstract: Disclosed is a memory card which includes a universal PCB including a first pad group and a second pad group, the first and second pad groups being connected to each other via one or more PCB wires, a first semiconductor chip electrically connected with at least one pad of the first pad group via a first bonding wire, and a second semiconductor chip electrically connected with at least one pad of the second pad groups via a second bonding wire, wherein the first bonding wire or the second bonding wire is changed according to a combination of the first and second semiconductor chips without a change in the PCB wires.

Abstract: A method and/or an apparatus of core timing prediction is disclosed. In one embodiment, a method may include generating a core timing model of a core logic that is accurately transferable to any chip-level integration process. The method may reduce performance degradation and/or performance variation of the core logic caused by a number of interactions between core logic components and chip-level components in the chip-level integration process. In addition, the core timing model of the core logic may be generated by filling un-wired tracks with metal in any of an outermost layer of the core logic after a core logic routing and constructing a layer at least an area of and adjacent to any of the outermost layer of the core logic with grounded metal that is orthogonal to those of the metal used in the outermost layer of the core logic.

Abstract: The present invention relates to a method for forming a raised conductive image on a non-conductive or dielectric surface, the method comprising placing a metal coordination complex on a surface of the substrate, exposing the surface to electromagnetic radiation, reducing the exposed complex. removing unexposed complex leaving an elemental metal image, removing unexposed metal complex and then plating the resulting elemental metal image with a highly conductive material.

Abstract: According to one embodiment, a semiconductor device includes a first insulating layer provided in a first area and in a second area, a line-and-space-like second insulating layer formed on the first insulating layer provided in the first area, and a third insulating layer formed on the first insulating layer provided in the second area and which is substantially identical to the second insulating layer in height.

Abstract: The present invention provides a natural evaporation humidifier which is space and energy efficient and maximizes humidification efficiency by enhancing diffusion of the moistened air. It is much easy and convenient for users to use, operate and carry the natural evaporation humidifier. The natural evaporation humidifier comprises a container, a plurality of inner support portions, a plurality of tunnels, a plurality of auxiliary support portions, a plurality of evaporation filters, and a plurality of support legs. The container, having a front and back wall, bottom, and side walls, forms an interior compartment and a water reservoir with the inner support portions. The inner support portions are shaped in curve, vertically attached to the bottom of the container, arranged in parallel along the length direction of the container to form a plurality of tunnels and evaporation filter housing areas. The inner support portions have a plurality of spacers inside each tunnel.

Abstract: A method and system for generating an optical fiber is provided. The method includes creating a green fiber consisting primarily of a ceramic material and sintering the green fiber with a laser by moving the green fiber through a beam of the laser to increase the density of the fiber after sintering. The system for creating a continuous optical fiber includes an extruder, a processing chamber and a laser. The extruder is configured to extrude a ceramic slurry as a green fiber. The processing chamber is configured to receive and process the green fiber. And, the laser is configured to direct a laser spot on the green fiber exiting the processing chamber to sinter the green fiber.

Abstract: An apparatus for correcting any warping of a light guide plate includes a retaining device and a heating device. The retaining device includes a top pressing plate, a bottom supporting plate and an oil hydraulic cylinder on the top pressing plate. The oil hydraulic cylinder applies a pressing force on the top pressing plate, and the top pressing plate and the bottom supporting plate cooperatively sandwich and retain a light guide plate. The heating device has a coil of wire for surrounding the light guide plate. The coil of wire is configured for heating the light guide plate, the pressure and the heat thereby correcting the warp of the light guide plate. A method for correcting a warp of a light guide plate is also provided.

Abstract: The purpose of the present invention is to make a change in the chromaticity of an optical member due to use unlikely to occur. A method of manufacturing a prism sheet 23c as an optical member 23 to be used in a backlight unit 12 that supplies light to a liquid crystal panel 11 and transmits light from LEDs 24 as light sources of the backlight unit 12, includes a step of stabilizing the chromaticity of transmitted light by irradiation with light from chromaticity stabilizing LEDs 32 as chromaticity stabilizing light sources having a dominant emission wavelength in a blue wavelength region.

Abstract: A contact lens of novel structure that can be produced with enhanced production efficiency and that has an enhanced water retainability on the lens surface so as to realize a superior wear feeling. At least one of convex lens anterior surface and concave lens posterior surface is provided with treated face having a periodic structure of minute projections and depressions of a size producing no tactile and visual effects during wear.

Abstract: A method of manufacturing gel particles adapted to apply a voltage to a liquid ejection head to eject a liquid including a polymeric material toward an ejection target liquid to thereby manufacture the gel particles, includes: raising the voltage from a first voltage to a second voltage at a first gradient; raising the voltage from the second voltage to a third voltage at a second gradient steeper than the first gradient at which the voltage is raised from the first voltage to the second voltage, and then holding the voltage at the third voltage; dropping the voltage from the third voltage to a fourth voltage, and then holding the voltage at the fourth voltage; raising the voltage from the fourth voltage to a fifth voltage at a third gradient, wherein the third gradient is gentler than the second gradient.

Abstract: Provided are methods for encapsulating substances. In certain methods, the capsule walls are obtained by interfacial reaction, wherein the interfacial reaction is carried out in a centrifugal reactor with rotating packing.

Abstract: Rapid and accurate determination of the formulation orientation of multi-layer capsule-shaped tablets with respect to different internal formulation layers proximate to the opposite narrow and rounded ends of the tablets is required. By including an appropriate color scheme in multi-layer osmotic tablets, detection of the formulation orientation is achieved by detecting the color at a spot location on a side of the tablet corresponding to one or another formulation layer or to one or another interface of two formulation layers depending on the formulation orientation of the tablet.

Abstract: A method for producing a polyolefin microporous membrane, comprising the following steps (A) to (D): (A) a kneading step of kneading a polyolefin resin, a plasticizer, and an antioxidant to form a kneaded material; (B) a molding step of processing the kneaded material into a sheet-shaped molded form after the kneading step; (C) a stretching step of stretching the sheet-shaped molded form to form a stretched material, after the molding step; and (D) a porous sheet forming step of extracting the plasticizer from the stretched material to form a porous sheet, before and/or after the stretching step, wherein the step (A) is a step of kneading the plasticizer to which 0.05 to 5% by mass of the antioxidant based on the polyolefin resin is added, and the polyolefin resin.

Abstract: A method for manufacturing an endless belt includes coating a solution containing a polyimide precursor and conductive particles on the circumferential surface of a core to form a first coating film, drying the first coating film so that the residual amount of a solvent of the first coating film falls within a range of from about 10% to about 20% in respective portions, coating a solution containing a polyimide precursor and conductive particles on the dried first coating film to form a second coating film, drying the second coating film, heating the first dried coating film and the dried second coating film so that the polyimide precursors are imidized, and removing the first coating film and the second coating film heated in the heating of the first coating film and second coating film from a core.

Abstract: A method of forming a composite article by injecting at least two composite materials comprising metal carbides into a mold to form a green compact is disclosed. The composite materials may be metal powders comprising a binder metal, a hard particle. The composite material may further comprise a plastic binder. The two different composite materials are injected into the mold to form the green compact. Additionally, the composite materials may be injected through a die before entering the mold. In a specific embodiment, the die forms at least one internal channel within the green compact.

Abstract: A device and a method for producing pellets from a melt, having a perforated plate with melt nozzles located therein from which nozzles the melt emerges. The perforated plate is located opposite a cutter arrangement with a cutter head with at least one blade, and a cutter shaft driven by a motor so that the at least one blade passes over the melt nozzles in the perforated plate in a rotating manner and in doing so severs pellets of the melt material emerging there. The cutter shaft is at least axially displaceable relative to a process chamber housing by means of at least one adjustable bearing. The position of the at least one blade can be determined and adjusted using a position sensing and adjusting device.

Abstract: A method of manufacturing a three-dimensional wood product including a curved face includes: softening a blank formed of a bowl-shaped wood; compressing the blank, the compressing being deforming the softened blank into a bowl shape different from that before the softening, by applying a compressive force to the blank; fixing the shape of the deformed blank by applying the compressive force; drying the fixed blank; and heat-shaping the blank, the heat-shaping being shaping the dried blank into a shape similar to the shape of the blank while heating the blank in the ambient air. The blank after the drying and before the heat-shaping has an inner face of the bowl shape, the inner face having a shape closer to a final shape to be achieved after the heat-shaping than a shape of an outer face of the bowl shape, and a surface area of the outer face is larger than that of an outer face of the final shape.

Abstract: The invention is directed to a processes for manufacturing golf balls having multi-layered covers including a very thin outermost thermoplastic cover layer and a thermoset uniformly contoured inner cover layer having a uniform thickness.

Abstract: A seal comprising a sealing ring (1) and a slide ring (2) wherein the slide ring (2) is provided on the side of the sealing ring (1) that faces the surface to be sealed. The sealing ring (1) and the slide ring (2) are designed in one piece by molding the sealing ring (1) to the slide ring (2) in a mold cavity that forms the slide ring into a cylindrical shape.

Abstract: A cylindrical core member for manufacturing a tubular member by curing a resin solution coated on an outer circumferential surface thereof, includes a substrate, a releasing layer that is formed on the outer circumferential surface including a central portion of the substrate in the axial direction, and plural low releasing portions having lower releasing properties than the releasing layer at both end portions of the substrate in the axial direction, the plural low releasing portions being intermittently disposed on the outer circumferential surface in the circumferential direction, and present in some places in the axial direction of the core member main body at the circumferential of the core member main body at both end portions of the substrate in the axial direction.

Abstract: The method to make the toner container provides a toner container exhibiting reduced environmental load and excellent strength together with moldability. The method is a blow molding method. The method employs a resin containing at least one of polyethylene and polypropylene formed from raw material prepared via a fermentation method.

Abstract: An apparatus for shaping plastics material pre-forms into plastics material containers with a blow mould which has at least two blow mould parts which are arranged so as to be movable with respect to each other on first and second blow mould carrier parts. A pressure pad arrangement is arranged between at least one blow mould carrier part and the blow mould part.

Abstract: The invention relates to a plain bearing for an underwater power plant, comprising at least one plain bearing segment for forming a first plain bearing shell; at least one running element of a second plain bearing shell, the running element forming the counter bearing surface to the plain bearing segment, the sliding surface of the running element having a higher hardness than the sliding surface of the plain bearing segment; a carrying element for the running element; characterized in that an intermediate layer having an adjustable plastic deformability is arranged between the running element and a carrying element.

Abstract: A green molded body comprises an organic binder and an inorganic compound source powder containing an aluminum source powder and a titanium source powder, wherein the organic binder is such that the viscosity at 20° C. of a 2 wt % aqueous solution of the organic binder is 5000 mPa·s or higher. A method for producing an aluminum titanate fired body includes the steps of molding a raw material mixture comprising an organic binder and an inorganic compound source powder containing an aluminum source powder and a titanium source powder to obtain a green molded body; heating the green molded body obtained at 150° C. to 900° C. to remove the organic binder; and firing the green molded body from which the organic binder has been removed, at 1300° C. or higher, wherein the organic binder is such that the viscosity at 20° C. of a 2 wt % aqueous solution of the organic binder is 5000 mPa·s or higher.

Abstract: A cap for mounting on a damper tube of a vibration damper, having an outer shell region that is cylindrical at least in sections and at least one elastic spring tongue. At least one positively locking element is arranged on the spring tongue in order to produce a positively locking connection between the cap and a protective element of the vibration damper. The at least one spring tongue has a region which, in the non-mounted state of the cap, is set back inwardly in the radial direction with respect to the outer shell region. The set- back region has a spreading element, by way of which the spring tongue is spread outwardly in the radial direction during the mounting of the cap.

Abstract: A partition member for partitioning a primary liquid chamber and a secondary liquid chamber is provided with a damping orifice passage and an elastic partition member. A stopper leg portion is integrally formed with and projects from a lower wall of an elastic diaphragm portion provided in a central region of the elastic partition member 30 so as to be pressed on a pressed surface of a support wall of a frame member. A third liquid chamber is defined by the support wall, the elastic partition member and the stopper leg portion and is opened in the vicinity of a primary liquid chamber side opening of the damping orifice passage through a relief passage. The pressed surface is increased in diameter as it goes upward.