Abstract: Electronic devices comprising a dielectric material, at least one carbon sheet, and two electrode terminals are described herein. The devices exhibit non-linear current-versus-voltage response over a voltage sweep range in various embodiments. Uses of the electronic devices as two-terminal memory devices, logic units, and sensors are disclosed. Processes for making the electronic devices are disclosed. Methods for using the electronic devices in analytical methods are disclosed.

Abstract: Provided is a method for amplifying a frequency variation of a detected signal in a biosensor that is used for detecting a biomolecule by measuring a change in frequency of an oscillating signal, the change being caused by pressure a biomolecule applies to a piezoelectric substance. The method for amplifying a frequency variation of a detected signal comprises the steps of: (a) applying a sample to a probe being fixed to an upper portion of a substrate of the biosensor to allow a biomolecule in the sample to be bound to the probe; (b) applying protein tagged with a metal particle to the biosensor to allow the protein and the biomolecule to be bound with each other; and (c) applying a metal enhancer to the biosensor to allow the metal enhancer to be bound to the metal particle having been bound to the protein.

Abstract: A method for increasing a spectroscopic signal in a biological assay is provided. The method includes forming a suspension of magnetically attractable particles. The method also includes introducing a first magnetic field at a first location to draw the magnetically attractable particles towards the first location and form a first agglomeration. The method also includes removing the first magnetic field. The method further includes introducing a second magnetic field at a second location to draw the first agglomeration towards the second location and form a second agglomeration. The method further includes focusing an excitation source on the second agglomeration formed at the second location.

Abstract: The disclosure relates to a fabrication process of a biosensor on a semiconductor wafer, comprising steps of: making a central photosensitive zone comprising at least one pixel-type biological analysis device comprising a photosensitive layer, and a first peripheral zone surrounding the central photosensitive zone, comprising electronic circuits. The first peripheral zone is covered by a hydrophilic coating, and the central photosensitive zone is covered with a hydrophobic coating. A barrier of a bio-compatible resin is formed on the second peripheral zone.

Abstract: A method of flash-RAM memory includes non-volatile random access memory (RAM) formed on a monolithic die and non-volatile page-mode memory formed on top of the non-volatile RAM, the non-volatile page-mode memory and the non-volatile RAM reside on the monolithic die. The non-volatile RAM is formed of stacks of magnetic memory cells arranged in three-dimensional form for higher density and lower costs.

Abstract: A stacking apparatus that stacks chip assemblies each having a plurality of chips disposed continuously with circuit patterns and electrodes, includes: a plurality of stages each allowed to move arbitrarily, on which the chip assemblies are placed; a storage unit that stores an estimated extent of change in a position of an electrode at each chip, expected to occur as heat is applied to the chip assemblies placed on the plurality of stages during a stacking process; and a control unit that sets positions of the plurality of stages to be assumed relative to each other during the stacking process based upon the estimated extent of change in the position of the electrode at each chip provided from the storage unit and position information indicating positions of individual chips formed at the chip assemblies and controls at least one of the plurality of stages.

Abstract: A method for etching features into an etch layer in a plasma processing chamber is provided. An optically timed deposition phase is provided comprising providing a flow of deposition phase gas, detecting the presence of deposition gas within the plasma processing chamber, providing RF energy for forming a plasma from the deposition phase gas in the plasma processing chamber, and stopping the flow of the deposition gas into the plasma processing chamber. An optically timed etching phase is provided, comprising providing a flow of an etch gas, detecting the presence of the etch gas within the plasma processing chamber, providing RF energy for forming a plasma from the etch gas in the plasma processing chamber, and stopping the flow of the etch gas into the plasma processing chamber.

Abstract: A chip quality determination method includes the steps of (a) determining the continuity of defective chips in at least four directions of an X-axis and a Y-axis on a wafer based on the wafer test result of determining the acceptability of chips arranged in a matrix in the four directions on the wafer, and dividing the defective chips into one or more defective groups so that successive ones of the defective chips are in the same defective group; (b) calculating a quality determination index of each of one or more determination target wafer periphery neighboring chips among wafer periphery neighboring chips located within a predetermined range from the periphery of the wafer based on the distance from a corresponding one of the defective groups; and (c) determining the quality of the determination target wafer periphery neighboring chips by comparing the quality determination indexes thereof with a preset threshold.

Abstract: Alignment data from an exposure tool suitable for exposing a plurality of semiconductor wafers are provided, the alignment data including alignment values applied by the exposure tool to respective ones of the plurality of semiconductor wafers at a plurality of measured positions.

Abstract: The ohmic contact between a growth substrate and an electrode formed thereon is improved in a zinc oxide-based semiconductor light-emitting device, thereby improving the light-emission efficiency and reliability A step for forming an n-type semiconductor layer, a light-emitting layer, and a p-type semiconductor layer in sequence on a first principal face of a substrate having a composition of MgxZn1-xO (0?x?0.68); a step for forming microcracks in a second principal face of the substrate so as to extend toward an interior of the substrate; a step for carrying out a heat treatment at a temperature of 100° C. or higher; and a step for forming an electrode by depositing a metal material composed of one among Al, a Ga alloy, and an In alloy on the second principal face of the substrate, and forming an electrode in a heat treatment at a temperature of 300° C. to 1000° C. are provided.

Abstract: A method for manufacturing an LED (light emitting diode) includes following steps: providing a first electrode, a second electrode and a Zener diode, the Zener diode being electrically connected to the first and second electrodes; providing a mold; the first electrode, the second electrode and the Zener diode being received in the mold; injecting a liquid molding material into the mold, thereby integrally forming a base, a dam, and a reflective cup, the Zener diode being encapsulated in the dam; setting first and second LED chips respectively on the first and second electrodes; filling an encapsulation material in the reflective cup to encapsulate the first and second LED chips. The first and second LED chips are separated from each other by the dam.

Abstract: A light emitting device includes a resin molded body having a circular or an oval recessed section at the center suppresses generation of cracks. The device is provided with a light emitting element, a first resin molded body having a plurality of outer surfaces, and a recessed section at the center. First and second leads are electrically connected to the light emitting element, and a second resin molded body is applied in the recessed section. The light emitting element is placed on the first lead, and the surface of the second resin molded resin forms a light emitting surface. A gate notch is formed on an extended line of a normal line on one point on a circular cross-section of the recessed section in the normal line direction.

Abstract: A method for sealing an organic light emitting diode (OLED) device is disclosed wherein the OLED device comprises a color filter. A color filter is deposited on a first glass plate or substrate and a glass-based frit is then deposited in a loop around the color filter, The deposited fit loop is then heated by electromagnetic energy to evaporate organic constituents and to sinter the fit in a pre-sintering step. An OLED device may then be assembled by positioning a second glass plate comprising an organic light emitting material deposited thereon in overlying registration with the first glass plate, with the color filer and the organic light emitting material positioned between the plates. The fit is then heated with a laser to form a hermetic seal between the first and second glass plates.

Abstract: A nanocrystal electroluminescence device comprising a polymer hole transport layer, a nanocrystal light-emitting layer and an organic electron transport layer wherein the nanocrystal light-emitting layer is independently and separately formed between the polymer hole transport layer and the organic electron transport layer. According to the nanocrystal electroluminescence device, since the hole transport layer, the nanocrystal light-emitting layer and the electron transport layer are completely separated from one another, the electroluminescence device provides a pure nanocrystal luminescence spectrum having limited luminescence from other organic layers and substantially no influence by operational conditions, such as voltage. Further included is a method for fabricating the nanocrystal electroluminescence device.

Abstract: Manufacturing method of an electronic component including connecting one lead of a pair of leads to a surface parallel with a pn connection layer of an electronic element having a structure where the p-type layer and the n-type layer are connected by the pn connection layer provided between the p-type layer and the n-type layer, connecting another lead to another surface parallel with the pn connection layer; and forming a supporting part of the pair of the leads that is connected to and supporting the electronic element, and an electrode part functioning as an electrode, by bending the pair of the leads to an outside.

Abstract: A method for manufacturing a transflective liquid crystal display panel includes providing an array substrate having a plurality of pixel regions, each of the pixel regions includes a device region, a transmission region and a reflection region defined therein; forming a first metal layer on the array substrate; patterning the first metal layer to simultaneously form a gate electrode in the device region and a plurality of metal bumps in the reflection region; forming a first insulating layer having a rough surface and covering the gate electrode and the metal bumps on the array substrate; forming a patterned semiconductor layer on the gate electrode; forming a reflective layer covering the first insulating layer and having a rough surface in the reflection region; and sequentially forming a patterned second insulating layer and a transparent pixel electrode on the array substrate.

Abstract: A method of fabricating an array substrate including forming a first metal layer; forming a gate insulating layer and an active layer; forming a second metal layer; forming a gate line, an etch-stopper and a gate electrode by patterning the first and second metal layers; forming an interlayer insulating layer including an opening, wherein the opening corresponds to the etch-stopper such that the opening is divided into first and second semiconductor contact holes respectively exposing both sides of the active layer; forming first and second ohmic contact layers, a source electrode, a drain electrode and a data line, the first and second ohmic contact layers respectively contacting both sides of the active layer through the first and second semiconductor contact holes; removing an exposed portion of the etch-stopper; and forming a pixel electrode contacting the drain electrode.

Abstract: For forming a gate electrode, a conductive film with low resistance including Al or a material containing Al as its main component and a conductive film with low contact resistance for preventing diffusion of Al into a semiconductor layer are laminated, and the gate electrode is fabricated by using an apparatus which is capable of performing etching treatment at high speed.

Abstract: A method of making a LED includes following steps. A substrate is provided, and the substrate includes an epitaxial growth surface. A carbon nanotube layer is placed on the epitaxial growth surface. A first semiconductor layer, an active layer, and a second semiconductor layer are grown in that order on the substrate. A reflector and a first electrode are deposited on the second semiconductor layer in that order. The substrate is removed. A second electrode is deposited on the first semiconductor layer.

Abstract: A method of fabricating an electrophoretic display device includes forming a gate line along a direction, a gate electrode extending from the gate line, a common line parallel to the gate line, and a first storage electrode extending from the common line on a substrate, forming a gate insulating layer on an entire surface of the substrate including the gate line, the gate electrode, the common line and the first storage electrode, forming a semiconductor layer, a data line, and source and drain electrodes through a mask process, wherein the semiconductor layer is disposed over the gate electrode, the data line crosses the gate line to define a pixel region, the source electrode extends from the data line, and the drain electrode is spaced apart from the source electrode over the semiconductor layer.

Abstract: The present disclosure provides methods for manufacturing a radio frequency (RF) powder including a plurality of RF particles, each of which includes a circuit element. A plurality of circuit elements, each corresponding to a different RF particle, may be formed on a first surface of a substrate. Grooves may be etched into the first surface of the substrate between the plurality of circuit elements. A protection film may be formed on each of the plurality of circuit elements and a portion of the substrate between a second, opposite surface of the substrate and bottoms of the grooves may be removed so that each of the plurality of circuit elements is associated with the remaining portion of the substrate.

Abstract: This present invention discloses a manufacturing method and structure for a wafer level image sensor module with fixed focal length. The method includes the following steps. First, a silicon wafer comprising several image sensor chips having a photosensitive area and a lens module array wafer comprising several wafer level lens modules with fixed focal length are provided. Next, the image sensor chips and the wafer level lens modules are sorted in grades according to the different quality grades. According to the sorting results, each of the wafer level lens modules is assigned to be situated above the image sensor chip that has the same grade. At the same time, each of the wafer level lens modules is directed to face the photosensitive area of each image sensor chip. Finally, in the packaging process, the wafer level lens module is surrounded by an encapsulation material.

Abstract: A method of manufacturing a solar cell includes providing a semiconductor substrate; disposing a reflection layer on one side of the semiconductor substrate, wherein the disposing the reflection layer comprises implanting gas into a surface of the one side of the semiconductor substrate and heating the gas; disposing an n+ region and a p+ region separated from each other on the other opposite facing side of the semiconductor substrate; disposing a first electrode connected to the n+ region; and disposing a second electrode connected to the p+ region.

Abstract: A method for manufacturing a pixel sensor cell that includes a photosensitive element having a non-laterally disposed charge collection region. The method includes forming a trench recess in a substrate of a first conductivity type material, and filling the trench recess with a material having second conductivity type material. The second conductivity type material is then diffused out of the filled trench material to the substrate region surrounding the trench to form the non-laterally disposed charge collection region. The filled trench material is removed to provide a trench recess, and the trench recess is filled with a material having a first conductivity type material. A surface implant layer is formed at either side of the trench having a first conductivity type material. A collection region of a trench-type photosensitive element is formed of the outdiffused second conductivity type material and is isolated from the substrate surface.

Abstract: An imager device is disclosed including a first substrate having an array of photosensitive elements formed thereon, a first conductive layer formed above the first substrate, a first conductive member extending through the first substrate, the first conductive member being conductively coupled to the first conductive layer, a standoff structure formed above the first substrate, a second conductive layer formed above the standoff structure, the second conductive layer being conductively coupled to the first conductive layer, and an electrically powered device positioned above the standoff structure, the electrically powered device being electrically coupled to the second conductive layer.

Abstract: A solid-state imaging apparatus and a manufacturing method of a solid-state imaging apparatus are provided. Metal wirings 102 and 103 are formed in an effective pixel region A and out-of effective pixel region B of a semiconductor substrate 100, and an etch stop layer 118 is formed over the metal wirings 102 and 103. Moreover, an insulating film 119 is formed on the etch stop layer 118, and another metal wiring 104 is formed on the insulating film 119 in the out-of effective pixel region B. Next, the insulating film 119 in the effective pixel region A is removed by using the etch stop layer 118, and interlayer lenses 105 are formed in the step in the effective pixel region A where the insulating film 119 is removed.

Abstract: Alternative additives that can be used in place of isopropyl alcohol in aqueous alkaline etchant solutions for texturing a surface of a single-crystalline silicon substrate are provided. The alternative additives do not have volatile constituents, yet can be used in an aqueous alkaline etchant solution to provide a pyramidal shaped texture surface to the single-crystalline silicon substrate that is exposed to such an etchant solution. Also provided is a method of forming a textured silicon surface. The method includes immersing a single-crystalline silicon substrate into an etchant solution to form a pyramid shaped textured surface on the single-crystalline silicon substrate. The etchant solution includes an alkaline component, silicon (etched into the solution as a bath conditioner) and glycerol or ethylene glycol as an additive. The textured surface of the single-crystalline silicon substrate has (111) faces that are now exposed.

Abstract: The present disclosure provides an image sensor semiconductor device. A semiconductor substrate having a first-type conductivity is provided. A plurality of sensor elements is formed in the semiconductor substrate. An isolation feature is formed between the plurality of sensor elements. An ion implantation process is performed to form a doped region having the first-type conductivity substantially underlying the isolation feature using at least two different implant energy.

Abstract: Conductive material grids or lines embedded or partially embedded in a transparent substrate of a solar cell. The grids or lines can have a higher conductivity than the anode or they can have the same conductivity. The grids or lines increase the volume of the anode and, thus decrease sheet resistance of the same.

Abstract: A Kesterite film is vacuum deposited and annealed on a substrate. Deposition is conducted at low temperature to provide good composition control and efficient use of metals. Annealing is conducted at a high temperature for a short period of time. Thermal evaporation, E-beam evaporation or sputtering in a high vacuum environment may be employed as part of a deposition process.

Abstract: Methods and devices are provided for forming thin-films from solid group IIIA-based particles. In one embodiment of the present invention, a method is described comprising of providing a first material comprising an alloy of a) a group IIIA-based material and b) at least one other material. The material may be included in an amount sufficient so that no liquid phase of the alloy is present within the first material in a temperature range between room temperature and a deposition or pre-deposition temperature higher than room temperature, wherein the group IIIA-based material is otherwise liquid in that temperature range. The other material may be a group IA material. A precursor material may be formulated comprising a) particles of the first material and b) particles containing at least one element from the group consisting of: group IB, IIIA, VIA element, alloys containing any of the foregoing elements, or combinations thereof.

Abstract: A back-illuminated type solid-state image pickup device (1041) includes read circuits (Tr1, Tr2) formed on one surface of a semiconductor substrate (1042) to read a signal from a photo-electric conversion element (PD) formed on the semiconductor substrate (1042), in which electric charges (e) generated in a photo-electric conversion region (1052c1) formed under at least one portion of the read circuits (Tr1, Tr2) are collected to an electric charge accumulation region (1052a) formed on one surface side of the semiconductor substrate (1042) of the photo-electric conversion element (PD) by electric field formed within the photo-electric conversion element (PD). Thus, the solid-state image pickup device and the camera are able to make the size of pixel become very small without lowering a saturation electric charge amount (Qs) and sensitivity.

Abstract: A light emitting device comprises a plurality of LED chips (“lateral” or “vertical” conducting) operable to generate light of a first wavelength range and a package for housing the chips. The package comprises: a thermally conducting substrate (copper) on which the LED chips are mounted and a cover having a plurality of through-holes in which each hole corresponds to a respective one of the LED chips. The holes are configured such that when the cover is mounted to the substrate each hole in conjunction with the substrate defines a recess in which a respective chip is housed. Each recess is at least partially filled with a mixture of at least one phosphor material and a transparent material. In a device with “lateral” conducting LED chips a PCB is mounted on the substrate and includes a plurality of through-holes which are configured such that each chip is directly mounted to the substrate. For a device with “vertical” conducting LED chips the LED chips are mounted on a diamond like carbon film.

Abstract: A memory or switching device includes a mesa and a first electrode conforming to said mesa. The device also includes a second electrode and a phase-change or switching material disposed between said first and second electrodes. The phase-change or switching material is in electrical communication with the first and second electrodes at a first contact region and a second contact region respectively. Also described is a method for making a memory or switching device. The method includes providing a first insulator and configuring the first insulator to provide a mesa. A first conductive layer is provided conforming to the mesa. A phase-change or switching material is provided over a portion of the first conductive layer, and a second conductive layer is provided over the phase-change or switching material.

Abstract: An object is to suppress deterioration of element characteristics even when an oxide semiconductor is formed after a gate insulating layer, a source electrode layer, and a drain electrode layer are formed. A gate electrode layer is formed over a substrate. A gate insulating layer is formed over the gate electrode layer. A source electrode layer and a drain electrode layer are formed over the gate insulating layer. Surface treatment is performed on surfaces of the gate insulating layer, the source electrode layer, and the drain electrode layer which are formed over the substrate. After the surface treatment is performed, an oxide semiconductor layer is formed over the gate insulating layer, the source electrode layer, and the drain electrode layer.

Abstract: A method includes placing a cover over a lower package component, wherein the cover comprises an opening aligned to the lower package component. An upper package component is placed over the lower package component. The upper package component is aligned to the opening, and a solder region is dispose between the upper package component and the lower package component. The cover and the upper package component are exposed to a radiation to reflow the solder region.

Abstract: The present invention is related to a method for aligning and bonding a first element (1) and a second element (2), comprising: obtaining a first element (1) having at least one protrusion, the protrusion having a base portion (12) made of a first material and an upper portion (13) made of a second, deformable material, different from the first material; obtaining a second element (2) having a first main surface and second main surface (8) and at least one through-hole between the first and second main surface; placing the first and second element onto each other; receiving in the through-hole of the second element (2) the protrusion of the first element (1), the protrusion being arranged and constructed so as to extend from an opening of the through-hole in the first main surface to a position beyond an opening of the through-hole in the second main surface (8); deforming the deformable portion (13) of the protrusion, such that the deformed portion mechanically fixes the second element (2) on the first el

Abstract: An integrated circuit including an active region a passive region and a cut line in the passive region includes a passivation layer that includes an outer nitride layer over an oxide layer. The integrated circuit also includes a crack stop below the passivation layer and in the passive region, and a solder ball in the active region. The passivation layer has a trench formed therein in a location that is further from the active region than the crack stop and closer to the active region than the cut line, the trench passing completely through the outer nitride layer and a least a portion of the way through the oxide layer.

Abstract: A microelectronic package includes first substrate (120) having first surface area (125) and second substrate (130) having second surface area (135). The first substrate includes first set of interconnects (126) having first pitch (127) at first surface (121) and second set of interconnects (128) having second pitch (129) at second surface (222). The second substrate is coupled to the first substrate using the second set of interconnects and includes third set of interconnects (236) having third pitch (237) and internal electrically conductive layers (233, 234) connected to each other with microvia (240). The first pitch is smaller than the second pitch, the second pitch is smaller than the third pitch, and the first surface area is smaller than the second surface area.

Abstract: A packaged electronic component and method of forming. The packaged electronic component is formed with a lead frame. The lead frame includes at least one silver structure. The silver structure attracts sulfur so as to inhibit sulfur contamination on the rest of the lead frame. In one example, the silver of the at least one silver structure has an average grain size thickness of one micron or less. In one embodiment, a sulfur removal process can be performed to remove sulfur from the silver structure.

Abstract: An integrated circuit containing a FeCap array. The FeCap array is at least partially surrounded on the sides by hydrogen barrier walls and on the top by a hydrogen barrier top plate. A method for at least partially enclosing a FeCap array with hydrogen barrier walls and a hydrogen barrier top plate.

Abstract: A semiconductor device and a process for producing the same, the semiconductor device comprising two conductive layers provided as separate layers, and an insulating layer sandwiched by the two conductive layers, in which the two conductive layers are electrically connected to each other with an embedded conductive layer or an oxide conductive layer provided as filling an opening formed in the insulating layer, and the embedded conductive layer comprises an organic resin film containing a conductive material dispersed therein or an inorganic film containing a conductive material dispersed therein.

Abstract: The method for manufacturing the semiconductor device is as follows: forming a gate electrode; forming a first insulating film over the gate electrode; performing halogen doping treatment on the first insulating film so that the first insulating film is supplied with a halogen atom; forming an oxide semiconductor film over the first insulating film so as to overlap with the gate electrode; performing heat treatment on the oxide semiconductor film so that a hydrogen atom is removed in the oxide semiconductor film; performing oxygen doping treatment on the oxide semiconductor film from which the hydrogen atom is removed so that the oxide semiconductor film is supplied with an oxygen atom; performing heat treatment on the oxide semiconductor film to which the oxygen atom is supplied; forming a source electrode and a drain electrode on and in contact with the oxide semiconductor film; forming a second insulating film.

Abstract: A method for manufacturing multi-gate transistor device includes providing a semiconductor substrate having a patterned semiconductor layer and a patterned hard mask sequentially formed thereon, removing the patterned hard mask, performing a thermal treatment to rounding the patterned semiconductor layer with a process temperature lower than 800° C., and sequentially forming a gate dielectric layer and a gate layer covering a portion of the patterned semiconductor layer on the semiconductor substrate.

Abstract: The present inventions are related to systems and methods for pre-equalizer noise suppression in a data processing system. As an example, a data processing system is discussed that includes: a sample averaging circuit, a selector circuit, an equalizer circuit, and a mark detector circuit. The sample averaging circuit is operable to average corresponding data samples from at least a first read of a codeword and a second read of the codeword to yield an averaged output based at least in part on a framing signal. The selector circuit is operable to select one of the averaged output and the first read of the codeword as a selected output. The equalizer circuit is operable to equalize the selected output to yield an equalized output, and the mark detector circuit is operable to identify a location mark in the equalized output to yield the framing signal.

Abstract: In a semiconductor that has a structure in which a work function controlling metal conductor is provided on a high dielectric insulation film, fine processing is performed without deteriorating a device. In a method of semiconductor processing, in which the semiconductor has an insulation film containing Hf or Zr formed on a semiconductor substrate and a conductor film containing Ti or Ta or Ru formed on an insulation film, and the conductor film is processed by using a resist formed on the conductor film under a plasma atmosphere, the resist is removed under the plasma atmosphere of gas that contains hydrogen and does not contain oxygen.

Abstract: A method for manufacturing a semiconductor device is provided. A gate structure is formed on a substrate. A first dopant implantation and a first strain atom implantation are performed. Thereafter, spacers are formed on sidewalls of the gate structure. A second dopant implantation and a second strain atom implantation are performed. A solid-phase epitaxy annealing process is performed to form source and drain regions made of a semiconductor compound solid-phase epitaxial layer beside the gate structure.

Abstract: In one implementation, a method of forming a field effect transistor includes etching an opening into source/drain area of a semiconductor substrate. The opening has a base comprising semiconductive material. After the etching, insulative material is formed within the opening over the semiconductive material base. The insulative material less than completely fills the opening and has a substantially uniform thickness across the opening. Semiconductive source/drain material is formed within the opening over the insulative material within the opening. A transistor gate is provided operatively proximate the semiconductive source/drain material. Other aspects and implementations are contemplated.

Abstract: A method of forming a field effect transistor comprises providing a substrate comprising a biaxially strained layer of a semiconductor material. A gate electrode is formed on the biaxially strained layer of semiconductor material. A raised source region and a raised drain region are formed adjacent the gate electrode. Ions of a dopant material are implanted into the raised source region and the raised drain region to form an extended source region and an extended drain region. Moreover, in methods of forming a field effect transistor according to embodiments of the present invention, a gate electrode can be formed in a recess of a layer of semiconductor material. Thus, a field effect transistor wherein a source side channel contact region and a drain side channel contact region located adjacent a channel region are subject to biaxial strain can be obtained.

Abstract: The disclosure relates to a fin field effect transistor (FinFET). An exemplary structure for a FinFET comprises a substrate comprising a top surface; a first insulation region and a second insulation region over the substrate top surface comprising tapered top surfaces; a fin of the substrate extending above the substrate top surface between the first and second insulation regions, wherein the fin comprises a recessed portion having a top surface lower than the tapered top surfaces of the first and second insulation regions, wherein the fin comprises a non-recessed portion having a top surface higher than the tapered top surfaces; and a gate stack over the non-recessed portion of the fin.