Abstract: The invention relates to a method for making a stack of memory circuits, wherein the method includes the step of testing the validity of at least two memory circuits. According to the invention, the method includes the phase of configuring each memory circuit, the configuration phase including the step of writing, within a configuration device of each memory circuit included in the stack, a piece of information on an identifier allocated to the memory circuit in the stack, and a piece of information on the results of the validity test of the memory circuit. The invention also relates to a method for addressing a memory circuit, to a stack of memory circuits, and to an electronic device including such a stack.

Abstract: A semiconductor integrated circuit includes a first semiconductor chip including a first output circuit which is enabled in a first operation mode and outputs a first output signal and a second output circuit which is enabled in a second operation mode and outputs a second output signal; a second semiconductor chip including a first input circuit which is enabled in the first operation mode and receives the first output signal and a second input circuit which is enabled in the second operation mode and receives the second output signal; and a common through chip via arranged to vertically penetrate through the semiconductor chip, be coupled with the first and second output circuits in one end and coupled with the first and second input circuits in the other end, and interface transfer of the first and second output signals which are enabled in different operation modes, including the first and second operation modes.

Abstract: For example, to include plural data input/output terminals and a strobe terminal that are electrically connected in common by a test probe, a command address terminal that is connected to a test probe, and an output control circuit that performs a selecting operation of data output circuits based on a signal that is supplied to the command address terminal. According to the present invention, it is possible to perform a test that uses non-compressed actual data while allocating plural data input/output terminals to one determination circuit within a tester. With this configuration, it is possible to test a large number of semiconductor devices in parallel by using a limited number of determination circuits within the tester.

Abstract: Non-volatile latch circuits, such as in memory cells and flip-flops, that are constructed for reliability screening. The non-volatile latch circuits each include ferroelectric capacitors coupled to storage nodes, for example at the outputs of cross-coupled inverters. Separate plate lines are connected to the ferroelectric capacitors of the complementary storage nodes. A time-zero test of the latch stability margin is performed by setting a logic state at the storage nodes, then programming the state into the ferroelectric capacitors by polarization. After power-down, the plate lines are biased with a differential voltage relative to one another, and the latch is then powered up to attempt recall of the programmed state. The differential voltage disturbs the recall, and provides a measure of the cell margin and its later-life reliability.

Abstract: A system for determining the logic state of a resistive memory cell element, for example an MRAM resistive cell element. The system includes a controlled voltage supply, an electronic charge reservoir, a current source, and a pulse counter. The controlled voltage supply is connected to the resistive memory cell element to maintain a constant voltage across the resistive element. The charge reservoir is connected to the voltage supply to provide a current through the resistive element. The current source is connected to the charge reservoir to repeatedly supply a pulse of current to recharge the reservoir upon depletion of electronic charge from the reservoir, and the pulse counter provides a count of the number of pulses supplied by the current source over a predetermined time. The count represents a logic state of the memory cell element.

Abstract: A memory device has a crossbar array including a first array of first electrodes extending along a first direction. A second array of second electrodes extends along a second direction. A non-crystalline silicon structure provided between the first electrode and the second electrode at an intersection defined by the first array and the second array. The non-crystalline silicon structure has a first layer having a first defect density and a second layer having a second defect density different from the first defect density. Each intersection of the first array and the second array defines a two-terminal memory cell.

Abstract: An addressing scheme for non-volatile memory arrays having short circuit defects that manages the demand for error correction. The scheme generally avoids simultaneous active driving of the row line and column line of the selected cell during write. Instead, only a single row or column line is actively driven at any one time and all other array lines are left floating. In addition, the number of memory cells accessed from a given row or column during a fetch may be limited. The benefits of the scheme include preventing short circuits from drawing excess currents through the array and limiting the frequency of read or write failures caused by short circuits to a manageable number. In one embodiment, the scheme maintains the demand for error correction to within the error correction capability of a flash controller. Exemplary embodiments include phase-change memory arrays.

Abstract: A nonvolatile resistance variable memory device (100) includes memory cells (M11, M12, . . . ) in each of which a variable resistance element (R11, R12, . . . ) including a variable resistance layer placed between and in contact with a first electrode and a second electrode, and a current steering element (D11, D12, . . . ) including a current steering layer placed between and in contact with a third electrode and a fourth electrode, are connected in series, and the device is driven by a first LR drive circuit (105a1) via a current limit circuit (105b) to decrease resistance of the variable resistance element while the device is driven by a second HR drive circuit (105a2) to increase resistance of the variable resistance element, thus using the current limit circuit (105b) to make a current for decreasing resistance of the variable resistance element lower than a current for increasing resistance of the variable resistance element.

Abstract: Nonvolatile memory elements are provided comprising switching metal oxides. The nonvolatile memory elements may be formed in one or more layers on an integrated circuit. Each memory element may have a first conductive layer, a metal oxide layer, and a second conductive layer. Electrical devices may be coupled in series with the memory elements. The first conductive layer may be formed from a metal nitride. The metal oxide layer may contain the same metal as the first conductive layer. The metal oxide may form an ohmic contact or a Schottky contact with the first conductive layer. The second conductive layer may form an ohmic contact or a Schottky contact with the metal oxide layer. The first conductive layer, the metal oxide layer, and the second conductive layer may include sublayers. The second conductive layer may include an adhesion or barrier layer and a workfunction control layer.

Abstract: A cross point variable resistance nonvolatile memory device includes memory cells having the same orientation for stable characteristics of all layers. Each memory cell (51) is placed at a different one of cross points of bit lines (53) in an X direction and word lines (52) in a Y direction formed in layers. In a multilayer cross point structure where vertical array planes sharing the word lines are aligned in the Y direction each for a group of bit lines aligned in a Z direction, even and odd layer bit line selection switch elements (57, 58) switch electrical connection and disconnection between a global bit line (56) and commonly-connected even layer bit lines and commonly-connected odd layer bit lines, respectively. A bidirectional current limiting circuit (92) having parallel-connected P-type current limiting element (91) and N-type current limiting element (90) is provided between the global bit line and the switch elements.

Abstract: A semiconductor device comprises a memory cell including a capacitor and a select transistor with a floating body structure, a bit line connected to the select transistor, a bit line control circuit, and a sense amplifier amplifying a signal read out from the memory cell. The bit line control circuit sets the bit line to a first potential during a non-access period of the memory cell, and thereafter sets the bit line to a second potential during an access period of the memory cell. Thereby, the data retention time can be prolonged by reducing leak current at a data storage node of the memory cell so that an average consumption current for the data retention can be reduced.

Abstract: An object is to provide a semiconductor device with a novel structure, which can hold stored data even when not powered and which has an unlimited number of write cycles. A semiconductor device includes a memory cell including a widegap semiconductor, for example, an oxide semiconductor and the semiconductor device includes a potential conversion circuit which functions to output a potential lower than a reference potential for reading data from the memory cell. With the use of a widegap semiconductor, a semiconductor device capable of sufficiently reducing the off-state current of a transistor included in a memory cell and capable of holding data for a long time can be provided.

Abstract: A memory device includes a memory array comprising a plurality of memory cells. At least a given one of the memory cells comprises a pair of cross-coupled inverters and associated write assist circuitry. The write assist circuitry comprises first switching circuitry coupled between a supply node of a device of the first inverter and a supply node of the memory cell, and second switching circuitry coupled between a supply node of a device of the second inverter and the supply node of the memory cell. The first and second switching circuitry are separately controlled such that during a write operation of the memory cell the supply node of one of the devices is connected to the supply node of the memory cell while the supply node of the other device is not connected to the supply node of the memory cell but is instead permitted to float.

Abstract: The invention provides a semiconductor integrated circuit device provided with an SRAM that satisfies the requirements for both the SNM and the write margin with a low supply voltage. The semiconductor integrated circuit device include: multiple static memory cells provided in correspondence with multiple word lines and multiple complimentary bit lines; multiple memory cell power supply lines that each supply an operational voltage to each of the multiple memory cells connected to the multiple complimentary bit lines each; multiple power supply circuits comprised of resistive units that each supply a power supply voltage to the memory cell power supply lines each; and a pre-charge circuit that supplies a pre-charge voltage corresponding to the power supply voltage to the complimentary bit lines, wherein the memory cell power supply lines are made to have coupling capacitances to thereby transmit a write signal on corresponding complimentary bit lines.

Abstract: A method of writing in a memory device comprising a plurality of MRAM cells, each cell including a magnetic tunnel junction having a resistance that can be varied during a write operation when heated at a high threshold temperature; a plurality of word lines connecting cells along a row; and a plurality of bit lines connecting cells along a column; the method comprising supplying a bit line voltage to one of the bit lines and a word line voltage to one of the word lines for passing a heating current through the magnetic tunnel junction of a selected cell; said word line voltage is a word line overdrive voltage being higher than the core operating voltage of the cells such that the heating current has a magnitude that is high enough for heating the magnetic tunnel junction at the predetermined high threshold temperature. The memory device can be written with low power consumption.

Abstract: A semiconductor memory device substantially prevents a faulty operation from being generated in a read operation, and increases the operation reliability. The semiconductor memory device includes a cell array configured to include a memory element having a different resistance value in response to data, a sense-amp configured to sense and amplify the data, a global bit line configured to couple the sense-amp to a cell array, and a discharge unit configured to discharge the global bit line prior to execution of a read operation.

Abstract: A semiconductor memory device includes a memory cell array configured to include a plurality of memory cells, a plurality of bit lines respectively coupled to the plurality of memory cells, a first power-supply voltage supplying circuit configured to provide a first power-supply voltage to the memory cell array through the plurality of bit lines, a second power-supply voltage supplying circuit configured to provide a second power-supply voltage to the memory cell array through the plurality of bit lines, a first address selection circuit configured to couple a bit line selected by a first selection address to the first power-supply voltage supplying circuit, and a second address selection circuit configured to couple a bit line selected by a second selection address to the second power-supply voltage supplying circuit.

Abstract: A method and a feedback controller for programming at least one multi-level phase-change memory cell with a programming signal. The method and feedback controller include a sequence of write pulses applied to the multi-level phase change memory cell, wherein the feedback controller adjusts in real time at least one parameter of each write pulse as a function of a determined resistance error of the phase-change memory cell with respect to a desired reference resistance level.

Abstract: A memory device and method for programming the memory device, more particularly a single pulse algorithm for programming a phase change memory cell or array. The single pulse can heat the memory cell to above its melting point and reduce in signal level so that the memory cell is crystallized.

Abstract: The present invention provides methods and apparatus for adjusting voltages of bit and word lines to program a two terminal memory cell. The invention may include setting a first line connected to a memory cell to a first voltage from a first line standby voltage, charging a second line connected to the memory cell to a predetermined voltage from a second line standby voltage, and switching the first line from the first voltage to a second voltage. The voltage difference between the first voltage and the predetermined voltage is such that a safe voltage results that does not program the memory cell. A voltage difference between the second voltage and the predetermined voltage is such that a programming voltage operative to program the memory cell results.

Abstract: A large scale memory array includes a uniform pattern of uniformly sized dummy bit cells and active bit cells. Sub-arrays within the large scale memory array are separated by the dummy bit cells. Signal distribution circuitry is formed with a width or height corresponding to the width or height of the dummy bit cells so that the signal distribution circuitry occupies the same footprint as the dummy bit cells without disrupting the uniform pattern across the large scale array. Edge dummy cells of a similar size or larger than the standard size bit cells may be placed around the edge of the large scale array to further reduce pattern loading affects.

Abstract: The present invention provides a semiconductor storage circuit that may suppress a data read characteristic from being deteriorated due to influence of characteristic change of a sense amplifier, in a multi-bit-type memory cell. The semiconductor storage circuit includes a memory cell array that has plural multi-bit-type memory cells, two multiplexers, and two sense amplifiers. The first multiplexer connects a main bit line connected to an R-side electrode of the even-numbered memory cell in a row direction to the first sense amplifier, and connects a main bit line connected to an L-side electrode of the odd-numbered memory cell to the second sense amplifier. The second multiplexer connects a main bit line connected to an L-side electrode of the even-numbered memory cell to the first sense amplifier, and connects a main bit line connected to an R-side electrode of the odd-numbered memory cell to the second sense amplifier.

Abstract: A stacked semiconductor memory device comprises a semiconductor substrate having a functional circuit, a plurality of memory cell array layers, and at least one connection layer. The memory cell array layers are stacked above the semiconductor substrate. The connection layers are stacked above the semiconductor substrate independent of the memory cell array layers. The connection layers electrically connect memory cell selecting lines arranged on the memory cell array layers to the functional circuit.

Abstract: In a NAND non-volatile memory system, a sensing process accounts for a relative position of a selected non-volatile storage element in a NAND string. In one approach, the storage elements are assigned to groups based on their position, and each group receives a common sensing adjustment during a verify or read process. A group which is closest to a source side of the NAND string may be the largest of all the groups, having at least twice as many storage elements as the other groups. The adjusting can include adjusting a sensing parameter such as body bias, source voltage, sensing time or sensing pre-charge level, based on the position of the sensed storage element or its associated word line position. The adjusting of the sensing may also be based on the control gate voltage and the associated data state involved in a specific sensing operation.

Abstract: Various exemplary embodiments of a nonvolatile memory apparatus are disclosed. In one exemplary embodiment, the memory apparatus may include: a page buffer; an even bit line connected to the page buffer; an odd bit line connected to the page buffer; an even memory cell string installed on the even bit line; an odd memory cell string installed on the odd bit line; and a bit line select unit configured to selectively generate a signal read path between the even bit line and the even memory cell string or between the odd bit line and the odd memory cell string.

Abstract: Strings of memory cells having a string select gate configured to selectively couple ends of a string to a data line and a source line concurrently, memory devices incorporating such strings and methods for accessing and forming such strings are provided. For example, non-volatile memory devices are disclosed that utilize vertical structure NAND strings of serially-connected non-volatile memory cells. One such string including two or more serially-connected non-volatile memory cells where each end of the string shares a string select gate with the other end of the string is disclosed.

Abstract: A method of providing an operating voltage in a memory device includes applying a read voltage to a selected word line while applying a first pass voltage to at least one unselected word line among word lines adjacent to the selected word line; and while applying a second pass voltage to the remaining unselected word lines (other than the at least one unselected word line to which the first pass voltage is applied). The level of the first pass voltage is higher than the level of the second pass voltage. The level of the first pass voltage may be set based on the level of the read voltage.

Abstract: A nonvolatile memory device is provided which includes a plurality of memory blocks, a bias block and a control logic block. The memory blocks are formed in wells, respectively. The bias block biases a well of a selected memory block. The control logic block controls the bias block to pre-charge doping regions of the selected memory block to a junction voltage before word line voltages are applied to the selected memory block in a programming operation.

Abstract: Apparatus having a string of memory cells are useful in semiconductor memory. Some apparatus have circuitry configured to program memory cells of the string in a particular sequence. Some apparatus have circuitry configured to program a threshold voltage of a selected memory cell in the string to match a target voltage compensating, at least in part, for a voltage drop across any unselected memory cells in the string on a source side of the selected memory cell during a sensing operation. Some apparatus have circuitry configured to maintain a resistance presented by source-side unselected memory cells of the string the same between a program verify operation and a later read operation.

Abstract: A flash memory device includes a memory cell array made up of memory cells arranged in rows and columns. A first page of data is programmed in selected memory cells of the memory cell array, and a second page of data is subsequently programmed in the selected memory cells. The first page of data is programmed using a program voltage having a first start value, and the second page of data is programmed using a program voltage having a second start value determined by a programming characteristic of the selected memory cells.

Abstract: Methods and memories having switching points for changing Vstep increments according to a level of a multilevel cell being programmed include programming at a smaller Vstep increment in narrow threshold voltage situations and programming at a larger Vstep increment where faster programming is desired.

Abstract: Apparatus and methods determine a program verify (PV) induced reading parameter distribution. A measured post-PV reading parameter distribution can be compared with an expected post-PV reading parameter distribution. For example, de-convolution can be applied to identify the PV induced reading parameter distribution. Based on the PV-induced reading parameter distribution, adjustments can be made to one or more parameters of the PV process.

Abstract: Provided is a program method of a multi-bit memory device with memory cells arranged in rows and columns. The program method includes a programming each memory cell of the first group of memory cells to a state within a first group of states according to a verify voltage level of a first group of verify voltage levels within a first range of levels, and programming each memory cell of the second group of memory cells to a state within a second group of states according to a verify voltage level of a second group of verify voltage levels within a second range of levels. The lowest verify voltage level in the second range of levels is higher than the highest verify voltage level in the first range of levels.

Abstract: An electrically programmable non-volatile memory device includes a plurality of memory cells, a plurality of lines for selectively biasing the memory cells, reconnection circuitry for reconnecting a pair of selected lines having different voltages, and a controller for controlling the memory device. The reconnection means includes a discharge circuit for discharging one of the selected lines being at the higher voltage in absolute value, an equalization circuit for equalizing the selected lines, a comparator circuit for measuring an indication of a voltage difference between the selected lines, and an evaluation circuit responsive to an enabling signal from the controller for activating the discharge circuit until an absolute value of the voltage difference exceeds a threshold value and for disabling the discharge circuit and enabling the equalization circuit when the absolute value of the voltage difference reaches the threshold value.

Abstract: A self refresh circuit includes a continuous output interrupting unit and a glitch removing unit. The continuous output interrupting unit is configured to receive a delay self refresh signal, transmit a pulse of an internal active signal as a first output active signal and interrupt the transmission of the pulse of the internal active signal during a first time period. The glitch removing unit is configured to generate and output a second output active signal when the first output active signal has a predetermined pulse width.

Abstract: An electrically programmable non-volatile memory device being integrated on a chip of semiconductor material is proposed.

Abstract: The invention provides methods for programming a floating gate. A floating gate tunneling device is used with an analog comparing device in a circuit having a floating reference node and an offset-mitigating feedback loop for iteratively programming a floating gate, or multiple floating gates.

Abstract: A circuit for generating a pumping voltage in a semiconductor memory apparatus includes a control signal generation block configured to generate a first control signal obtained by level-shifting a voltage level of a test signal to a first driving voltage level, a voltage application section configured to supply an external voltage to a first node in response to a first transmission signal, a first charge pump configured to raise a voltage level of the first node by a first predetermined level in response to an oscillator signal, and a first pumping voltage output section configured to select at least one of a first connection unit and a second connection unit in response to the first control signal, and to interconnect the first node with a second node using the selected connection unit when a second transmission signal is enabled, wherein a first pumping voltage is output through the second node.

Abstract: The semiconductor device includes the read circuit which reads data written to a memory cell. The read circuit includes a first transistor, a second transistor, a first switch, and a second switch. A first terminal of the first transistor is electrically connected to a gate of the first transistor, and a second terminal of the first transistor is electrically connected to an output from the read circuit via the first switch. A first terminal of the second transistor is electrically connected to a gate of the second transistor, and a second terminal of the second transistor is electrically connected to the output from the read circuit via the second switch. A channel formation region of the first transistor can be formed using an oxide semiconductor, and a channel formation region of the second transistor can be formed using silicon.

Abstract: Some embodiments of the present invention provide data storage systems including a plurality of memories and a control circuit coupled to the plurality of memories by a common channel. The control circuit is configured to sequentially transfer respective units of data to respective memories within each of a plurality of predetermined groups of the plurality of memories over the common channel and to transition from transferring units of data to a first one of the groups to transferring units of data to a second one of the groups based on an attribute of the units of data. The attribute may be related to a programming time associated with a unit of data. For example, the attribute may include a bit significance of the unit of data.

Abstract: A data strobe signal output driver includes a trigger block, a predriver block, and a main driver block. The trigger block is configured to receive a first signal, a second signal, a first clock and a second clock, and to output a predrive signal based thereon. The predriver block is configured to receive the predrive signal, a driver off signal and a termination enable signal, and to output a first main drive signal and a second main drive signal based thereon. The main driver block is configured to output a data strobe signal based on the first and second main drive signals.

Abstract: A circuit for a semiconductor memory device includes: a filtering control signal generation unit configured to synchronize a seed signal activated in a pre-amble period of a data strobe signal with the data strobe signal and sequentially generate a plurality of filtering control signals in response to the seed signal; and a filtering signal output unit configured to generate a filtering signal for filtering the data strobe signal in response to the plurality of filtering control signals and a plurality of burst length (BL) control signals.

Abstract: A method of operation in a memory controller comprising generating a mode control signal to specify at least one of a first and second mode is disclosed. In the first mode, the memory controller is configured to operate by issuing a memory access command to initiate a first data transfer between the memory controller and a first memory device, and generating a strobe signal to accompany data associated with the first data transfer. In the second mode, the controller is configured to operate by issuing a memory access command to initiate a second data transfer between the memory controller and at least first and second memory devices involving a full width that includes data widths of both the first and second memory devices, and issuing first and second strobe signals that accompany respective data transfers associated with each of the data widths of the first and second memory devices.

Abstract: Methods and apparatus for synchronizing a delay locked loop, such as delay locked loops used with NAND memories are disclosed. In at least one embodiment, one or both of a clock and the delay locked loop are stopped for energy savings. A synchronization start signal can be provided by the NAND memory or a controller to start the clock and/or delay locked loop, and to synchronize the delay locked loop to the clock before competing the read operation.

Abstract: A memory circuit includes a memory cell configured to be re-writable. A write enable circuit is configured to enable writing a signal via a pair of bit lines to the memory cell depending on a write signal. A charge supply circuit is configured to supply a charge to at least one of the pair of bit lines. A charge supply controller is configured to control the charge supply circuit to disable the supply of charge and couple the write enable circuit to at least one of the pair of bit lines after a first determined period following the reception of the write signal.

Abstract: A mat compress circuit includes a pre-control signal generator that generates a first pre-control signal and a second pre-control signal alternatively activated in response to an up/down bank selection address in a mat compression test, and a control signal transmitter that inverts and transfers the first and second pre-control signals in response to a switching signal activated when there is an input of a block selection address in the mat compression test.

Abstract: A memory module including a plurality of ranks. Each of the ranks includes a parallel test apparatus for simultaneous testing and a parallel test control unit. In response to a parallel test mode control signal, the parallel test apparatus generates first parity data for write data including a plurality of bits and generating first data obtained by replacing a bit value of at least one bit of the plurality of bits of the write data with the first parity data during a write operation, and generates second parity data for the first data and transmitting the second parity data as read data during a read operation. The parallel test control unit controls the write operation and the read operation in a parallel test mode by generating the parallel test mode control signal. Combinations of read data from the plurality of ranks correspond to different bits of the write data.

Abstract: A semiconductor memory device includes a memory cell array including a first memory cell coupled to a first bit line and a word line, and a second memory cell coupled to a second bit line and the word line and disposed adjacent to the first memory cell. A controller circuit is configured to provide first and second precharge voltages to the first and second bitlines, respectively. The first precharge voltage is provided as a positive power supply voltage and the second precharge voltage is provided as a negative stress voltage during a burn-in test operation. Related methods of operation are also discussed.

Abstract: A dynamic random access memory (DRAM) having pairs of bitlines, each pair being connected to a first bit line sense amplifier, wordlines crossing the bitlines pairs forming an array, charge storage cells connected to the bitlines, each having an enable input connected to a wordline, the bit line sense amplifiers being connected in a two dimensional array, pairs of primary databuses being connected through first access transistors to plural corresponding bit line sense amplifiers in each row of the array, apparatus for enabling columns of the first access transistors, databus sense amplifiers each connected to a corresponding data bus pair, a secondary databus, the secondary databus being connected through second access transistors to the databus sense amplifiers, and apparatus for enabling the second access transistors.

Abstract: To provide a plurality of memory banks, each of which is divided into a plurality of segments; a bank address register that designates a memory bank that becomes a refresh target; a segment address register that designates a segment that becomes a refresh target; and a refresh control circuit that prohibits a refresh operation of the memory bank or the segment not designated by at least one of the bank address register and the segment address register. This semiconductor device is capable of designating whether to perform a refresh operation not only in a memory bank unit but also in a segment unit within the memory bank, and thus it achieves a further reduction of the power consumption.