Abstract: A light-controlling element includes an illumination unit capable of controlling an amount of emitted light, and a light guide body on which the light emitted from the illumination unit is incident. The light guide body has a function of propagating the light while totally reflecting the light inside the light guide body, and the light guide body has a function of propagating the light emitted from the illumination unit at a plurality of different propagation angles inside the light guide body. The light guide body includes a plurality of light extraction regions having a function of extracting the light to the outside. At least two of the plurality of light extraction regions have different incidence angle ranges in which the light is capable of being extracted to the outside.

Abstract: A light guide device includes a light guide body and two or more pluralities of spaced-apart slits. The slits are formed by undercuts in the light guide body. Sidewalls of the slits form facets that redirect light impinging on the facets. In some embodiments, the light guide body is attached to a light source. The light source emits light that is injected into the light guide body and the slits redirect the light out of the light guide body and towards a desired target. In some embodiments, the target is a display and a first plurality of slits directs light from the light source across the light guide body and over the face of the display. A second plurality of slits then directs light out of the light guide body and towards the display.

Abstract: A light bar assembly and a backlight module are disclosed. The light bar assembly comprise a light source, a circuit board and a connector. The circuit board comprises a first supporting portion and a bending portion which is bent from the first supporting portion, and the light source is disposed on the first supporting portion. The connector is electrically connected to the light source, and the connector is disposed on the bending portion. Accordingly, by providing the bending portion on the circuit board and disposing the connector on the bending portion in the light bar assembly and the backlight module of the present disclosure, it is unnecessary to cut a portion of the light guide plate corresponding to the connector during the assembling process. Thereby, both the risk of light leakage from the backlight module and the product cost are reduced, and reliability of the backlight module is improved.

Abstract: The present invention provides an LED light bar and a backlight module of liquid crystal display device. The LED light bar of liquid crystal display device includes: a metal core printed circuit board and an LED chip mounted on the metal core printed circuit board. The metal core printed circuit board includes a metal substrate, an insulation layer formed on the metal substrate, and a circuit formed on the insulation layer. The LED chip has leads to electrically connect with the circuit. The insulation layer forms a hollow portion corresponding to the LED chip. The LED chip is received in the hollow portion and the LED chip has an undersurface engaging the metal substrate. The present invention has a simple structure, is easy to manufacture, and makes an LED light bar showing improved heat dissipation performance.

Abstract: A large area light source includes a narrow space of several millimeters long arranged between adjacent ends of circuit boards of LED bars that are arranged in series in their longitudinal direction, and one end or both ends of a connecting pin is attached movable in its longitudinal direction to a coupling terminal arranged on an end of the circuit board of the LED bar, the LED bar is attached movable in its longitudinal direction to its holder. Even if deformation of distortion, bending, or strain is induced by transportation, installation, or use of the area light source, the movable LED bar as well as the connecting pin absorbs expansion and contraction stress working between the adjacent ends of the circuit boards to securely prevent such breaking of wire incurred by use of a plurality of divided LED bars.

Abstract: A linear light source module includes a mirror light guide component and a light emitting component. The mirror light guide component has a light emitting end, a surface having a mirror light reflecting layer formed thereon and a light incidence end. The light emitting component is configured for providing light to the light incidence end. The mirror light guide component is a light guide bar and is configured for converting the light from the first light emitting component into a linear light when the light emitting component is lighted, and the mirror light guide component is a mirror bar and is configured for providing a mirror function when the light emitting component is closed. An optical touch device with the linear light source module can avoid a blind zone and can be used as a dual-touch device or a multi-touch device.

Abstract: The present invention provides a slim bezel backlight module of liquid crystal display device, which includes: a bezel, a back panel, a connection member, and a plastic frame arranged on the back panel. The bezel includes a front plate that forms a displaying opening and a side plate extending downward from an end of the front plate. The back panel includes a bottom board that is opposite to the front plate. The front plate of the bezel is recessed to form a first extruded threaded hole having internal threading. The bottom board of the back panel forms a bore corresponding to the first extruded threaded hole. The plastic frame forms a through hole corresponding to the bore. The connection member extends through the through hole and has two ends respectively mating and connecting the first extruded threaded hole of the front plate of the bezel and the bore of the bottom board of the back panel to thereby fix the bezel to the back panel.

Abstract: A switching mode power supply apparatus is provided. The switching mode power supply apparatus may include a switch unit configured to switch an input voltage to a transformer and a controller configured to select an operation mode having a switching frequency according to a size of a load applied to a secondary side of the transformer and control a switching operation of the switch unit. The switching mode power supply apparatus may include a transformer. A refrigerator having the switching mode power supply apparatus is also provided.

Abstract: An isolated switched mode power supply, SMPS, comprises a switching controller operable to generate start-up switching control signals during start-up of the isolated SMPS, and operational switching control signals of period T during subsequent operation of the isolated SMPS. The SMPS further comprises a transformer having a primary winding and a full-bridge drive circuit arranged to drive the primary winding of the transformer in response to the switching control signals. The full-bridge drive circuit has: a first switching element and a boot-strap driving circuit arranged to switch the first switching element in response to the switching control signals, the boot-strap driving circuit having a boot-strap capacitor. The full-bridge drive circuit further comprises a second switching element connected to the first switching element and to the boot-strap driving circuit, and arranged to conduct a current to charge the boot-strap capacitor when switched ON in response to the switching control signals.

Abstract: A switching power supply device and method for control thereof, including an input voltage generating unit, a transformer, an output voltage generating unit, a MOS transistor, an output voltage detecting unit, a switching control unit, and a power supply unit. The output voltage detecting unit detects a transformer tertiary winding voltage, compares it with a first reference value, compares the differentiated tertiary winding voltage with a second reference value, and determines the start and end of a detection period based on the two comparisons. The output voltage detecting unit also samples and holds the voltage with two sampling pulses within the detection period, selects one of the two sampled and held voltages, and outputs the selected voltage when the detection period ends.

Abstract: A flyback type switching power supply includes between P and N of a direct current output a sudden load change detector circuit, which normally has no power consumption, that detects only a transient fluctuation of a direct current output voltage, and starts the switching of a primary side semiconductor switch when there is no load or a light load, even when the semiconductor switch is in an off state, thereby enabling the detection of the direct current output voltage in a tertiary winding, and suppressing a drop in the direct current output voltage.

Abstract: A control circuit includes a feedback circuit, a drive signal generator, an unregulated dormant mode and output reset control circuit, and a counter. The feedback circuit generates an enable signal and in response, the drive signal generator regulates the output of the power converter. The unregulated dormant mode and output reset control circuit powers down the drive signal generator such that the regulation is ceased when the energy requirement at the output has fallen below a threshold. The drive signal generator is then powered up after a first period of time such that the regulation resumes. The counter then counts cycles of a clock signal for which the enable signal indicates an increase in the energy requirement at the output. The counter disables the drive signal generator when a count of the counter reaches a threshold number to discharge the output to less than a regulation output voltage value.

Abstract: A method for operating the DC-to-DC voltage regulator including plural active switches and plural inductors is disclosed. The method including the steps of: turning on the first active switch, and then turning off the first active switch when the current flowing in the first inductor is equal to zero; turning on the third active switch, and then turning off the third active switch when the current flowing in the second inductor is equal to zero; turning on the second active switch, and then turning off the second active switch when the current flowing in the first inductor is equal to zero; and turning on the fourth active switch, and then turning off the fourth active switch when the current flowing in the second inductor is equal to zero.

Abstract: A power conversion system and a DC link choke therefore are presented, in which a continuous core structure is provided with first and second legs around which four or more windings are located, with one or more shunt structures providing a magnetic flux path between intermediate portions of the first and second legs.

Abstract: The present invention relates to a method for feeding an unbalanced, three-phase current into a three-phase AC voltage system, comprising the steps of: producing a positive phase-sequence system for the current to be fed in, producing a negative phase-sequence system for the current to be fed in, superimposing the positive phase-sequence system and the negative phase-sequence system to form the current to be fed in and feeding the current composed in this manner into the three-phase AC voltage system.

Abstract: Inverters connected in parallel each include a power converter that carries out a direct current to alternating current conversion and supplies voltage to a motor, and a control unit, where one of the inverters is a master inverter and the control unit computes a voltage command value for the power converter in the one inverter, while the other inverter is a slave inverter and the power converter in the slave inverter is driven by the voltage command value, a transmission means transmits the voltage command value, and the control unit of the master inverter includes a delay device that delays the voltage command value by a transmission time needed when transmitting a computed voltage command value to the slave inverter, and provides the voltage command value delayed by the delay device to the power converter of the master inverter.

Abstract: An inverter control device includes a voltage detector, a target value calculation section, an inverter control section, an abnormality detector and a voltage clamp unit. The target value calculation section calculates target value of an alternating current output from the inverter based on a detection voltage detected by the voltage detector. The inverter control section generates a control signal for a switching element of the inverter based on the detection voltage and the target value to control the inverter. The abnormality detector detects an abnormality in the voltage detector. The voltage clamp unit holds the detection voltage for calculating the target value at a first assured voltage determined based on a lower limit area of an assured voltage range that assures an operation of the inverter and holds the detection voltage for generating the control signal at a second (higher) assured voltage upon detecting the abnormality in the voltage detector.

Abstract: A power supply circuit includes an alternating current to direct current (AC/DC) converter, an uninterruptible power supply (UPS), a protection circuit, and a power supply unit (PSU). The AC/DC converter converts AC power from the UPS to DC power and transmits the DC power to the PSU through the protection circuit. The protection circuit includes a first resistor, a first switch, a first capacitor, and a microprocessor. At the initial time when the UPS first supplies power to the UPS, the microprocessor turns off the first switch; after a preset time has elapsed, the microprocessor turns on the first switch.

Abstract: An example controller for use in a power supply includes a zero crossing detection (ZCD) circuit, a threshold detection circuit, and a punctuated switching control circuit. The ZCD circuit generates a ZCD signal that pulses each zero-crossing of an ac input voltage. The threshold detection circuit receives and compares an output of the power supply with a threshold reference. The punctuated switching control circuit generates a switching signal to control a switch to regulate the output of the power supply. The switching signal is generated to have intervals of switching and intervals of no switching, where each interval of switching begins responsive to the output of the power supply dropping below the threshold reference and each interval of no switching begins responsive to the output rising above the threshold reference. Each interval has a beginning that is synchronized with a pulse of the ZCD signal.

Abstract: A battery free off-grid solar inverter system includes an inverter and a controller. The inverter is used for converting a direct current voltage provided by a solar panel into an alternating current voltage. The inverter has an input terminal, an output terminal, and a control terminal. The input terminal is used for coupling to the solar panel for receiving the direct current voltage, and the output terminal is used for coupling to a load for coupling the alternating current voltage. The controller is coupled to the control terminal for gradually increasing the alternating current voltage to make the direct current voltage be gradually decreased when the battery free off-grid solar inverter system is turned on. The controller stops increasing the alternating current voltage when the direct current voltage is lower than a predetermined direct current voltage value.

Abstract: An electrode pattern is arranged near an output pattern, a leakage current leaked from the output pattern is detected by a leakage-current detection circuit via the electrode pattern, and a light emitting diode is driven based on a detection result of the leakage-current detection circuit, thereby notifying an operation state of an inverter.

Abstract: The object of the invention is to provide an energy management system for variable resource energy generating systems, which incorporates means for the storing of energy and the management thereof. The system permits the needs which arise in the power grid to be met, and participates in the regulation of the power grid and contributing to the stability and quality thereof.

Abstract: A semiconductor memory device according to an embodiment comprises: a plurality of memory cells arranged in a first direction and a second direction; local bit lines connected to group of the memory cells; a global bit line to be commonly connected to a plurality of the local bit lines; and switch circuits connected between the local bit lines and the global bit line. The switch circuits connect the global bit line to one of the local bit lines, the one of the local bit lines being electrically connected to the memory cells of the group located at a position specified by select information of the first direction and the second direction.

Abstract: Methods and systems for measuring the resistance of multiple memory elements are disclosed. The memory elements may be multi-bit memory and through precise measurement of resistance of the multi-bit memory elements, determination of how many and which memory elements fall into specific memory ranges can be accomplished. Furthermore, storage and/or display of this information may allow for the creation of resistance distribution histograms for modeling of one or more memory arrays.

Abstract: An object is to provide a highly integrated storage device which can operate at high speed and a driving method thereof. The storage device includes two storage portions, two precharge switches, and one sense amplifier. In each of the storage portions, storage elements are arranged in a matrix. In each of the storage elements, a node electrically connected to a source or a drain of a transistor whose off-state current is small is a memory storing portion. A page buffer circuit is unnecessary; thus, high-speed operation is possible and high integration is achieved.

Abstract: Methods and apparatus for providing single finFET and multiple finFET SRAM arrays on a single integrated circuit. A first single port SRAM array of a plurality of first bit cells is described, each first bit cell having a y pitch Y1 and an X pitch X1, the ratio of X1 to Y1 being greater than or equal to 2, each bit cell further having single fin finFET transistors to form a 6T SRAM cell and a first voltage control circuit; and a second single port SRAM array of a plurality of second bit cells, each second bit cell having a y pitch Y2 and an X pitch X2, the ratio of X2 to Y2 being greater than or equal to 3, each of the plurality of second bit cells comprising a 6T SRAM cell wherein the ratio of X2 to X1 is greater than about 1.1.

Abstract: Methods and apparatus for providing finFET SRAM cells. An SRAM cell structure is provided including a central N-well region and a first and a second P-well region on opposing sides of the central N-well region, having an area ratio of the N-well region to the P-well regions between 80-120%, the SRAM cell structure further includes at least one p-type transistor formed in the N-well region and having a gate electrode comprising a gate and a gate dielectric over a p-type transistor active area in the N-well region; and at least one n-type transistor formed in each of the first and second P-well regions and each n-type transistor having a gate electrode comprising a gate and a gate dielectric over an n-type transistor active area in the respective P-well region. Methods for operating the SRAM cell structures are disclosed.

Abstract: A memory element has a layered structure, including a memory layer that has magnetization perpendicular to a film face in which a magnetization direction is changed depending on information, and includes a Co—Fe—B magnetic layer, the magnetization direction being changed by applying a current in a lamination direction of the layered structure to record the information in the memory layer, a magnetization-fixed layer having magnetization perpendicular to a film face that becomes a base of the information stored in the memory layer, and an intermediate layer that is formed of a non-magnetic material and is provided between the memory layer and the magnetization-fixed layer, a first oxide layer and a second oxide layer.

Abstract: High density semiconductor memory devices are provided. The device may include a cell array region including a lower structure, an upper structure, and a selection structure, the selection structure being interposed between the lower and upper structures and including word lines, and a decoding circuit controlling voltages applied to the word lines. The decoding circuit may be configured to apply a first voltage to a pair of the word lines adjacent to each other and to apply a second voltage different from the first voltage to the remaining ones of the word lines, in response to word line address information input thereto.

Abstract: Provided are a magnetoresistance effect element with a stable magnetization direction perpendicular to film plane and a controlled magnetoresistance ratio, in which writing can be performed by magnetic domain wall motion, and a magnetic memory including the magnetoresistance effect element. The magnetoresistance ratio is controlled by forming a ferromagnetic layer of the magnetoresistance effect element from a ferromagnetic material including at least one type of 3d transition metal or a Heusler alloy. The magnetization direction is changed from a direction in the film plane to a direction perpendicular to the film plane by controlling the film thickness of the ferromagnetic layer on an atomic layer level.

Abstract: A variable resistive memory device includes an array of a plurality of memory cells. Each of the plurality of memory cells includes first and second electrodes, and an SbmSen material layer (where m and n are positive numbers, respectively) interposed between the first electrode and the second electrode. The SbmSen material layer includes a separation structure in which a plurality of Sb atoms are in contact with a plurality of Se atoms.

Abstract: The purpose of the present invention is to improve a rewriting transmission rate and reliability of a phase change memory. To attain the purpose, a plurality of phase change memory cells (SMC or USMC) which are provided in series between a word line (2) and a bit line (3) and have a selection element and a storage element that are parallel connected with each other are entirely set, and after that, a part of the cells corresponding to a data pattern is reset. Alternatively, the reverse of the operation is carried out.

Abstract: A semiconductor integrated circuit includes a first constant current output circuit that outputs a first constant current from a first constant current terminal to a first output terminal. The semiconductor integrated circuit includes an error current output circuit that outputs an error current from an error current terminal to the first output terminal.

Abstract: According to one embodiment, a semiconductor storage device includes a memory cell array and a controller. The memory cell array includes a first memory cell, a second memory cell, a third memory cell, and a fourth memory cell. The controller writes data having n values (n is natural numbers of 2 or more to k or less) in the second memory cell and simultaneously writes the fourth memory cell, after writing the data having the n values in the first memory cell. When reading the data from the first memory cell, the controller reads data of the first memory cell and the third memory cell which is selected simultaneously with the first memory cell and, changes a read voltage of the first memory cell based on the data read from the third memory cell.

Abstract: A control circuit provides an at least partially negative threshold voltage distribution to a memory cell, thereby erasing retained data of the memory cell, and provides multiple levels of positive threshold voltage distributions thereto, thereby programming multiple levels of data to the memory cell. The control circuit, when executing a program operation to the memory cell, executes a first program operation that provides the multiple levels of positive threshold voltage distributions to a first memory cell which is a memory cell subject to program, and executes a second program operation that provides a positive threshold voltage distribution, to a second memory cell adjacent to the first memory cell, irrespective of (regardless of) whether data to be programmed to the second memory cell is (already) present in the second memory cell or not.

Abstract: A data storage device includes a non-volatile memory device which includes a memory cell array; and a memory controller which includes a buffer memory and which controls the non-volatile memory device. The operating method of the data storage device includes storing data in the buffer memory according to an external request, and determining whether the data stored in the buffer memory is data accompanying a buffer program operation of the memory cell array. When the data stored in the buffer memory is data accompanying the buffer program operation, the method further includes determining whether a main program operation on the memory cell array is required, and when a main program operation on the memory cell array is required, determining a program pattern of the main program operation on the memory cell array. The method further includes issuing a set of commands for the main program operation on the memory cell array to the multi-bit memory device based on the determined program pattern.

Abstract: A method and system for extending the life span of a flash memory device. The flash memory device is dynamically configurable to store data in the single bit per cell (SBC) storage mode or the multiple bit per cell (MBC) mode. In the MBC storage mode, the cell can have one of multiple possible states, where each state is defined by respective threshold voltage ranges. In the SBC mode, the cell can have states with threshold voltages corresponding to states of the MBC storage mode which are non-adjacent to each other to improve reliability characteristics of the cell.

Abstract: A method of programming a nonvolatile memory device comprises pre-programming multi-bit data in a plurality of multi-level memory cells, reading the pre-programmed multi-bit data from the plurality of multi-level cells based on state group codes indicating state groups of the plurality of multi-level cells, and re-programming the read multi-bit data to the plurality of multi-level cells.

Abstract: A semiconductor memory device capable of reducing the size of a NAND flash memory device includes a latch unit configured to store a bad block address, a comparator configured to compare the bad block address with an access address so as to output a bad-block detection signal, and a bad block controller configured to sequentially output a plurality of bad block pulses corresponding to the bad-block detection signal during a predetermined period in response to a plurality of bad-block flag signals that are sequentially activated.

Abstract: A semiconductor memory apparatus comprises first and second memory blocks each comprising semiconductor elements coupled to first and second local line groups, a first switching circuit configured to couple a first global line group to the first local line group of the first memory block in response to a block selection signal, a second switching circuit configured to couple a second global line group to the second local line groups of the first and second memory blocks in response to the block selection signal, and a third switching circuit configured to couple the first global line group to the first local line group of the second memory block in response to the block selection signal.

Abstract: A page buffer circuit is coupled to a bit line of a memory array. The page buffer circuit includes a latch storing different data during different phases of a multi-phase program operation. A preparation phase is after the program phase and after the program verify phase of the present multi-phase program operation. For the preparation phase, the control circuitry causes the latch to store the preparation data indicating whether to program the memory cell in a subsequent multi-phase program operation following the present multi-phase program operation. Results of the program verify phase, and contents of the latch at a start of the present multi-phase program operation, are sufficient to determine the preparation data.

Abstract: Flash memory devices and systems are provided. One flash memory device includes an n-channel metal oxide semiconductor field-effect transistor (nMOSFET), a silicon-oxide-nitride-oxide silicon (SONOS) transistor coupled to the nMOSFET, and an isolated p-well coupled to the nMOSFET and the SONOS transistor. A flash memory system includes an array of memory devices divided into a plurality of paired sectors, a global bit line (GBL) configured to provide high voltage to each respective sector during erase and program operations coupled to each of the plurality of sectors, and a plurality of sense amplifiers coupled between a respective pair of sectors. Methods for operating a flash memory are also provided. One method includes providing high voltage, via the GBL, to the paired sectors during erase and program operations and providing low voltage, via a local bit line, to each memory device during read operations.

Abstract: A semiconductor memory apparatus including a latch unit configured to be driven in response to activation of a reset selection signal and resetting a first node and a second node; and an auxiliary driving unit configured to support a driving force of the latch unit in response to the reset selection signal and a voltage logic level of the first node or the second node, wherein the first node and the second node have substantially opposite voltage logic levels.

Abstract: A memory has a serial interface. The serial interface is programmable to either use separate dedicated input and output pads, or to use one bidirectional pad. When one bidirectional pad is used, the interface signal count is reduced by one.

Abstract: A non-volatile memory device programs memory cells in each row in a manner that minimizes the coupling of spurious signals. A control logic unit programs the cells in a row using a set of bit state assignments chosen by evaluating data that are to be written to the cells in the row. The control logic unit performs this evaluation by determining the number of cells in the row that will be programmed to each of a plurality of bit states corresponding to the write data. The control logic unit then selects a set of bit state assignments that will cause the programming level assigned to each bit state to be inversely proportional to the number of memory cells in the row that are programmed with the bit state. The selected set of bit states is then used to program the memory cells in the row.

Abstract: A semiconductor memory device includes a memory array including a plurality of memory cells, and a peripheral circuit configured to perform an erase operation by supplying a first erase voltage to selected memory cells and perform an erase verify operation by supplying an erase verify voltage to the selected memory cells, wherein the peripheral circuit is configured to increase the first erase voltage to a first level at a first rising rate for a first rising period and increase the first erase voltage to a first target level at a second rising rate lower than the first rising rate for a second rising period.

Abstract: A system and method to enable reading from non-volatile memory (NVM) devices is described. In one embodiment, the method includes setting a sensing parameter used to read data stored in a NVM device, reading from pluralities of locations of the NVM device with the sensing parameter set at the first value. The locations of the NVM device store an identical value. The method also includes verifying whether the identical value is read correctly from the locations of the NVM device. The method also includes setting the sensing parameter to a second value when the identical value is not read correctly with the sensing parameter set at the first value. The method further includes determining a third value for the sensing parameter from the identical value and setting the sensing parameter to the third value when the identical value is read correctly.

Abstract: A method and apparatus to program data into a row of a non-volatile memory array and verify, internally to the non-volatile memory array, that the data was successfully programmed. The verification includes comparing the programmed data from the row of the non-volatile memory array to data in the plurality of high voltage page latches that were used to program the row.

Abstract: The present disclosure includes methods, devices, and systems for adjusting sensing voltages in devices. One or more embodiments include memory cells, and a controller configured to perform a sense operation on the memory cells using a sensing voltage to determine a quantity of the memory cells having a threshold voltage (Vt) greater than the sensing voltage and adjust a sensing voltage used to determine a state of the memory cells based, at least partially, on the determined quantity of memory cells.

Abstract: A method and circuit for implementing column redundancy steering for memories with wordline repowering, and a design structure on which the subject circuit resides are provided. Each respective data column receives a precharge signal applied to an associated precharge function. An inverting multiplexer is provided in a precharge path after the wordline repowering having inputs coupled to the respective precharge functions before and after the wordline repowering. The inverting multiplexer passes the precharge signal from the precharge function before the wordline repowering or from the precharge function after the wordline repowering. The inverting multiplexer is controlled by the redundancy steering control signal that activates redundancy steering.