Abstract: Organometallic precursors may be utilized to form titanium silicon nitride films that act as heaters for phase change memories. By using a combination of TDMAT and TrDMASi, for example in a metal organic chemical vapor deposition chamber, a relatively high percentage of silicon may be achieved in reasonable deposition times, in some embodiments. In one embodiment, two separate bubblers may be utilized to feed the two organometallic compounds in gaseous form to the deposition chamber so that the relative proportions of the precursors can be readily controlled.

Abstract: Disclosed is a method of manufacturing a thin-film light-absorbing layer using spraying, including mixing precursor solutions comprising CuCl2, InCl3 and SeC(NH2)2 under a nitrogen atmosphere at room temperature thus preparing a mixture solution; spraying the mixture solution on a substrate and drying it, thus forming a thin film; and selenizing the thin film under a selenium atmosphere. A method of manufacturing a thin-film solar cell is also provided, which includes forming a back contact layer on a glass substrate using sputtering; forming a light-absorbing layer on the back contact layer using spraying; forming a buffer layer on the light-absorbing layer using chemical vapor deposition; forming a window layer on the buffer layer using sputtering; and forming an upper electrode layer on the window layer.

Abstract: A method of fabricating a programmable memory microelectronic device includes depositing onto a first electrode an intermediate layer of a material having a chalcogenide; depositing an ionizable metallic layer on the intermediate layer; irradiating with ultraviolet radiation the ionizable metallic layer so that metallic ions from the ionizable metallic layer diffuse into the intermediate layer to form a chalcogenide material containing metallic ions, and depositing a second electrode on the layer of chalcogenide material containing metallic ions obtained in the prior step. The second and third steps are repeated at least n times, where n is an integer greater than or equal to 1. The ionizable metallic layer deposited during the second step has a sufficiently small thickness that the metallic ions may be diffused totally during the irradiation (third) step.

Abstract: A method for synthesizing a thin film of copper, zinc, tin, and a chalcogen species (“CZTCh” or “CZTSS”) with well-controlled properties. The method includes depositing a thin film of precursor materials, e.g., approximately stoichiometric amounts of copper (Cu), zinc (Zn), tin (Sn), and a chalcogen species (Ch). The method then involves re-crystallizing and grain growth at higher temperatures, e.g., between about 725 and 925 degrees K, and annealing the precursor film at relatively lower temperatures, e.g., between 600 and 650 degrees K. The processing of the precursor film takes place in the presence of a quasi-equilibrium vapor, e.g., Sn and chalcogen species. The quasi-equilibrium vapor is used to maintain the precursor film in a quasi-equilibrium condition to reduce and even prevent decomposition of the CZTCh and is provided at a rate to balance desorption fluxes of Sn and chalcogens.

Abstract: An electrode (3i) of a radiofrequency parallel plate plasma reactor includes an electrode surface of a multitude of surfaces of metal members (28) which reside on dielectric spacing members (29), whereby the metal members (28) are mounted in an electrically floating manner. The dielectric members (29) are mounted, opposite to the metal members (28), upon a metal Rf supply body (14a).

Abstract: Provided are a method of doping carbon nanotubes, p-doped carbon nanotubes prepared using the method, and an electrode, a display device or a solar cell including the carbon nanotubes. Particularly, a method of doping carbon nanotubes having improved conductivity by reforming the carbon nanotubes using an oxidizer, doped carbon nanotubes prepared using the method, and an electrode, a display device or a solar cell including the carbon nanotubes are provided.

Abstract: It is an object of the present invention to form an organic transistor including an organic semiconductor having high crystallinity without loosing an interface between an organic semiconductor of a channel where carriers are spread out and a gate insulating layer and deteriorating a yield. A semiconductor device according to the present invention has a stacked structure of organic semiconductor layers, and at least the upper organic semiconductor layer is in a polycrystalline or a single crystalline state and the lower organic semiconductor layer is made of a material serving as a channel. Carrier mobility can be increased owing to the upper organic semiconductor layer having high crystallinity; thus, insufficient contact due to the upper organic semiconductor layer can be compensated by the lower organic semiconductor layer.

Abstract: Methods of forming a graphene material on a surface are presented. A metal material is disposed on a material substrate or material layer and is infused with carbon, for example, by exposing the metal to a carbon-containing vapor. The carbon-containing metal material is annealed to cause graphene to precipitate onto the bottom of the metal material to form a graphene layer between the metal material and the material substrate/material layer and also onto the top and/or sides of the metal material. Graphene material is removed from the top and sides of the metal material and then the metal material is removed, leaving only the graphene layer that was formed on the bottom of the metal material. In some cases graphene material that formed on one or more side of the sides of the metal material is not removed so that a vertical graphene material layer is formed.

Abstract: An organic light emitting diode display and a fabrication method thereof, the display including a substrate; a thin film transistor on the substrate; and an organic light emitting diode on the substrate, the organic light emitting diode including a pixel electrode, an organic emission layer, and a common electrode, wherein the organic emission layer includes a red (R) pixel, a green (G) pixel, and a blue (B) pixel, the pixel electrode includes a first pixel electrode, a second pixel electrode, and a third pixel electrode that respectively correspond to the red pixel, the green pixel, and the blue pixel, the first pixel electrode, the second pixel electrode, and the third pixel electrode each have different thicknesses, and the first pixel electrode, the second pixel electrode, and the third pixel electrode each include a first hydrophobic layer.

Abstract: A method of etching a programmable memory microelectronic device (10) having a substrate covered with at least one of the following layers in succession: a first electrode (2) based on a first metallic element; a layer (4) of chalcogenide doped with a second metallic element; a second electrode (5) based on a third metallic element; a diffusion barrier type electrically-conductive layer (6); and a hard mask (7); is provided. The method includes etching, using an inert gas plasma, at least the hard mask (7), the electrically-conductive layer (6), the second electrode (5) and the chalcogenide layer (4), where the etching step is carried out by cathode sputtering at a temperature strictly less than 150° C., preferably at a temperature of at most 120° C., and particularly preferably at a temperature of at most 100° C.

Abstract: A method for housing an electronic component in a device package includes providing a first substrate, wherein the electronic component is arranged in a component area on a first main surface of the first substrate, and wherein first contact pads are arranged outside of the component area, forming an open top frame structure around the component area on the first main surface of the first substrate, providing a second substrate having second contact pads, arranged symmetrically to the first contact pads and electrically and mechanically connecting the first main surface of the first substrate with the first main surface of the second substrate, so that the frame structure and the second substrate from a cavity or recess around the electronic component on the first substrate.

Abstract: A method for manufacturing an integrated circuit package system includes: connecting an integrated circuit die with a bottom connection structure; placing an adhesive encapsulation over the integrated circuit die and the bottom connection structure with the bottom connection structure exposed; and placing a top connection structure over the adhesive encapsulation at an opposing side to the bottom connection structure.

Abstract: A method of producing a slider wafer populated with electromagnetic components optically aligned with photonic elements for HAMR applications. Laser chips are transferred from a laser substrate wafer to the slider wafer by a massively parallel printing transfer process. After wafer bonding the laser chips to the slider wafer, the shape and optical alignment of the photonic elements are precisely aligned en masse by lithographic processing.

Abstract: Methods of bonding together semiconductor structures include annealing a first metal feature on a first semiconductor structure, bonding the first metal feature to a second metal feature of a second semiconductor structure to form a bonded metal structure that comprises the first metal feature and the second metal feature, and annealing the bonded metal structure. Annealing the first metal feature may comprise subjecting the first metal feature to a pre-bonding thermal budget, and annealing the bonded metal structure may comprise subjecting the bonded metal structure to a post-bonding thermal budget that is less than the pre-bonding thermal budget. Bonded semiconductor structures are fabricated using such methods.

Abstract: A method for connecting substrates is provided. The method includes the steps of: preparing a first wiring substrate having a first substrate including a first region and a second region which are provided with a first metal wire, wherein an area ratio between the first region and the first metal wires in the first region is different from an area ratio between the second region and the first metal wire in the second region; heating the first wiring substrate to bend the first wiring substrate; and electrically connecting a third wiring on a third substrate to the first metal wire provided on the first wiring substrate, thereby mounting the first wiring substrate on the third substrate in a manner that the first surface of the first substrate is nonparallel to the first surface of the third substrate.

Abstract: A method for forming a semiconductor device package includes providing a lead frame array having a plurality of leads. Each of the plurality of leads includes an opening extending through the lead from a first surface of the lead to a second surface of the lead, opposite the first surface, and each of the openings is at least partially filled with a solder wettable material. A plurality of semiconductor devices are attached to the lead frame array. The plurality of semiconductor devices are encapsulated, and, after encapsulating, the plurality of semiconductor devices are separated along separation lines which intersect the openings.

Abstract: A method for manufacture of an integrated circuit package system includes: providing a leadframe with an integrated circuit mounted thereover; encapsulating the integrated circuit with an encapsulation; mounting an etch barrier below the leadframe; and etching the leadframe.

Abstract: A semiconductor device is made by disposing a plurality of semiconductor die on a carrier and creating a gap between each of the semiconductor die. A first insulating material is deposited in the gap. A portion of the first insulating material is removed. A conductive layer is formed over the semiconductor die. A conductive lining is conformally formed on the remaining portion of the first insulating material to form conductive via within the gap. The conductive vias can be tapered or vertical. The conductive via is electrically connected to a contact pad on the semiconductor die. A second insulating material is deposited in the gap over the conductive lining. A portion of the conductive via may extend outside the first and second insulating materials. The semiconductor die are singulated through the gap. The semiconductor die can be stacked and interconnected through the conductive vias.

Abstract: A dual-face package has an LSI chip sealed with a mold resin, and electrodes for external connections on both of the front face and the back face. The LSI chip is bonded onto the die pad of a leadframe whose outer lead portions are exposed as back-face electrodes at at least the back face. The LSI chip and a plurality of inner lead portions of the leadframe are connected by wiring. At least some of the plurality of inner lead portions have front-face electrodes integrally formed by working a portion of the leadframe. Head faces of the front-face electrodes, or bump electrodes connected to the respective head faces of the front-face electrodes serve as electrodes for external connections to another substrate, element, or the like.

Abstract: A method and structure provides a Direct Write Wafer Level Chip Scale Package (DWWLCSP) that utilizes permanent layers/coatings and direct write techniques to pattern these layers/coatings, thereby avoiding the use of photoimagable materials and photo-etching processes.

Abstract: A semiconductor device has a plurality of semiconductor die mounted to a carrier. An adhesive material is deposited over a portion of the semiconductor die and carrier to secure the semiconductor die to the carrier. The adhesive material is deposited over a side of the semiconductor die and over a surface of the carrier. The adhesive material can be deposited over a corner of the semiconductor die, or over a side of the semiconductor die, or around a perimeter of the semiconductor die. An encapsulant is deposited over the semiconductor die and carrier. The adhesive material reduces shifting of the semiconductor die with respect to the carrier during encapsulation. The adhesive material is cured and the carrier is removed. The adhesive material can also be removed. An interconnect structure is formed over the semiconductor die and encapsulant. The semiconductor die are singulated through the encapsulant and interconnect structure.

Abstract: In a reflow process for connecting a semiconductor die and a package substrate, the temperature gradient and thus the thermally induced mechanical forces in a sensitive metallization system of the semiconductor die may be reduced during the cooling phase. To this end, one or more heating intervals may be introduced into the cooling phase, thereby efficiently reducing the temperature difference. In other cases, the central region may additionally be cooled by providing appropriate locally restricted mechanisms, such as a locally restricted gas flow and the like. Consequently, desired short overall process times may be obtain without contributing to increased yield losses when processing sophisticated metallization systems on the basis of a lead-free contact regime.

Abstract: Stacked microelectronic devices and methods of manufacturing stacked microelectronic devices are disclosed herein. In one embodiment, a method of manufacturing a microelectronic device includes forming a plurality of electrically isolated, multi-tiered metal spacers on a front side of a first microelectronic die, and attaching a back-side surface of a second microelectronic die to individual metal spacers. In another embodiment, the method of manufacturing the microelectronic device may further include forming top-tier spacer elements on front-side wire bonds of the first die.

Abstract: An implantable hermetically sealed microelectronic device and method of manufacture are disclosed. The microelectronic device of the present invention is hermetically encased in a insulator, such as alumina formed by ion bean assisted deposition (“IBAD”), with a stack of biocompatible conductive layers extending from a contact pad on the device to an aperture in the hermetic layer. In a preferred embodiment, one or more patterned titanium layers are formed over the device contact pad, and one or more platinum layers are formed over the titanium layers, such that the top surface of the upper platinum layer defines an external, biocompatible electrical contact for the device. Preferably, the bottom conductive layer is larger than the contact pad on the device, and a layer in the stack defines a shoulder.

Abstract: A method for producing a semiconductor device such as a RC-IGBT or a BIGT having a patterned surface wherein partial regions doped with dopants of a first conductivity type and regions doped with dopants of a second conductivity type are on a same side of a semiconductor substrate is proposed. An exemplary method includes: (a) implanting dopants of the first conductivity type and implanting dopants of the second conductivity type into the surface to be patterned; (b) locally activating dopants of the first conductivity type by locally heating the partial region of the surface to be patterned to a first temperature (e.g., between 900 and 1000° C.) using a laser beam similar to those used in laser annealing; and (c) activating the dopants of the second conductivity type by heating the substrate to a second temperature lower than the first temperature (e.g., to a temperature below 600° C.).

Abstract: A method of manufacturing a reverse blocking insulated gate bipolar transistor to form an isolation layer for bending and extending a pn junction, which exhibits a high reverse withstand voltage, to the front surface side. This ensures a high withstand voltage in the reversed direction and reduces leakage current in the reversely biased condition. Formation of a tapered groove by an anisotropic alkali etching process is conducted, resulting in a semiconductor substrate left with a thickness of at least 60 ?m between one principal surface and the bottom surface of the tapered groove formed from the other principal surface.

Abstract: A method of fabricating a gate includes sequentially forming an insulation layer and a conductive layer on substantially an entire surface of a substrate. The substrate has a device isolation layer therein and a top surface of the device isolation layer is higher than a top surface of the substrate. The method includes planarizing a top surface of the conductive layer and forming a gate electrode by patterning the insulation layer and the conductive layer.

Abstract: A thin film transistor array substrate having a high charge mobility and that can raise a threshold voltage, and a method of fabricating the thin film transistor array substrate are provided. The thin film transistor array substrate includes: an insulating substrate; a gate electrode formed on the insulating substrate; an oxide semiconductor layer comprising a lower oxide layer formed on the gate electrode and an upper oxide layer formed on the lower oxide layer, such that the oxygen concentration of the upper oxide layer is higher than the oxygen concentration of the lower oxide layer; and a source electrode and a drain electrode formed on the oxide semiconductor layer and separated from each other.

Abstract: A pixel structure includes a substrate; a scan line; a gate electrode; an insulating layer disposed on the scan line, the gate electrode and the substrate; a channel and a data line disposed on the insulating layer; a source electrode and a drain electrode disposed on the channel; a passivation layer; a pixel electrode and a connecting electrode. The data line does not overlap the scan line. The passivation layer disposed on the source electrode and the drain electrode includes a first contact hole partially exposing the drain electrode, and a plurality of second contact holes partially exposing the data line or the scan line. The pixel electrode disposed on the passivation layer is electrically connected to the drain electrode through the first contact hole. Furthermore, the connecting electrode disposed on the passivation layer is electrically connected to the data line or the scan line through the second contact holes.

Abstract: A TFT array substrate includes a substrate, at least one gate line and gate electrode, a gate insulating layer, and at least one channel component, source electrode, drain electrode and data line. The gate line and gate electrode are disposed on the substrate, wherein both of the gate line and gate electrode have first and second conductive layers, the first conductive layer is formed on the substrate, the first conductive layer contains molybdenum nitride , the second conductive layer is formed on the first conductive layer, and the second conductive layer contains copper. The gate insulating layer is disposed on the gate line, gate electrode and the substrate. The channel component is disposed on the gate insulating layer. The source electrode and drain electrode are disposed on the channel component, and data line is disposed on the gate insulating layer.

Abstract: It is an object of the present invention to provide a thin film transistor in which an oxide semiconductor film containing indium (In), gallium (Ga), and zinc (Zn) is used and contact resistance of a source or a drain electrode layer is reduced, and a manufacturing method thereof. An IGZO layer is provided over the source electrode layer and the drain electrode layer, and source and drain regions having lower oxygen concentration than the IGZO semiconductor layer are intentionally provided between the source and drain electrode layers and the gate insulating layer, so that ohmic contact is made.

Abstract: A thin film transistor (“TFT”) includes a poly silicon layer formed on a flexible substrate and including a source region, a drain region, and a channel region, and a gate stack formed on the channel region of the poly silicon layer, wherein the gate stack includes first and second gate stacks, and a region of the poly silicon layer between the first and second gate stacks is an off-set region. A method of manufacturing the TFT is also provided.

Abstract: Manufacturing technique for a semiconductor device having a first MISFET of an n channel-type and a second MISFET of a p channel type, including forming a first insulating film composed of a silicon oxide film or a silicon oxynitride film on a semiconductor substrate for forming a gate insulating film of the respective MISFETs; depositing metal elements on the first insulating film; forming of a silicon film on the first insulating film for the forming of a gate electrode of the respective MISFETs; and producing the respective gate electrodes by patterning the silicon film. The depositing of the metal films on the first insulating film is such that there is produced in the vicinity of the interface between the gate electrode and the gate insulating film a surface density of the metal elements within a range of 1×1013 to 5×1014 atoms/cm2.

Abstract: Semiconductor arrays including a plurality of access devices disposed on a buried conductive line and methods for forming the same are provided. The access devices each include a transistor having a source region and drain region spaced apart by a channel region of opposite dopant type and an access line associated with the transistor. The access line may be electrically coupled with one or more of the transistors and may be operably coupled to a voltage source. The access devices may be formed in an array on one or more conductive lines. A system may be formed by integrating the semiconductor devices with one or more memory semiconductor arrays or conventional logic devices, such as a complementary metal-oxide-semiconductor (CMOS) device.

Abstract: A thin film capacitor is characterized by forming a lower electrode, coating a composition onto the lower electrode without applying an annealing process having a temperature of greater than 300° C., drying at a predetermined temperature within a range from ambient temperature to 500° C., and calcining at a predetermined temperature within a range of 500 to 800° C. and higher than a drying temperature. The process from coating to calcining is performed the process from coating to calcining once or at least twice, or the process from coating to drying is performed at least twice, and then calcining is performed once. The thickness of the dielectric thin film formed after the first calcining is 20 to 600 nm. The ratio of the thickness of the lower electrode and the thickness of the dielectric thin film formed after the initial calcining step (thickness of lower electrode/thickness of the dielectric thin film) is preferably in the range 0.10 to 15.0.

Abstract: Disclosed is a semiconductor component arrangement and a method for producing a semiconductor component arrangement. The method comprises producing a trench transistor structure with at least one trench disposed in the semiconductor body and with at least an gate electrode disposed in the at least one trench. An electrode structure is disposed in at least one further trench and comprises at least one electrode. The at least one trench of the transistor structure and the at least one further trench are produced by common process steps. Furthermore, the at least one electrode of the electrode structure and the gate electrode are produced by common process steps.

Abstract: An example of a method of fabricating a gate oxide of a floating gate transistor includes forming a plurality of shallow trench isolation (STI) regions in a silicon wafer. The method also includes selectively filling the STI regions with oxide. Further, the method includes forming sacrificial oxide regions on the silicon wafer. Furthermore, the method includes forming implant regions in the silicon wafer. In addition, the method includes selectively removing the sacrificial oxide regions. The method further includes forming the gate oxide.

Abstract: Devices can be fabricated using a method of growing nanoscale structures on a semiconductor substrate. According to various embodiments, nucleation sites can be created on a surface of the substrate. The creation of the nucleation sites may include implanting ions with an energy and a dose selected to provide a controllable distribution of the nucleation sites across the surface of the substrate. Nanoscale structures may be grown using the controllable distribution of nucleation sites to seed the growth of the nanoscale structures. According to various embodiments, the nanoscale structures may include at least one of nanocrystals, nanowires, or nanotubes. According to various nanocrystal embodiments, the nanocrystals can be positioned within a gate stack and function as a floating gate for a nonvolatile device. Other embodiments are provided herein.

Abstract: The semiconductor element includes an oxide semiconductor layer on an insulating surface; a source electrode layer and a drain electrode layer over the oxide semiconductor layer; a gate insulating layer over the oxide semiconductor layer, the source electrode layer, and the drain electrode layer; and a gate electrode layer over the gate insulating layer. The source electrode layer and the drain electrode layer have sidewalls which are in contact with a top surface of the oxide semiconductor layer.

Abstract: The invention provides a method for fabricating a deep trench isolation including: providing a substrate; forming a first trench in the substrate; conformally forming a first liner layer on the sidewall and bottom of the first trench; forming a first filler layer on the first liner layer and filling the first trench; forming an epitaxial layer on the substrate and the first trench; forming a second trench through the epitaxial layer and over the first trench; conformally forming a second liner layer on the sidewall and bottom of the second trench; and forming a second filler layer on the second liner layer and filling the second trench.

Abstract: A method for fabricating a recessed channel access transistor device is provided. A semiconductor substrate having thereon a recess is provided. A gate dielectric layer is formed in the recess. A gate material layer is then deposited into the recess. A dielectric cap layer is formed on the gate material layer. The dielectric cap layer and the gate material layer are etched to form a gate pattern. A liner layer is then formed on the gate pattern. A spacer is formed on the liner layer on each sidewall of the gate pattern. The liner layer not masked by the spacer is etched to form an undercut recess that exposes a portion of the gate material layer. The spacer is then removed. The exposed portion of the gate material layer in the undercut recess is oxidized to form an insulation block therein.

Abstract: The present invention discloses a manufacturing method of a high voltage device. The high voltage device is formed in a first conductive type substrate. The high-voltage device includes: a second conductive type buried layer; a first conductive type high voltage well; and a second conductive type body. The high voltage well is formed by the same step for forming a first conductive type well or a first conductive type channel stop layer of a low voltage device formed in the same substrate. The body is formed by the same step for forming a second conductive type well of the low voltage device.

Abstract: A methods of forming a flash memory device are provided. The flash memory device comprises a silicon dioxide layer on a substrate and a silicon nitride layer that is formed on the silicon dioxide layer. The properties of the silicon nitride layer can be modified by any of: exposing the silicon nitride layer to ultraviolet radiation, exposing the silicon nitride layer to an electron beam, and by plasma treating the silicon nitride layer. A dielectric material is deposited on the silicon nitride layer and a conductive date is formed over the dielectric material. The flash memory device with modified silicon nitride layer provides an increase in charge holding capacity and charge retention time of the unit cell of a non-volatile memory device.

Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a gate over a substrate. The method includes performing a first implantation process to form a first doped region in the substrate, the first doped region being adjacent to the gate. The method includes performing a second implantation process to form a second doped region in the substrate, the second doped region being formed farther away from the gate than the first doped region, the second doped region having a higher doping concentration level than the first doped region. The method includes removing portions of the first and second doped regions to form a recess in the substrate. The method includes epitaxially growing a third doped region in the recess, the third doped region having a higher doping concentration level than the second doped region.

Abstract: An integrated circuit device and method for manufacturing the integrated circuit device provide improved control over a shape of a trench for forming the source and drain features of integrated circuit device, by forming a second doped region in a first doped region and removing the first and the second doped regions by a first and a second wet etching processes.

Abstract: A semiconductor device includes a MOS transistor, a source electrode and a drain electrode on the MOS transistor each include a first carbon doped silicon layer including carbon at a first carbon concentration and phosphorus at a first phosphorus concentration and a second carbon doped silicon layer over the first silicon carbide layer, which includes phosphorus at a second phosphorus concentration higher than the first phosphorus concentration, and which includes carbon at a second carbon concentration less than or equal to the first carbon concentration.

Abstract: The present disclosure provides a bipolar junction transistor (BJT) device and methods for manufacturing the BJT device. In an embodiment, the BJT device includes: a semiconductor substrate having a collector region, and a material layer disposed over the semiconductor layer. The material layer has a trench therein that exposes a portion of the collector region. A base structure, spacers, and emitter structure are disposed within the trench of the material layer. Each spacer has a top width and a bottom width, the top width being substantially equal to the bottom width.

Abstract: An X-ray image sensor having scintillating material embedded into wave-guide structures fabricated in a CMOS image sensor (CIS). After the CIS has been fabricated, openings (deep pores) are formed in the back side of the CIS wafer. These openings terminate at a distance of about 1 to 5 microns below the upper silicon surface of the wafer. The depth of these openings can be controlled by stopping on a buried insulating layer, or by stopping on an epitaxial silicon layer having a distinctive doping concentration. The openings are aligned with corresponding photodiodes of the CIS. The openings may have a shape that narrows as approaching the photodiodes. A thin layer of a reflective material may be formed on the sidewalls of the openings, thereby improving the efficiency of the resulting waveguide structures. Scintillating material (e.g., CsI(Tl)) is introduced into the openings using a ForceFill™ technology or by mechanical pressing.

Abstract: A method of manufacturing resistive memory includes the steps: forming a first implanted stacked structure having a first impurity diffusion layer, a second impurity diffusion layer, and a third impurity diffusion layer in a substrate; etching at least the first implanted stacked structure to form a plurality of second implanted stacked structures, wherein the first impurity diffusion layers are first signal lines; forming a plurality of first insulating layers between the second implanted stacked structures; etching the second implanted stacked structures to form a plurality of third implanted stacked structures, wherein the first signal lines are not etched; forming a plurality of second insulating layers between the third implanted stacked structures; forming a plurality of memory material layers electrically coupled to the third impurity diffusion layers; and forming a plurality of second signal lines perpendicular to the first signal lines and electrically coupled to the memory material layers.

Abstract: Methods of forming embedded, multilayer capacitors in printed circuit boards wherein copper or other electrically conductive channels are formed on a dielectric substrate. The channels may be preformed using etching or deposition techniques. A photoimageable dielectric is an upper surface of the laminate. Exposing and etching the photoimageable dielectric exposes the space between the copper traces. These spaces are then filled with a capacitor material. Finally, copper is either laminated or deposited atop the structure. This upper copper layer is then etched to provide electrical interconnections to the capacitor elements. Traces may be formed to a height to meet a plane defining the upper surface of the dielectric substrate or thin traces may be formed on the remaining dielectric surface and a secondary copper plating process is utilized to raise the height of the traces.