Abstract: In order to provide a system which detects and classifies abnormality in a solar battery even during power generation, an output voltage and an output current of the solar battery during power generation are detected, and a solar battery characteristic equation and a threshold value for detecting an abnormal state are calculated using the detected voltage value and current value and the measurement data of an external environment measurement unit. The kind of abnormal state of the solar battery is classified using the calculation result of the characteristic equation and the threshold value.

Abstract: A test device of a semiconductor device for testing a semiconductor device including a plurality of interface pads includes a plurality of coupling units, each configured to be coupled to a corresponding one of the plurality of interface pads, a channel configured to be coupled to the plurality of coupling units, a voltage generating unit configured to generate a test voltage applied to the channel, and a current measuring unit configured to measure a current that flows on the channel in response to the test voltage.

Abstract: A test structure of a semiconductor wafer includes a series of electrical units connected electrically in series output-to-input in an open loop configuration. The series of electrical units is configured to have alternating output voltages, such that each electrical unit is configured to output a voltage opposite an output voltage of a preceding electrical unit. Each electrical unit is configured to have an output voltage that alternates when an input voltage applied to a first electrical unit in the series of electrical units alternates.

Abstract: A LED light source measuring instrument includes a shell portion and a test portion. The shell portion supports the test portion. The test portion includes a carrier plate for carrying a LED light source, and provides automatic electrical connections to a bottom surface of an SMT LED light source. The test portion further includes a flexible tube and a vacuum pump, at least one air hole set in the test portion, the flexible tube connecting with the air hole and the vacuum pump, the vacuum provided by the vacuum pump holding the LED light source firmly to the under test zone of the carrier plate.

Abstract: A system for detecting unauthorized removal or tampering. The system comprises a printed circuit board having tamper-response electronics and a flexible circuit assembly defining a connector portion, a switch portion, and a cable extending between the connector portion and the switch portion. The flexible circuit assembly is coupled with the printed circuit board at the connector portion. The flexible circuit assembly comprises a plurality of layers each comprising a flexible dielectric substrate and a switch disposed in the switch portion. The switch is in electrical communication with the tamper-response electronics of the printed circuit board via a conductive path. The flexible circuit assembly also comprises a tamper-responsive conductor circuit enclosing the conductive path. The tamper-responsive conductor circuit is in electrical communication with the tamper-response electronics of the printed circuit board.

Abstract: A method and apparatus for camouflaging an application specific integrated circuit (ASIC), wherein the ASIC comprises a plurality of interconnected functional logic is disclosed. The method adds functionally inert elements to the logical description or provides alternative definitions of standard logical cells to make it difficult for reverse engineering programs to be used to discover the circuit's function. Additionally, post processing may be performed on GDS layers to provide a realistic fill of the empty space so as to resemble structural elements found in a functional circuit.

Abstract: A multiple signal format output driver is configurable to provide a current-mode logic (CML) output signal in response to a CML value of one or more first values of the control signal. The output driver is configurable to provide a low-power, low-voltage positive emitter-coupled logic (low-power LVPECL) output signal in response to a low-power LVPECL value of the one or more first values of the control signal. The output driver is configurable to provide a low-voltage differential signaling (LVDS) output signal in response to an LVDS value of the one or more first values of the control signal. The output driver may be configurable to provide a LVPECL output signal in response to a second value of the control signal. The output driver may be configurable to provide a high-speed current steering logic (HCSL) output in response to a third value of the control signal.

Abstract: Provided is a semiconductor chip for a programmable logic device which can hold configuration data even when supply of a power supply potential is interrupted and can operate with low power. Further, a semiconductor device using the semiconductor chip is provided. The semiconductor chip can hold configuration data even when supply of a power supply potential is interrupted and can operate with low power. The semiconductor chip includes a transistor and a pad connected to the transistor. The transistor is formed using a material which allows a sufficient reduction in off-state current of the transistor; for example, an oxide semiconductor material that is a wide bandgap semiconductor.

Abstract: A decoder for sequentially enabling outputs in response to clock signal inputs is described including X number of logic stages corresponding to X number of outputs of the decoder. Each of the logic stages has a plurality of inputs, wherein each logic stage includes fewer than log2X inputs for receiving the clock signal inputs.

Abstract: A circuit for detecting a time skew, including: at least two comparators; a first set of paths respectively connecting a first source of a first signal to said comparators; and a second set of paths respectively connecting a second source of a second signal to said comparators, each comparator detecting a possible skew between said first and second signals.

Abstract: A key press detecting circuit and method detect the status of multiple keys through a single pin. In an embodiment, a constant current is provided to apply to a key module through a single pin, to generate a voltage at the single pin that is related to the equivalent resistance of the key module observed from the single pin, and the voltage of the single pin is compared with a set of reference values to identify the status of the plurality of keys. In another embodiment, a variable current is provided to apply to a key module through a single pin in such a way that the variable current is adjusted to maintain a constant voltage at the single pin, and the variable current is compared with a set of reference values to identify the status of the plurality of keys.

Abstract: The invention describes methods and systems for digital synthesis of electric signals. According to the invention, one or more bit-patterns are provided, each indicative of a rectangular waveform having a characteristic frequency. Further to determining a selected signal frequency to be synthesized, a selected bit-pattern associated therewith is obtained. Bits of the selected bit-pattern are cyclically serialized to generate a substantially rectangular waveform signal comprising the characteristic frequency. Then, the signal is filtered to suppress spurious frequencies outside a certain unfiltered frequency band which corresponds to the selected bit-pattern to thereby obtain a filtered signal with prominent frequency component corresponding to the selected signal frequency.

Abstract: In one embodiment, a power switch driving circuit can include: (i) a first circuit configured receiving a control signal, and controlling a first transistor gate, where a first transistor source is coupled to a power supply, and a first transistor drain is coupled to a driving signal configured to control a power switch; (ii) a second circuit configured to receive the control signal, and to control a second transistor gate, where a second transistor source is coupled to ground, and a second transistor drain is coupled to the driving signal; and (iii) a driving enhancement circuit having a third transistor and a first inverter that is configured to invert an output of the first circuit to control a third transistor gate, where a third transistor source is coupled to the driving signal, and a third transistor drain is coupled to the power supply.

Abstract: To reduce power consumption, a semiconductor device includes a power source circuit for generating a power source potential, and a power supply control switch for controlling supply of the power source potential from the power source circuit to a back gate of a transistor, and the power supply control switch includes a control transistor for controlling conduction between the power source circuit and the back gate of the transistor by being turned on or off in accordance with a pulse signal that is input into a control terminal of the control transistor. The power source potential is intermittently supplied from the power source circuit to the back gate of the transistor, using the power supply control switch.

Abstract: An apparatus for monitoring timing of a plurality of critical paths of a functional circuit includes a plurality of canary circuits, each configured to be coupled to a critical path of a functional circuit for detecting and outputting critical timing events. Each canary circuit includes an adjustable delay element and an analyser circuit for receiving a count of the critical timing event output from at least one of the plurality of canary circuits for a predetermined time interval for a plurality of delay values of the adjustable delay elements and for determining a probability distribution of critical timing events of the at least one of the plurality of critical paths for the predetermined time interval for the plurality of delay values.

Abstract: A controller for an SMPS is disclosed. The controller applies a frequency jitter to the SMPS to reduce Electromagnetic Interference (EMI) and/or audible noise. A second input variable is multiplied by a correlated jitter signal, in order to compensate the output power for the frequency jitter. A corresponding method is also disclosed. Since the jitter compensation occurs within the controller, the method is particularly suitable for controllers operating under different control modes for different output powers (or other output criteria). The multiplicative compensation is applicable across a wide range of converter types.

Abstract: System and method for signal synchronization. The system includes a first selection component, a first signal generator, a second signal generator and a first gate drive component. The first selection component is configured to receive a first mode signal and generate a first selection signal based on at least information associated with the first mode signal. The first signal generator is configured to, if the first selection signal satisfies one or more first conditions, receive a first input signal and generate at least a first clock signal based on at least information associated with the first input signal. Furthermore, the first gate drive component is configured to, if the first selection signal satisfies the one or more first conditions, receive at least the first clock signal and output a first drive signal to a first switch.

Abstract: A system for synchronizing a first clock and a second clock includes a receiver associated with the first clock, configured to receive a remote pulse from the second clock. The remote pulse has a pulse repetition frequency and spectral characteristics that are known to the local clock. The system also includes a local pulse emitter configured to create a local pulse at the first clock, and optics configured to align the local pulse and the remote pulse. The system further includes an interferometer configured to create an interference pattern between the local pulse and the remote pulse. A controller is provided that is configured to calculate a time delay between the first clock and the second clock based on the interference pattern between the local pulse and the remote pulse.

Abstract: A frequency synthesizer capable of generating a clock signal having reduced digital spurs and reduced jitter is described. An apparatus includes a frequency modulator configured to generate a divide control signal and a digital quantization error signal in response to a divide ratio. The apparatus includes a phase modulator configured to generate a phase error signal based on the digital quantization error signal. The phase modulator is an n-order sigma-delta modulator module, n being an integer greater than one. The apparatus may include an interpolative divider configured to generate a feedback signal in a phase-locked loop (PLL) based on an output signal of the PLL, the divide control signal, and the phase error signal. The interpolative divider may include the frequency modulator and the phase modulator. The phase modulator may have a unity gain signal transfer function.

Abstract: A semiconductor device including an integrator circuit, in which electric discharge from a capacitor can be reduced to shorten time required for charging the capacitor in the case where supply of power supply voltage is stopped and restarted, and a method for driving the semiconductor device are provided. One embodiment has a structure in which a transistor with small off-state current is electrically connected in series to a capacitor in an integrator circuit. Further, in one embodiment of the present invention, a transistor with small off-state current is electrically connected in series to a capacitor in an integrator circuit; the transistor is on in a period during which power supply voltage is supplied; and the transistor is off in a period during which supply of the power supply voltage is stopped.

Abstract: An input jitter filter for a phase-locked loop and methods of use are provided. The method includes generating a masking zone around falling edges of a feedback signal. The method also includes determining that one or more outputs of a phase detector fall within the masking zone. The method further includes ignoring input clock noise when the one or more outputs of the phase detector fall within the masking zone.

Abstract: The present disclosure provides a clock generator circuit comprising a master clock generator unit configured to generate a master clock signal, and a plurality of slave phase locked loop units. Each of the plurality of slave phase looked loop units is configured to receive the master clock signal as an input reference signal and a corresponding source clock signal. The slave phase locked loop unit may comprise an inner loop and an outer loop. The inner loop may comprise a frequency synthesizer locked on a master clock signal received from a master clock generator unit, while the outer loop may comprise a binary phase detector, an output of which goes to a loop filter with proportional and integral action, controlling the inner loop frequency value via a sigma delta input.

Abstract: A phase-locked loop (PLL) circuit is provided. The PLL circuit includes a phase frequency detector (PFD), a first charge pump (CP), a second CP, a first loop component set, a second loop component set, a voltage control oscillator (VCO) and a frequency divider. The first CP and the second CP are coupled to the PFD. The first loop component set is coupled between the first CP and the VCO. The second loop component set is coupled between the second CP and the VCO. The frequency divider is coupled between the PFD and the VCO. The first loop component set generates an offset current to adjust the working range of the first CP and the second CP. The second loop component set generates an offset current and a DC adjustment voltage to control the control voltage outputted to the VCO.

Abstract: A method for synchronizing input sampling to desired phase angles of sinusoidal signals including determining a delay time period for converging a next sample point to a next desired phase angle based on a phase error value.

Abstract: A PLL fail-over circuit technique and method to mitigate the effects of single-event transients comprises providing a pair of substantially identical phase-locked loops and producing a respective delayed clock signal from each. The outputs of the phase-locked loops are monitored for errors comprising high frequency transients or differences in clock signal outputs from a reference frequency. A clock out signal is output representative of the first delayed clock signal if an error is detected in the second phase-locked loop and the second delayed clock signal is output if an error is detected in the first phase-locked loop.

Abstract: A delay-locked loop includes a first delay unit, a second delay unit, a third delay unit, a phase detector, and a controller. The first delay unit generates a first delay clock according to a clock and a first delay time. The second delay unit generates a second delay clock according to the first delay clock and a second delay time. The third delay unit generates a third delay clock according to the second delay clock and a third delay time. The phase detector generates a phase detection signal according to the clock and the second delay clock. The controller generates and outputs a phase control signal according to the phase detection signal. The second delay unit and the third delay unit adjust the second delay time and the third delay time respectively according to the phase control signal.

Abstract: Low power, jitter and latency clocking with common reference clock signals for on-package input/output interfaces. A filter phase locked loop circuit in a master device on a first die provides a clock signal having a frequency of 2F. A local phase locked loop circuit in the master device on the first die is coupled with the filter phase locked loop to provide a clock signal to functional components of the master device through a local clock divider circuit to provide a clock signal of F to the functional components. A remote phase locked loop circuit in a slave device on a second die is coupled with the filter phase locked loop to provide a clock signal to one or more functional components of the slave device through a local clock divider circuit to provide a clock signal of F to the functional components.

Abstract: LC tank and ring-based VCOs are disclosed that each include a differential pair of transistors for steering a tail current generated by a current source responsive to a bias voltage. A biasing circuit generates the bias voltage such that a transconductance for the transistors in the differential pairs is inversely proportional to a resistance.

Abstract: A semiconductor device includes a controlled oscillator and a control unit. The controlled oscillator includes a resonance circuit, an amplification unit, and a current adjustment unit. The resonance circuit includes one or a plurality of inductors and a first capacitive unit having a variable capacitance value. The amplification unit is connected to the resonance circuit, and outputs a local oscillation signal having an oscillation frequency corresponding to a resonance frequency of the resonance circuit. The current adjustment unit adjusts a value of a drive current to be supplied to the amplification unit. The control unit controls the capacitance value of the first capacitive unit and the current adjustment unit. When the control unit instructs the current adjustment unit to change the value of the drive current to be supplied to the amplification unit, the control unit also changes the capacitance value of the first capacitive unit.

Abstract: An edge alignment apparatus includes: a signal source, for generating a first and a second square wave signals; a phase delay circuit, for receiving the first and the second square wave signals to generate a delayed first and a delayed second square wave signals; a data circuit, for generating a third square wave signal according to the delayed second square wave signal; and a phase calibrating circuit, for receiving the third square wave signal and the delayed first squared wave signal to generate at least one phase tuning signal to the phase delay circuit for tuning a phase difference between the delayed first and the delayed second square wave signals, such that a signal edge of the third square wave signal aligns with that of the first square wave signal. The first, second and third square wave signals have a same frequency.

Abstract: There is described a method and corresponding pulse generating device, for generating an output pulse signal having an output pulse duration. The method comprises: receiving at an input port an input pulse signal comprising an input pulse duration; duplicating the input pulse signal into a first digital pulse signal and a second digital pulse signal each comprising the input pulse duration; delaying at least one of the first and the second digital pulse signals by a time delay to obtain respectively a first and a second delayed digital pulse signal, a time delay difference between the first and the second delayed digital pulse signals being substantially equal to the output pulse duration; logically combining the first and the second delayed digital pulse signals to generate the output pulse signal with the output pulse duration smaller than the input pulse duration; and outputting the output pulse signal at an output port.

Abstract: A data output circuit and a data output method thereof are provided. The data output circuit includes a delay locked loop, a duty ratio correction block, and an output unit. The delay locked loop corrects a duty ratio of a first internal clock. The delay locked loop includes a correction enable signal output unit configured to output a correction enable signal when the operation of correcting the duty ratio of the first internal clock is completed. The duty ratio correction block corrects the duty ratio of the first internal clock by using a duty ratio detection signal in response to the correction enable signal, and outputs the corrected first internal clock as an output clock. The output unit detects a duty ratio of the output clock, generates the duty ratio detection signal to the duty ratio correction block, and outputs a data strobe signal in response to the output clock.

Abstract: Circuits and methods are provided for generating clock signals and correcting duty cycle distortion in clock signals. A circuit for generating a clock signal includes a multiplexer circuit and an edge-triggered flip-flop circuit. The multiplexer circuit selectively outputs one of a plurality of input clock signals. The edge-triggered flip-flop detects a transitioning edge of the input clock signal that is selectively output from the multiplexer circuit, and in response to the detection, samples a logic level of a received data signal, and generates a transition of an output clock signal at an output port of the edge-triggered flip-flop. The multiplexer circuit selectively outputs one of the plurality of input clock signals to a clock signal port of the edge-triggered flip-flop, based on a logic level of the output clock signal at the output port of the edge-triggered flip-flop, which is input to a select control port of the multiplexer circuit.

Abstract: A multi-phase partial response equalizer circuit includes sampler circuits that sample an input signal to generate sampled signals in response to sampling clock signals having different phases. A first multiplexer circuit selects one of the sampled signals as a first sampled bit to represent the input signal. A first storage circuit coupled to an output of the first multiplexer circuit stores the first sampled bit in response to a first clock signal. A second multiplexer circuit selects one of the sampled signals as a second sampled bit to represent the input signal based on the first sampled bit. A second storage circuit stores a sampled bit selected from the sampled signals in response to a second clock signal. A time period between the second storage circuit storing a sampled bit and the first storage circuit storing the first sampled bit is substantially greater than a unit interval in the input signal.

Abstract: Time-Mode Signal Processing (TMSP) offers a means for offsetting some of the challenges for analog circuit designs when exploiting CMOS circuit processes designed for digital applications. It would therefore be beneficial to provide a digital method for the storage, addition and subtraction of Time-Mode variables as these offer significant benefit to providing TMSP techniques and expanding their exploitation within devices, systems, and applications. Whilst driven by CMOS process challenges the TM circuits outlined may exploit essentially any digital circuit technology since they are based upon delay. The inventors present an approach to TM variables wherein a switched delay unit is exploited and adopted such that the instantaneous phase difference between two rising signal edges can be latched and used to perform various arithmetic operations. Beneficially, the technique allows analog sampled-data signal processing to be implemented within digital circuitry.

Abstract: In accordance with an embodiment, an offset-compensated active load includes a pair of transistors having control electrodes connected to their drain electrodes through coupling devices. The control electrodes of the transistors are connected to each other through a plurality of charge storage elements. In accordance with another embodiment, an offset current is generated in response to coupling input terminals of an input stage together. The offset current flows towards an active load which generates an offset voltage in response to the offset current. The offset voltage is stored in the plurality of charge storage devices of the offset-compensated active load.

Abstract: Apparatus and method for coupling high voltages for a semiconductor device via high voltage switches are disclosed. A high voltage switch includes a switch and a level shifter. The switch is defined between a voltage source and a voltage output. An enable line is coupled to a first transistor of the switch. The level shifter includes an input and an output. A characterization line is coupled to the input of the level shifter and the output of the level shifter is coupled to a second transistor of the switch. The level shifter further includes a power rail that is coupled to the switch between the first transistor and the second transistor.

Abstract: A circuit comprising a first input transistor having a drain, a source and a gate. A first diode connected transistor having a drain, a source and a gate, wherein the gate of the first diode connected transistor is coupled to the drain of the first diode connected transistor, and the drain of the first input transistor is coupled to the drain of the first diode connected transistor. A first load transistor having a drain, a source and a gate, wherein the drain of the first load transistor is coupled to the drain of the first diode connected transistor and the source of the first load transistor is coupled to the source of the first diode connected transistor.

Abstract: A semiconductor switch comprises a PNPN structure arranged to provide an SCR-like functionality, and a MOS gate structure, preferably integrated on a common substrate. The switch includes ohmic contacts for the MOS gate, and for the cathode and gate regions of the PNPN structure; the anode contact is intrinsic. A fixed voltage is typically applied to an external node. The MOS gate structure allows current to be conducted between the external node and the intrinsic anode when on, and the PNPN structure conducts the current from the anode to the cathode when an appropriate voltage is applied to the gate contact. Regenerative feedback keeps the switch on once it begins to conduct. The MOS gate inhibits the flow of current between the external node and anode—and thereby turns off the switch—when off. When on, the MOS gate's channel resistance serves as a ballast resistor.

Abstract: A zero-crossing detector with effective offset cancellation includes a set of series connected capacitors and an amplifier having an input terminal. An offset capacitor is operatively connected between the amplifier and the set of series connected capacitors. A switch is operatively connected to the input terminal, and an offset sampling capacitor is operatively connected to the switch. The switch connects the offset sampling capacitor to the input terminal of the amplifier during a charge transfer phase.

Abstract: An adaptable mixer device is operable in a first mode and a second mode and includes a first set of mixer units operable in the first mode and a second set of mixer units operable in the second mode. The second set of mixer units includes at least one mixer unit that is common to both the first set of mixer units and the second set of mixer units. The second set of mixer units also includes a plurality of mixer units that are not in the first set of mixer units. Similarly, the first set of mixer units including a plurality of mixer units that are not in the second set of mixer units.

Abstract: A return-type current-reuse mixer having a transconductance/amplification stage, a mixing stage, and a high-pass and a low-pass filter network. The transconductance/amplification stage has a current-reuse CMOS topology wherein an input frequency signal is converted into a frequency current, low-frequency components are removed from the frequency current by the high-pass filter network, the frequency current is fed into the mixing stage, modulation occurs in the mixing stage, and then an intermediate-frequency signal is generated and output. Once high-frequency components are removed from the intermediate-frequency signal by the low-pass filter network, the intermediate-frequency signal is sent again for input into the transconductance/amplification stage, then amplified in the transconductance/amplification stage and output. The mixer transconductance/amplification stage employs a current-reuse technique.

Abstract: It is described a switching device comprising a semiconductor switching unit; a contactor electrically coupled in series with the semiconductor switching unit; and a controller being configured for activating an electrically isolating state of the switching device and/or activating an electrically conducting state of the switching device based on a command signal or based on a comparison of a measured value and predetermined activation condition.

Abstract: A switching power capable of avoiding coupling effects is provided. The switching power comprises a driving loop. The driving loop comprises the substrate end and the gate end of a power Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) and a controlling gate, and the controlling gate is connected to the gate end of the power MOSFET and the substrate end of the power MOSFET is connected to the controlling gate. The switching power provided by the present can avoid the coupling effect of the driving loop and the power stage loop at the common source pin, thereby reducing the switching power losses and improving the efficiency of the switching power.

Abstract: The present invention discloses an analog switching circuit having a first terminal receiving an input signal, a second terminal providing an output signal and a control terminal receiving a switching control signal. The analog switching circuit has a first logic circuit providing a first control signal and a second control signal based on the switching control signal; an NMOS and a PMOS coupled between the first terminal and the second terminal, and controlled by the first control signal and the second control signal respectively; a first control circuit controls the backgate voltage of the NMOS based on the input signal and the switching control signal; and a second control circuit controls the backgate voltage of the PMOS based on the input signal and the switching control signal.

Abstract: An output circuit includes a current source and a first MOS transistor coupled in series between a power supply terminal and an output terminal. The first MOS transistor includes a backgate coupled to a drain of the second MOS transistor. The second MOS transistor includes a source coupled to a source of a third MOS transistor. The second MOS transistor includes a source coupled to backgates of the second and third MOS transistors. The backgates of the second and third MOS transistors are in a floating condition.

Abstract: A charge pump circuit (11) comprises a first stage (31) and at least a second stage (32), each having a capacitor (130, 230) and a current source (100, 200). The charge pump circuit (11) is configured such that, in a first phase (A) of operation, the capacitor (130) of the first stage (31) is switched in series to the current source (100) of the first stage (31) and the capacitor (230) of the second stage (32) is switched in series to the current source (200) of the second stage (32) and that, in a second phase (B) of operation, the capacitor (130) of the first stage (31) and the capacitor (230) of the second stage (32) are switched in series for providing a supply voltage (VHF) at an output (15) of the charge pump circuit (11). A comparator signal (SCOM) is generated by comparing a voltage at an electrode of one of the capacitors (130, 230) of the first and the at least second stage (31, 32) with a reference voltage (VR).

Abstract: An internal voltage generating circuit may include a first pull up resistor activated by a first range signal and connected between a pull up voltage terminal and a pull up common node; a second pull up resistor activated by a second range signal and connected between the pull up voltage terminal and the pull up common node; a first pull down resistor activated by the first range signal and connected between a pull down voltage terminal and a pull down common node; a second pull down resistor activated by the second range signal and connected between the pull down voltage terminal and the pull down common node; a resistor string including a plurality of series resistors connected between the pull up common node and the pull down common node; and a voltage selection circuit select voltage in response to voltage selection information.

Abstract: A reconfigurable integrated circuit (IC) has IC interface terminals including circuit input terminals and circuit output terminals. A bypass controller and bypass circuitry are coupled to each other, and to at least one of the circuit input terminals and at least one of the circuit output terminals. A processing circuit has multiple circuit modules coupled to the bypass circuitry. The processing circuit is coupled to at least one of the circuit input terminals and at least one of the circuit output terminals. In operation the bypass controller controls the bypass circuitry to selectively couple at least one pair of the IC interface terminals together, the pair including one of the circuit input terminals and one of the circuit output terminals. When the pair of IC interface terminals are coupled together, at least one of the circuit modules is selectively de-coupled from the pair of the IC terminals.

Abstract: Methods, systems, and computer readable media for low power multimode interconnect for lossy and tightly coupled multi-channel are disclosed. According to one aspect, a system for low power multimode interconnect includes a receiver for receiving a plurality of input signals that have been encoded by a multimode encoding equation to have voltage levels according to the multimode encoding equation and for decoding the received signals according to a multimode decoding equation to produce binary data as output, wherein the receiver includes a set of frequency-compensated amplifiers for emphasizing high-frequency components of the received input signals and a set of latches for receiving amplified signals from the frequency-compensated amplifiers and for decoding the amplified signals according to the multimode decoding equation to produce binary data as output.