Abstract: A thin film transistor array panel is provided that includes: a gate electrode that is disposed on an insulating substrate; a gate insulating layer that is disposed on the gate electrode; an oxide semiconductor that is disposed on the gate insulating layer; a blocking layer that is disposed on the oxide semiconductor; a source electrode and a drain electrode that are disposed on the blocking layer; a passivation layer that is disposed on the source electrode and drain electrode; and a pixel electrode that is disposed on the passivation layer. The blocking layer includes a first portion that is covered by the source electrode and drain electrode and a second portion that is not covered by the source electrode and drain electrode, and the first portion and the second portion include different materials.

Abstract: An interconnect sensor for detecting delamination due to coefficient of thermal expansion mismatch and/or mechanical stress. The sensor comprises a conductive path that includes a via disposed between two back end of line metal layers separated by a dielectric. The via is coupled between a first probe structure and a second probe structure and mechanically coupled to a stress inducing structure. The via is configured to alter the conductive path in response to mechanical stress caused by the stress inducing structure. The stress inducing structure can be a through silicon via or a solder ball. The dielectric material can be a low-k dielectric material. In another embodiment, a method of forming an interconnect sensor is provided for detecting delamination.

Abstract: Provided are a semiconductor package, a semiconductor memory module including the semiconductor package, and a system including the semiconductor memory module. The semiconductor package may include a plurality of main terminals arranged on a surface of the semiconductor package with constant intervals, and the plurality of main terminals may include terminals of a first set including a plurality of input/output terminals to which test signals may be input, and terminals of a second set including a plurality of input/output terminals to/from which signals other than the test signals may be input/output.

Abstract: A semiconductor apparatus includes first and second vias, a first circuit unit, a second circuit unit and a third circuit unit. The first and second vias electrically connect a first chip and a second chip with each other. The first circuit unit is disposed in the first chip, receives test data, and is connected with the first via. The second circuit unit is disposed in the first chip, and is connected with the second via and the first circuit unit. The third circuit unit is disposed in the second chip, and is connected with the first via. The first circuit unit outputs an output signal thereof to one of the first via and the second circuit unit in response to a first control signal.

Abstract: Testing of integrated circuits is achieved by a test architecture utilizing a scan frame input shift register, a scan frame output shift register, a test controller, and a test interface comprising a scan input, a scan clock, a test enable, and a scan output. Scan frames input to the scan frame input shift register contain a test stimulus data section and a test command section. Scan frames output from the scan frame output shift register contain a test response data section and, optionally, a section for outputting other data. The command section of the input scan frame controls the test architecture to execute a desired test operation.

Abstract: Provided are a thin film transistor (TFT) including a selectively crystallized channel layer, and a method of manufacturing the TFT. The TFT includes a gate, the channel layer, a source, and a drain. The channel layer is formed of an oxide semiconductor, and at least a portion of the channel layer contacting the source and the drain is crystallized. In the method of manufacturing the TFT, the channel layer is formed of an oxide semiconductor, and a metal component is injected into the channel layer so as to crystallize at least a portion of the channel layer contacting the source and the drain. The metal component can be injected into the channel layer by depositing and heat-treating a metal layer or by ion-implantation.

Abstract: To improve problems with on-state current and off-state current of thin film transistors, a thin film transistor includes a pair of impurity semiconductor layers to which an impurity element imparting one conductivity type is added, provided with a space therebetween; a conductive layer which is overlapped, over the gate insulating layer, with the gate electrode and one of the pair of impurity semiconductor layers to which an impurity element imparting one conductivity type is added; and an amorphous semiconductor layer which is provided successively between the pair of impurity semiconductor layers to which an impurity element imparting one conductivity type is added in such a manner that the amorphous semiconductor layer extends over the gate insulating layer from the conductive layer and is in contact with both of the pair of impurity semiconductor layers to which an impurity element imparting one conductivity type is added.

Abstract: A thin film transistor capable of reliably preventing the entry of light into an active layer, and a display including the thin film transistor are provided. A thin film transistor includes: a gate electrode; an active layer; and a gate insulating film arranged between the gate electrode and the active layer, the gate insulating film including a first insulating film, a first light-absorbing layer and a second insulating film, the first insulating film arranged in contact with the gate electrode, the first light-absorbing layer arranged in contact with the first insulating film and made of a material absorbing light of 420 nm or less, the second insulating film arranged between the first light-absorbing layer and the active layer.

Abstract: A backplane includes: a substrate, a pixel electrode, which includes a transparent conductive material, on the substrate, a capacitor first electrode formed on the same layer as the pixel electrode, a first protection layer covering the capacitor first electrode and an upper edge of the pixel electrode, a gate electrode of a thin film transistor (TFT) formed on the first protection layer, a capacitor second electrode formed on the same layer as the gate electrode, a first insulating layer that covers the gate electrode and the capacitor second electrode, a semiconductor layer that is formed on the first insulating layer and includes a transparent conductive material, a second insulating layer covering the semiconductor layer, source and drain electrodes of the TFT that are formed on the second insulating layer, and a third insulating layer that covers the source and drain electrodes and exposes the pixel electrode.

Abstract: A mask assembly includes a frame forming an opening, and a plurality of unit masks which form a plurality of deposition openings, the longitudinal ends of the unit masks being fixed to the frame. At least two adjacent ones of the plurality of unit masks have deposition recesses formed on both sides facing each other. The width of the deposition recesses along a width direction of the unit masks is equal to or greater than the width of the deposition openings along the width direction of the unit masks.

Abstract: According to an embodiment of the present invention, a thin film transistor array panel includes a gate line and a data line insulated from each other an insulating substrate where the gate line and the data line cross each other to define a pixel region, a thin film transistor (TFT) disposed at an intersection of the gate line and the data line, a floating electrode where at least a portion of the floating electrode overlaps the data line, and a pixel electrode disposed at the pixel region where the pixel electrode is connected to the TFT and overlaps the at least a portion of the floating electrode.

Abstract: The invention relates to a large area organic light emitting diode display having a uniformed luminescence throughout the display area. The invention suggests an organic light emitting diode display comprising a thin film transistor substrate including a thin film transistor, a driving current line to supply an electric signal to the thin film transistor, a driving line contact hole to expose some portions of the driving current line, and an organic light emitting diode connected to the thin film transistor; a cap including a cap substrate and an auxiliary electrode disposed on a surface of the cap substrate with an area that is at least ? of an area of the cap substrate; a conductive sealing material to electrically connect the auxiliary electrode and the driving current line through the driving line contact hole; and an organic adhesive joining the thin film transistor substrate and the cap.

Abstract: According to one embodiment, a semiconductor light emitting device includes a substrate, a first electrode, a first conductivity type layer, a light emitting layer, a second conductivity type layer and a second electrode. The first conductivity type layer includes a first contact layer, a window layer having a lower impurity concentration than the first contact layer and a first cladding layer. The second conductivity type layer includes a second cladding layer, a current spreading layer and a second contact layer. The second electrode includes a narrow-line region on the second contact layer and a pad region electrically connected to the narrow-line region. Band gap energies of the first contact and window layers are larger than that of the light emitting layer. The first contact layer is provided selectively between the window layer and the first electrode and without overlapping the second contact layer as viewed from above.

Abstract: A high quality single crystal wafer of SiC is disclosed having a diameter of at least about 100 mm and a micropipe density of less than about 25 cm?2.

Abstract: A process is described for producing silicon carbide crystals having increased minority carrier lifetimes. The process includes the steps of heating and slowly cooling a silicon carbide crystal having a first concentration of minority carrier recombination centers such that the resultant concentration of minority carrier recombination centers is lower than the first concentration.

Abstract: The present disclosure, which is directed to ultra-thin-body-and-BOX and Double BOX fully depleted SOI devices having an epitaxial diffusion-retarding semiconductor layer that slows dopant diffusion into the SOI channel, and a method of making these devices. Dopant concentrations in the SOI channels of the devices of the present disclosure having an epitaxial diffusion-retarding semiconductor layer between the substrate and SOI channel are approximately 50 times less than the dopant concentrations measured in SOI channels of devices without the epitaxial diffusion-retarding semiconductor layer.

Abstract: The silicon carbide semiconductor device includes a substrate, a drift layer, a base region, a source region, a trench, a gate insulating layer, a gate electrode, a source electrode, a drain electrode, and a deep layer. The deep layer is disposed under the base region and is located to a depth deeper than the trench. The deep layer is divided into a plurality of portions in a direction that crosses a longitudinal direction of the trench. The portions include a group of portions disposed at positions corresponding to the trench and arranged at equal intervals in the longitudinal direction of the trench. The group of portions surrounds corners of a bottom of the trench.

Abstract: An integrated circuit device and method for manufacturing the same are disclosed. An exemplary device includes a semiconductor substrate having a substrate surface and a trench isolation structure disposed in the semiconductor substrate for isolating an NMOS region of the device and from a PMOS region of the device. The device further includes a first fin structure comprising silicon or SiGe disposed over a layer of III-V semiconductor material having a high band gap energy and a lattice constant greater than that of Ge; a second fin structure comprising silicon or SiGe disposed over a layer of III-V semiconductor material having a high band gap energy and a lattice constant smaller than that of Ge; and a gate structure disposed over and arranged perpendicular to the first and second fin structures.

Abstract: A wide-band-gap reverse-blocking MOS-type semiconductor device includes a SiC n?-type drift layer; a p+-type substrate on the first major surface side of the drift layer; a trench extending through a p+-type substrate into the drift layer; a titanium electrode in the trench bottom that forms a Schottky junction with the SiC n?-type drift layer; an active section including a MOS-gate structure on the second major surface side of the drift layer facing to the area, in which the Schottky junctions are formed; a breakdown withstanding section surrounding the active section; and a trench isolation layer surrounding the breakdown withstanding section, the trench isolation layer extending from the second major surface of the drift layer into p+-type substrate and including insulator film buried therein. The device facilitates making a high current flow with a low ON-voltage and exhibits a very reliable reverse blocking capability.

Abstract: Disclosed are a light emitting device package and a light emitting apparatus. The light emitting device package comprises a package body comprising a light emitting surface inclined at an oblique angle with respect to a bottom surface, a plurality of lead electrodes in the package body, and at least one light emitting device electrically connected to the lead electrodes.

Abstract: An organic electroluminescent (EL) display includes a plurality of organic EL devices for red, green, and blue subpixels, each including a first electrode on a light output side, a second electrode opposite the first electrode, and an organic compound layer including a light-emitting layer therebetween. The organic EL devices have a resonator structure between a first reflective surface closer to the first electrode than the organic compound layer and a second reflective surface closer to the second electrode than the organic compound layer. A predetermined white color is displayed by mixing the three colors such that an optical distance of the organic EL devices of each color between an emission position in the light-emitting layer and the second reflective surface is set within ±10% from an optical distance corresponding to an nth-order minimum of a curve of required current density against at least the optical distance.

Abstract: A light emitting device includes a substrate having a surface region and a light emitting diode overlying the surface region. The light emitting diode is fabricated on a semipolar or nonpolar GaN containing substrate and emits electromagnetic radiation of a first wavelength. The diode includes a quantum well region characterized by an electron wave function and a hole wave function. The electron wave function and the hole wave function are substantially overlapped within a predetermined spatial region of the quantum well region. The device has a transparent phosphor overlying the light emitting diode. The phosphor is excited by the substantially polarized emission to emit electromagnetic radiation of a second wavelength.

Abstract: A method comprising depositing an ink comprising a nanomaterial and a liquid vehicle from a micro-dispenser onto a layer of a device is disclosed. A method comprising depositing an ink comprising a nanomaterial and a liquid vehicle from a micro-dispenser onto a material capable of transporting charge in a predetermined arrangement is also disclosed. Methods for fabricating devices including nanomaterials are also disclosed. In certain preferred embodiments, the nanomaterial comprises semiconductor nanocrystals. In certain preferred embodiments, a micro-dispenser comprises an inkjet printhead.

Abstract: A light emitting device includes: a multilayer body including a light emitting layer made of a semiconductor; a first bonding metal layer attached to the multilayer body; a substrate; and a second bonding metal layer attached to the substrate and bonded to the first bonding metal layer at a bonding interface, at least one of a planar size of the first bonding metal layer on the bonding interface side and a planar size of the second bonding metal layer on the bonding interface side being smaller than a planar size of the substrate.

Abstract: A light emitting device including a light emitting structure including a first conductive type semiconductor layer, an active layer, and a second conductive type semiconductor layer; a first photonic crystal structure on the light emitting structure; a lower encapsulant on the first photonic crystal structure; and a second photonic crystal structure on the lower encapsulant.

Abstract: The present disclosure relates to high efficiency light emitting diode devices and methods for fabricating the same. In accordance with one or more embodiments, a light emitting diode device includes a substrate having one or more recessed features formed on a surface thereof and one or more omni-directional reflectors formed to overlie the one or more recessed features. A light emitting diode layer is formed on the surface of the substrate to overlie the omni-directional reflector. The one or more omni-directional reflectors are adapted to efficiently reflect light.

Abstract: Provided is a high-efficiency light emitting diode (LED) that includes: a support substrate; a semiconductor stack positioned on the support substrate, the semiconductor stack including a p-type compound semiconductor layer, an active layer, and an n-type compound semiconductor layer; a first electrode positioned between the support substrate and the semiconductor stack and in ohmic contact with the semiconductor stack; a first bonding pad positioned on a portion of the first electrode that is exposed outside of the semiconductor stack; and a second electrode positioned on the semiconductor stack. Protrusions are formed on exposed surfaces of the semiconductor stack. In addition, the second electrode may be positioned between the first electrode and the support substrate and contacted with the n-type compound semiconductor layer through openings of the semiconductor stack.

Abstract: Provided is a light emitting device. In one embodiment, a light emitting device includes: a substrate including ?-Ga203; a light emitting structure on the substrate, the light emitting structure including a first conductive type semiconductor layer, an active layer, and a second conductive type semiconductor layer; an electrode on the light emitting structure; and a porous layer at a lateral surface region of the substrate.

Abstract: In a method for manufacturing a light-emitting device according to an embodiment of the present invention, one surface of a first substrate including a reflective layer including an opening, a light absorption layer formed over the reflective layer to cover the opening in the reflective layer, a protective layer formed over the light absorption layer and including a groove at a position overlapped with the opening in the reflective layer, and a material layer formed over the protective layer and a deposition surface of a second substrate are disposed to face each other and light irradiation is performed from the other surface side of the first substrate, so that an EL layer is formed in a region on the deposition surface of the second substrate, which is overlapped with the opening in the reflective layer.

Abstract: Light emitting structures are disclosed that can include a semiconductor light emitting diode (LED) that includes a p-n junction active layer. A first layer can include a binder material having a thickness that is less than about 1000 ?m, wherein the first layer is directly on the LED. A second layer can include phosphor particles, where the second layer can have a thickness that is less than about 1000 ?m and can be directly on the first layer so that the first layer is between the LED and the second layer.

Abstract: A light emitting diode (LED) light engine includes a solid transparent dome mounted on one or more LED dies to form a base module, a flexible sheath having embedded therein a phosphor that converts light of a first wavelength range to light of a second wavelength range, the sheath being attached to the base module so that the sheath conforms to a light emitting surface of the dome. The sheath emits light of the second wavelength range when the LED is emitting light of the first wavelength range. Further sheaths may be formed each with different phosphors or phosphor blends, and one of the sheaths may be selected to cover the base module depending on the color of light to be produced by the light engine.

Abstract: Disclosed are a semiconductor light emitting device. The semiconductor light emitting device comprises a light emitting structure including a first conductive semiconductor layer, a second conductive semiconductor layer, and an active; an electrode on a first region of the first conductive semiconductor layer; a conductive support member under the light emitting structure; a metal layer between the light emitting structure and the conductive support member; and a reflective layer between the metal layer and the light emitting structure, wherein the metal layer is physically contacted with a lower surface of the reflective layer, wherein the reflective layer includes a first layer and a second layer, wherein the first layer has a different material from the second layer, wherein the metal layer has a protrusion, wherein the first conductive semiconductor layer includes a roughness.

Abstract: A light-emitting device is disclosed. The light-emitting device comprises a substrate, an ion implanted layer on the substrate, a light-emitting stack layer disposed on the ion implanted layer, and an adhesive layer connecting the substrate with the light-emitting stack layer, wherein the adhesive layer comprises a thin silicon film disposed between the ion implanted layer and the light-emitting layer. This invention also discloses a method of manufacturing a light-emitting device comprising the steps of forming a light-emitting stack layer, forming a thin silicon film on the light-emitting stack layer, providing a substrate, forming an ion implanted layer on the substrate, and providing an electrode potential difference to form an oxide layer between the thin silicon film and the ion implanted layer.

Abstract: A layered substrate includes a first substrate including an upper surface, a lower surface, a peripheral surface between peripheral edges of the upper surface and the lower surface, and a cut portion cut into the peripheral surface and passing through the upper surface and the lower surface, and a second substrate including an upper surface, a lower surface, and a peripheral surface between peripheral edges of the upper surface and the lower surface, and the lower surface of the second substrate layered on the upper surface of the first substrate and closing the cut portion of the first substrate from above. The second substrate includes a heat conductor that is thermally connected to an element to be mounted on the upper surface of the second substrate, the heat conductor configured to thermally extend to the cut portion of the first substrate.

Abstract: The present invention provides a light-emitting element having a structure in which the drive voltage is comparatively low and a light-emitting element in which the increase in the drive voltage over time is small. Further, the present invention provides a display device in which the drive voltage and the increase in the drive voltage over time are small and which can resist long-term use. A layer in contact with an electrode in a light-emitting element is a layer containing a P-type semiconductor or a hole-generating layer such as an organic compound layer containing a material having electron-accepting properties. The light-emitting layer is sandwiched between the hole-generating layers, and an electron-generating layer is sandwiched between the light-emitting layer and the hole-generating layer on a cathode side.

Abstract: The invention is applicable for use in conjunction with a light-emitting semiconductor structure that includes a semiconductor active region of a first conductivity type containing a quantum size region and having a first surface adjacent a semiconductor input region of a second conductivity type that is operative, upon application of electrical potentials with respect to the active and input regions, to produce light emission from the active region. A method is provided that includes the following steps: providing a semiconductor output region that includes a semiconductor auxiliary layer of the first conductivity type adjacent a second surface, which opposes the first surface of the active region, and providing the auxiliary layer as a semiconductor material having a diffusion length for minority carriers of the first conductivity type material that is substantially shorter than the diffusion length for minority carriers of the semiconductor material of the active region.

Abstract: A semiconductor device includes a semiconductor body with a base layer and a field shaping zone of a first conductivity type. The base layer extends parallel to a back surface of the semiconductor body in a central portion and into an edge portion that surrounds the central portion. The field shaping zone is formed in the edge portion and has a maximum dopant concentration exceeding at least three times a maximum dopant concentration in the base layer. A back side metal structure directly adjoins the back surface in the central portion and extends over the edge portion. A dielectric structure is between the back side metal structure and the field shaping zone. Leakage current mechanisms reducing the reverse blocking capabilities are reduced.

Abstract: An n-type GaN layer (3), a GaN layer (7) formed over the n-type GaN layer (3), an n-type AlGaN layer (9) formed over the GaN layer (7), a gate electrode (15) and a source electrode (13) formed over the n-type AlGaN layer (9), a drain electrode (14) formed below the n-type GaN layer (3), and a p-type GaN layer (4) formed between the GaN layer (7) and the drain electrode (14) are provided.

Abstract: A field effect transistor includes a nitride-based semiconductor multi-layer structure, a source electrode (108), a drain electrode (109), a protective film (110), and a gate electrode (112) that is provided in a recess structure, which is formed by etching, directly or with a gate insulating film interposed therebetween. The nitride-based semiconductor multi-layer structure includes at least a base layer (103) made of AlXGa1-XN (0?1), a channel layer (104) made of GaN or InGaN, a first electron supply layer (105), which is an undoped or n-type AlYGa1-YN layer, a threshold value control layer (106), which is an undoped AlZGa1-ZN layer, and a second electron supply layer (107), which is an undoped or n-type AlWGa1-WN layer, epitaxially grown in this order on a substrate (101) with a buffer layer (102) interposed therebetween. The Al composition of each layer in the nitride-based semiconductor multi-layer structure satisfies 0<X?Y?1 and 0<Z?Y?1.

Abstract: To provide a circuit layout design method that can prevent degradation of the circuit reliability even in highly miniaturized circuit cells. In order to prevent noise from a power supply potential or a reference potential with a large potential difference from affecting a gate electrode and causing a malfunction, a first plug connected to the gate electrode and a second plug to which the power supply potential or the reference potential is supplied are required to be spaced from each other by a distance sufficient for the noise from the power supply potential or the reference potential not to affect the first plug. To this end, among the second plugs placed at equal intervals under the wiring, only the second plug placed at a layout position that is not sufficiently spaced from the first plug is deleted at the time of planar layout design.

Abstract: An integrated circuit chip includes a semiconductor substrate, a first circuit in or coupled to the semiconductor substrate, a second circuit device in or coupled the semiconductor substrate, a dielectric structure coupled the semiconductor substrate, a first interconnecting structure in the dielectric structure, a first pad connected to the first node of the voltage regulator through the first interconnecting structure, a second interconnecting structure in the dielectric structure, a second pad connected to the first node of the analog circuit through the second interconnecting structure, a passivation layer coupled the dielectric structure, wherein multiple openings in the passivation layer exposes the first and second pads, and a third interconnecting structure coupled the passivation layer and coupled the first and second pads.

Abstract: A field effect transistor device includes: a reservoir bifurcated by a membrane of three layers: two electrically insulating layers; and an electrically conductive gate between the two insulating layers. The gate has a surface charge polarity different from at least one of the insulating layers. A nanochannel runs through the membrane, connecting both parts of the reservoir. The device further includes: an ionic solution filling the reservoir and the nanochannel; a drain electrode; a source electrode; and voltages applied to the electrodes (a voltage between the source and drain electrodes and a voltage on the gate) for turning on an ionic current through the ionic channel wherein the voltage on the gate gates the transportation of ions through the ionic channel.

Abstract: Elements of an edge termination structure, such as multiple concentric guard rings, are effectively doped regions in a drift layer. To increase the depth of these doped regions, individual recesses may be formed in a surface of the drift layer where the elements of the edge termination structure are to be formed. Once the recesses are formed in the drift layer, these areas about and at the bottom of the recesses are doped to form the respective edge termination elements.

Abstract: The disclosure relates generally to junction gate field effect transistor (JFET) structures and methods of forming the same. The JFET structure includes a p-type substrate having a p-region therein; an n-channel thereunder; and n-doped enhancement regions within the n-channel, each n-doped enhancement region separated from the p-region.

Abstract: An ESD protection element is formed by a PN junction diode including an N+ type buried layer having a proper impurity concentration and a first P+ type buried layer and a parasitic PNP bipolar transistor which uses a second P+ type buried layer connected to a P+ type diffusion layer as the emitter, an N? type epitaxial layer as the base, and the first P+ type buried layer as the collector. The first P+ type buried layer is connected to an anode electrode, and the P+ type diffusion layer and an N+ type diffusion layer surrounding the P+ type diffusion layer are connected to a cathode electrode. When a large positive static electricity is applied to the cathode electrode, and the parasitic PNP bipolar transistor turns on to flow a large discharge current.

Abstract: A semiconductor apparatus according to embodiments of the invention can include a first semiconductor device made of silicon, the first semiconductor devices being arranged collectively, whereby to form a first device group, and a second semiconductor device made of silicon carbide, the second semiconductor devices being arranged collectively, whereby to form a second device group. The apparatus can also include a wiring conductor connecting the first semiconductor device and the second semiconductor device, a cooling fin base comprising a projection formed thereon, whereby to dissipate heat generated from the first and second semiconductor devices, and the projections arranged under the second device group being spaced apart from each other more widely than the projections arranged under the first device group.

Abstract: An object is to provide a memory device which does not need a complex manufacturing process and whose power consumption can be suppressed, and a semiconductor device including the memory device. A solution is to provide a capacitor which holds data and a switching element which controls storing and releasing charge in the capacitor in a memory element. In the memory element, a phase-inversion element such as an inverter or a clocked inverter includes the phase of an input signal is inverted and the signal is output. For the switching element, a transistor including an oxide semiconductor in a channel formation region is used. In the case where application of a power supply voltage to the phase-inversion element is stopped, the data is stored in the capacitor, so that the data is held in the capacitor even when the application of the power supply voltage to the phase-inversion element is stopped.

Abstract: An electronic device employing a graphene layer as a charge carrier layer. The graphene layer is sandwiched between layers that are constructed of a material having a highly ordered crystalline structure and a high dielectric constant. The highly ordered crystalline structure of the layers surrounding the graphene layer has low density of charged defects that can lead to scattering of charge carriers in the graphene layer. The high dielectric constant of the layers surrounding the graphene layer also prevents charge carrier scattering by minimizing interaction between the charge carriers and the changed defects in the surrounding layers. An interracial layer constructed of a thin, non-polar, dielectric material can also be provided between the graphene layer and each of the highly ordered crystalline high dielectric constant layers to minimize charge carrier scattering in the graphene layer through remote interfacial phonons.

Abstract: A method of preventing blooming in a pixel array includes affecting an amount of light that impinges on a photoelectric conversion element by adjusting a transmissivity of an electrochromic element based on an output of the photoelectric conversion element.

Abstract: A solid-state imaging device in which the potential of a signal line, which is obtained before a pixel has an operating period, is fixed to an intermediate potential between a first power-supply potential and a second power-supply potential.