Abstract: A passive interposer apparatus with a shielded through silicon via (TSV) configuration is disclosed. The apparatus includes a p-doped substrate, wherein at least an upper portion of the p-doped substrate is heavily p-doped. An interlayer dielectric layer (ILD) is disposed over the upper portion of the p-doped substrate. A plurality of through silicon vias (TSVs) are formed through the ILD and the p-doped substrate. A plurality of shielding lines disposed between the TSVs electrically couple respective second metal contact pads to the upper portion of the p-doped substrate.

Abstract: A semiconductor package and a method for fabricating the same are provided. A leadframe including a die pad and a plurality of peripheral leads is provided. A carrier, having a plurality of connecting pads formed thereon, is attached to the die pad, wherein a planar size of the carrier is greater than that of the die pad, allowing the connecting pads on the carrier to be exposed from the die pad. At least a semiconductor chip is attached to a side of an assembly including the die pad and the carrier, and is electrically connected to the connecting pads of the carrier and the leads via bonding wires. A package encapsulant encapsulates the semiconductor chip, the bonding wires, a part of the carrier and a part of the leadframe, allowing a bottom surface of the carrier and a part of the leads to be exposed from the package encapsulant.

Abstract: In a non-leaded type semiconductor device, a tab, tab suspension leads, and other leads are exposed to one surface of a seal member. A semiconductor element is positioned within the seal member and fixed to a surface of the tab with an adhesive. The tab is formed larger than the semiconductor element so that outer peripheral edges of the tab are positioned outside outer peripheral edges of the semiconductor element. A groove is formed in the tab surface portion positioned between the area to which the semiconductor element is fixed and wire connection areas to which the wires are connected, the groove being formed so as to surround the semiconductor element fixing area, thereby preventing peeling-off between the tab to which the semiconductor element is fixed and the resin which constitutes the package.

Abstract: A lead frame includes a first outer lead portion and a second outer lead portion which is arranged to oppose to the first outer lead portion with an element-mounting region between them. An inner lead portion has first inner leads connected to the first outer leads and second inner leads connected to the second outer leads. At least either the first or second inner leads are routed in the element-mounting region. An insulation resin is filled in the gaps between the inner leads located on the element-mounting region. A semiconductor device is configured with semiconductor elements mounted on both the top and bottom surfaces of the lead frame.

Abstract: An electronic device and manufacturing thereof. One embodiment provides a semiconductor chip having a control electrode and a first load electrode on a first surface and a second load electrode on a second surface. A first lead is electrically coupled to the control electrode. A second lead is electrically coupled to the first load electrode. A third lead is electrically coupled to the first load electrode, the third lead being separate from the second lead. A fourth lead is electrically coupled to the second load electrode, the second and third leads being arranged between the first and fourth leads.

Abstract: A package process is provided. An adhesive layer is disposed on a carrier board and then plural first semiconductor devices are disposed on the adhesive layer. A first molding compound formed on the carrier board covers the sidewalls of the first semiconductor devices and fills the gaps between the first semiconductor devices so as to form a chip array board constructed by the first semiconductor devices and the first molding compound. Next, plural second semiconductor devices are flip-chip bonded to the first semiconductor devices respectively. Then, a second molding compound formed on the chip array board at least covers the sidewalls of the second semiconductor devices and fills the gaps between the second semiconductor devices. Subsequently, the chip array board is separated from the adhesive layer. Then, the first and the second molding compound are cut along the gaps between the second semiconductor devices.

Abstract: A layered chip package includes a main body. The main body includes a main part, and further includes first terminals and second terminals disposed on the top and bottom surfaces of the main part, respectively. The main part includes first and second layer portions, and through electrodes penetrating them. The through electrodes are electrically connected to the first and second terminals. Each of the layer portions includes a semiconductor chip having a first surface and a second surface opposite thereto, and further includes surface electrodes. The surface electrodes are disposed on a side of the semiconductor chip opposite to the second surface. The first and second layer portions are bonded to each other such that the respective second surfaces face each other. The first terminals are formed by using the surface electrodes of the first layer portion. The second terminals are formed by using the surface electrodes of the second layer portion.

Abstract: System and method for thermal management in a multi-chip packaged device. A microelectronic unit is disclosed, and includes a semiconductor element having a top surface and a bottom surface remote from the top surface. A semiconductor device including active elements is located adjacent to the top surface. Operation of the semiconductor device generates heat. Additionally, one or more first blind vias extend from the bottom surface and partially into a thickness of the semiconductor element. In that manner, the blind via does not contact or extend to the semiconductor device (defined as active regions of the semiconductor element, and moreover, is electrically isolated from the semiconductor device. A thermally conductive material fills the one or more first blind vias for heat dissipation.

Abstract: A cavity wafer for flip chip stacking includes an electrostatic (ESC) chuck wafer with a plurality of cavities, and a bonding layer on a surface of the ESC chuck wafer. The bonding layer is configured to receive a through-silicon-via (TSV) interposer with solder bumps. The plurality of cavities are configured to receive the solder bumps at the TSV interposer. The bonding layer is configured to receive an electrostatic bias for bonding the ESC chuck wafer to the TSV interposer with the solder bumps.

Abstract: A package for at least one semiconductor device and a method for making the package. At least one dielectric layer is selectively printed on at least a portion of the semiconductor device creating first recesses aligned with a plurality of the electrical terminals. A conductive material is printed in the first recesses forming contact members on the semiconductor device. At least one dielectric layer is selectively printed on at least a portion of the package to create a plurality of second recesses corresponding to a target circuit geometry. A conductive material is printed in at least a portion of the second recesses to create a circuit geometry. The circuit geometry includes a plurality of exposed terminals electrically coupled to the electric terminals on the semiconductor device.

Abstract: In accordance with one or more embodiments, a flange package comprises a flange and an interposer having two or more fingers disposed in an interposer trench. The flange has a mold lock formed about a periphery of the interposer trench. A dielectric ring comprising a dielectric material is formed in the interposer trench, and in and around the periphery of the mold lock. A semiconductor die is disposed within the dielectric ring having gate pads and source pads formed on a first side, and having drain pads disposed on a second side of the die. The gate pads are coupled to the interposer and the source pads are coupled to the flange. A gate lead is coupled to the interposer and a drain lead is coupled to the drain pads. Other embodiments are disclosed.

Abstract: An interposer having decaps formed in blind-vias, a packaged semiconductor structure having decaps formed in blind-vias, and methods for forming the same are provided. In one embodiment, an interposer is provided that includes an interconnect layer disposed on a substrate. A plurality of through-vias are formed through the substrate in an isolated region of the substrate. At least one of the plurality of conductive vias are electrically coupled to at least one of a plurality of top wires formed in the interconnect layer. A plurality of blind-vias are formed through the substrate in a dense region of the substrate during a common etching step with the through-vias. At least one blind-via includes (a) a dielectric material lining the blind-vias, and (b) a conductive material filling the lined blind-vias and forming a decoupling capacitor.

Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include attaching a die to a carrier material, wherein the carrier material comprises a top layer and a bottom layer separated by an etch stop layer; forming a dielectric material adjacent the die, forming a coreless substrate by building up layers on the dielectric material, and then removing the top layer carrier material and etch stop layer from the bottom layer carrier material.

Abstract: An integrated circuit package system includes: providing a singulated, layered structure equivalent in size to an integrated circuit die and having an adhesive layer, an electrical insulator layer, and a heat slug; attaching the integrated circuit die to a base; attaching bond wires to a top of the base for electrical connection between the integrated circuit die and the base; attaching the singulated, layered structure to the integrated circuit die wherein the bond wires are surrounded by the adhesive layer; and encapsulating the integrated circuit die and a portion of the heat slug with a molding compound.

Abstract: Embodiments of the present disclosure provide a method that comprises providing a first die having a surface comprising a bond pad to route electrical signals of the first die and attaching the first die to a layer of a substrate. The method further comprises forming one or more additional layers of the substrate to embed the first die in the substrate and coupling a second die to the one or more additional layers, the second die having a surface comprising a bond pad to route electrical signals of the second die. The second die is coupled to the one or more additional layers such that electrical signals are routed between the first die and the second die.

Abstract: A carrier-free semiconductor package includes a circuit structure having an insulating layer and a circuit layer embedded in the insulating layer and having a plurality of conductive traces and RF (radio frequency) traces, a chip disposed on a first surface of the insulating layer and electrically connected to the conductive traces, an encapsulant covering the chip and the circuit layer, a ground layer formed on a second surface of the insulating layer opposite to the first surface, and a plurality of solder balls disposed on the conductive traces or terminals on the conductive traces, wherein portions of the solder balls electrically connect the ground layer so as to allow the RF traces and the ground layer to form a microstrip line having an RF function, thus obtaining a single-layer carrier-free semiconductor package having low cost and simplified RF design.

Abstract: A flexible semiconductor package apparatus having a responsive bendable conductive wire member is presented. The apparatus includes a flexible substrate, semiconductor chips, and conductive wires. The semiconductor chips are disposed on the flexible substrate and spaced apart from each other on the flexible substrate. Each semiconductor chip has bonding pads. The conductive wires are electrically connected to the bonding pads of the semiconductor chip. Each conductive wire has at least one elastic portion. One preferred configuration is that part of the conductive wire is wound to form a coil spring shape so that the coil spring shape of the conductive wire aid in preventing the conductive wire from being separated from the corresponding bonding pad of the semiconductor chip when the flexible substrate on which the semiconductor chips are mounted are bent, expanded or twisted.

Abstract: A semiconductor device includes a semiconductor chip of a multilayer wiring structure having an insulating film formed on a surface thereof, multiple electrode pads formed at a central part and an outer peripheral part of the insulating film, and multiple protective metal layers formed respectively on the electrode pads. The semiconductor device also includes a substrate having the semiconductor chip mounted thereon and including multiple substrate terminals formed on a surface thereof respectively in positions corresponding to the electrode pads. The semiconductor chip is mounted on the substrate by connecting a stud bump to a solder bump. The stud bump is formed on any one of each of the protective metal layers and each of the substrate terminals and the solder bump is formed on the other one of each of the protective metal layers and each of the substrate terminals.

Abstract: A semiconductor device and a fabrication method thereof are provided. An electrically conductive elastic member is formed on a semiconductor die, and a conductive bump is formed on the elastic member. Accordingly, since the conductive bump is formed on the elastic member, or to protrude from a top surface of the elastic member, the height and thus diameter of the conductive bump is reduced allowing a fine pitch to be realized. Further, the elastic member is elastic and thus mitigates external impacts from being transferred from the conductive bump to the semiconductor die.

Abstract: A microelectronic assembly includes a substrate having a first surface and a second surface remote from the first surface. A microelectronic element overlies the first surface and first electrically conductive elements are exposed at one of the first surface and the second surface. Some of the first conductive elements are electrically connected to the microelectronic element. Wire bonds have bases joined to the conductive elements and end surfaces remote from the substrate and the bases, each wire bond defining an edge surface extending between the base and the end surface. An encapsulation layer extends from the first surface and fills spaces between the wire bonds such that the wire bonds are separated by the encapsulation layer. Unencapsulated portions of the wire bonds are defined by at least portions of the end surfaces of the wire bonds that are uncovered by the encapsulation layer.

Abstract: An integrated circuit device including a substrate, a first internal bonding pad, a second internal bonding pad, an external bonding pad and a bonding wire is provided. A first circuit, a second circuit, at least one interconnect line and an electrostatic discharge protection circuit are embedded in the substrate. The first internal bonding pad is disposed on a surface of the substrate and electrically connected to the first circuit. The second internal bonding pad is disposed on the surface of the substrate and electrically connected to the second circuit. The first internal bonding pad is electrically connected to the second internal bonding pad via the bonding wire. The first internal bonding pad is electrically connected to the electrostatic discharge protection circuit via the interconnect line. The electrostatic discharge protection circuit is electrically connected to the external bonding pad which is used for electrically connecting an external package lead.

Abstract: A semiconductor die includes a substrate including a topside including circuit elements configured to provide a circuit function. The die includes at least one multi-layer structure including a first material having a first CTE, a second material including a metal having a second CTE, wherein the second CTE is higher than the first CTE. A coefficient of thermal expansion (CTE) graded layer includes at least a dielectric portion that is between the first material and the second material having a first side facing the first material and a second side facing the second material. The CTE graded layer includes a non-constant composition profile across its thickness that provides a graded CTE which increases in CTE from the first side to the second side. The multi-layer structure can be a through-substrate-vias (TSV) that extends through the thickness of the substrate.

Abstract: Metal nitride coatings containing carbon can be either electrically conductive or substantially non-conductive depending on the degree to which they have been exposed to an oxidative environment. Substantially non-conductive metal nitride coatings can be used as protective layers in electrical devices. Particularly in an electrical device containing carbon nanomaterials, the metal nitride coatings can be used to mask the device's operational characteristics. Such devices can contain an electrical interconnect containing a carbon nanomaterial and a substantially non-conductive coating on the carbon nanomaterial. The substantially non-conductive coating can contain at least one substantially non-conductive metal nitride layer and at least some carbon. Methods for making such devices and metal nitride coatings are also described herein.

Abstract: The present invention provides a method of fabricating an interconnect structure in which a patternable low-k material replaces the need for utilizing a separate photoresist and a dielectric material. Specifically, this invention relates to a simplified method of fabricating single-damascene and dual-damascene low-k interconnect structures with at least one patternable low-k dielectric and at least one inorganic antireflective coating. In general terms, a method is provided that includes providing at least one patternable low-k material on a surface of an inorganic antireflective coating that is located atop a substrate, said inorganic antireflective coating is vapor deposited and comprises atoms of M, C and H wherein M is at least one of Si, Ge, B, Sn, Fe, Ta, Ti, Ni, Hf and La; forming at least one interconnect pattern within the at least one patternable low-k material; and curing the at least one patternable low-k material.

Abstract: A semiconductor package includes a chip, a carrier, a bonding wire and a molding compound. The chip includes a pad. The carrier includes a finger and has an upper surface and a lower surface opposite to the upper surface, wherein the upper surface supports the chip. The bonding wire is extended from the finger to the pad for electrically connecting the chip to the carrier, wherein the bonding wire defines a projection portion on the upper surface of the carrier, a straight line is defined to pass through the finger and pad, there is a predetermined angle between the tangent line of the projection portion at the finger and the straight line. The molding compound seals the chip and the bonding wire, and covers the carrier.

Abstract: According to one embodiment, a semiconductor device having a pattern layout includes a first interconnect pattern and a contact pad. The first interconnect pattern includes lines and spaces which are alternately aligned in a first direction with a predetermined pitch. The contact pad is arranged between the lines in the first interconnect pattern and has a width that is triple the predetermined pitch. An interval between the line in the first interconnect pattern and the contact pad is the predetermined pitch, and the predetermined pitch is 100 nm or below.

Abstract: A semiconductor device includes a semiconductor substrate, electrodes separated from each other and extending from a first main surface in the direction of depth of the semiconductor substrate, and an interconnect portion coupling the electrodes to each other and extending from the first main surface in the direction of depth of the semiconductor substrate without passing through the semiconductor substrate. One of the electrodes is a through electrode passing through the semiconductor substrate to reach a second main surface. For semiconductor devices having through electrodes and vertically stacked on each other, the interconnect portion serves to enhance the degree of design freedom.

Abstract: A bump electrode, a dummy bump, and a heat-resistant polymer film, whose upper-surface heights are uniformed, are formed on each of a first silicon substrate and a second silicon substrate, and then, the first silicon substrate and the second silicon substrate are bonded to each other so that the bump electrodes formed on the respective substrates are electrically connected to each other. At this time, the dummy bump is arranged so as to be bonded to the heat-resistant polymer film on the silicon substrate opposed thereto, so that a semiconductor device having both of good electrical connection between the bump electrodes and bump protection performance obtained by a polymer film with high heat resistance and without voids can be achieved.

Abstract: System and method for reducing contact resistance and improving barrier properties is provided. An embodiment comprises a dielectric layer and contacts extending through the dielectric layer to connect to conductive regions. A contact barrier layer is formed between the conductive regions and the contacts by electroless plating the conductive regions after openings have been formed through the dielectric layer for the contact. The contact barrier layer is then treated to fill the grain boundary of the contact barrier layer, thereby improving the contact resistance. In another embodiment, the contact barrier layer is formed on the conductive regions by electroless plating prior to the formation of the dielectric layer.

Abstract: A combination substrate includes a first substrate having multiple wiring board mounting pads for installing a printed wiring board and multiple connection pads on the opposite side of the wiring board mounting pads, a second substrate having multiple package substrate mounting pads for loading one or more package substrates and multiple connection pads on the opposite side of the package substrate mounting pads, a resin component filling a space between the first substrate and the second substrate, and multiple component loading pads positioned to load an electronic component between the first substrate and the second substrate and formed on one of the first substrate and the second substrate. The connection pads of the second substrate are electrically connected to the connection pads of the first substrate.

Abstract: A system and method prevent corrosive elements (or at least the oxidizing agent) from making contact with metal connections at the interface between two layers of a stacked IC device. When layers are positioned in proximity to each other, a cavity is formed at the boundary of the planar surfaces of the layers. This cavity is bounded by a peripheral seal between the layers. In one embodiment, a vacuum is created within the cavity thereby reducing the corrosive atmosphere within the cavity. In another embodiment, the cavity is filled with an inert gas, such as argon. Once the cavity has oxidizing elements reduced, the peripheral seal can be encapsulated to prevent seepage of contaminants into the cavity.

Abstract: A semiconductor package onto which a plurality of passive elements is mounted. A substrate includes a first surface and a second surface. A semiconductor chip is on one of the first surface and the second surface of the substrate. A plurality of passive elements are on the substrate. The plurality of passive elements include a plurality of first passive elements and a plurality of second passive elements that are taller than the plurality of first passive elements. The plurality of first passive elements are on at least one of the first surface and the second surface, and at least two of the plurality of second passive elements are on the second surface.

Abstract: This disclosure related to a stacked chip package structure having a sloped dam structure located on the substrate and beside the chip stack. The dam structure can facilitate the dispensing process of the underfill.

Abstract: A package structure includes a substrate, a first die and at least one second die. The substrate includes a first pair of parallel edges and a second pair of parallel edges. The first die is mounted over the substrate. The first die includes a third pair of parallel edges and a fourth pair of parallel edges, wherein the third pair of parallel edges and the fourth pair of parallel edges are not parallel to the first pair of parallel edges and the second pair of parallel edges, respectively. The at least one second die is mounted over the first die.

Abstract: A semiconductor device includes a carrier and a first chip attached to the carrier. The semiconductor device includes a sintered insulation material over at least a portion of the carrier and the first chip.

Abstract: A semiconductor die is attached to a substrate by a glass frit layer. Gas that might be trapped between the die and the glass frit layer during firing of the glass frit can escape through passages that are formed against the bottom surface of the die by topographies that extend away from and which are substantially orthogonal to the bottom of the die.

Abstract: A method of assembly of a semiconductor package includes treating the electrical contacts thereof by the application on the electrical contacts of a chemical composition comprising at least one ionic polar surfactant. A semiconductor package has a coating on the electrical contacts thereof, the coating comprising at least one ionic polar surfactant. A device includes a semiconductor package with electrical contacts on a circuit board, the electrical contacts having a coating that includes an ionic surfactant.

Abstract: A semiconductor package including a substrate, a semiconductor device, a protection layer, a bonding wire, and a molding compound is provided. The substrate has a contact pad and a solder mask, and the contact pad is exposed from the solder mask. The semiconductor device is disposed on the substrate. The protection layer is disposed on the contact pad. The bonding wire connects the semiconductor device to the contact pad. An end of the bonding wire penetrates the protection layer and bonds with a portion of a surface of the contact pad to form a bonding region. The protection layer covers an entire surface of the contact pad except the bonding region. The molding compound covers the semiconductor device, the contact pad, and the bonding wire.

Abstract: A chip structure and a chip package structure are disclosed herein. The chip structure includes a chip and a bump. The chip includes at least one pad. The bump is disposed on a bounding region of the pad. The shape of the bump is triangular pillar or trapezoidal pillar. A surface area of connection between the bump and the pad is less than or equal to the bounding region. Therefore, the material usage and the cost of the bump can be reduced. In addition, such shape of the bump has directional characteristic so that it is easy to perform the chip testing via the identifiable pads, and perform the package process of bonding the chip to a circuit board or any carriers.

Abstract: A pattern structure in a semiconductor device includes an extending line and a pad connected with an end portion of the extending line. The pad may have a width that is larger than a width of the extending line. The pad includes a protruding portion extending from a lateral portion of the pad. The pattern structure may be formed by simplified processes and may be employed in various semiconductor devices requiring minute patterns and pads.

Abstract: A system for storing and retrieving energy may include a cable and a weight connected to the cable. A plurality of cable modules may be attached at spaced-apart locations to the cable above the weight. Each cable module may prevent the cable above and below the cable module from coming in contact with a neighboring stationary wall. A hoist may controllably raise and lower the weight by sequentially grabbing each neighboring cable module.

Abstract: In a control apparatus for an inverter generator having a generator unit driven by an engine, a converter connected to the generator unit to convert an alternating current from the generator unit to a direct current, and an inverter connected to the converter to invert the direct current from the converter to an alternating current and output it to an electric load, it is configured to detect an overload condition based on the alternating current from the inverter to the electric load; stop outputting from the inverter to the electric load with the engine being kept operating when the overload condition is detected; output a release command to release a stop condition where the outputting to the electric load is stopped upon manipulation by an operator; and restart the outputting to the electric load by releasing the stop condition when the release command is outputted.

Abstract: Looped AirFoil Wind Turbine (LAWT) (10) is a novel wind turbine with a basic system of a triangular structure (14) utilizing both lift and drag aerodynamic forces produced by wind energy. The entire triangular structure (14) could either yaw to always face the wind direction (W) or stay in a fixed position. The LAWT system (10) uses airfoil blades (12) shaped like an airplane wing, traveling linearly on travel wheels (22) riding on travel tracks (50, 52, 54). While traveling up, the wings are powered by a positive lift force and drag force while using negative lift force and drag force when traveling downward. All wings (12) are connected by a segmented chain (16) which transfers the kinetic power of wheeled wing carriages (18) directly to multiple generators (26), requiring no gears.

Abstract: A system is disclosed for an electrical generator system for a vehicle. The system includes a wind turbine, an electrical generator mechanically connected to the wind turbine and configured to connect to an electrical energy storage device that is configured to store electrical energy on-board the vehicle, and a rigid, conical housing, forming an interior chamber, the housing having an inlet end and an outlet end, the inlet end having a larger diameter than the outlet end, and the conical housing configured to direct wind flow into the wind turbine.

Abstract: A method is provided for operating a wind turbine with a rotor having a rotor blade adjustable in its blade pitch angle. A generator is connected to the rotor and a measurement unit captures an actual value of a variable representative of a rotational speed of the generator. A set-point for a generator torque is provided and the set-point thereof is corrected. An actual value of a variable representative of a rotational speed of the generator is captured. A set-point for the torque as a function of the captured actual value is provided and the set-point for the torque as a function of a parameter for air density is corrected. A pitch angle value is captured and the set-point for the torque is increased when the captured value for the pitch angle exceeds a minimum value and has been corrected on the basis of an air density parameter.

Abstract: The invention is directed to a method for operating a wind turbine in the event of a grid error. The wind turbine has a rotor having a rotor blade adjustable in its blade pitch angle, a generator and a unit for capturing an actual value of the rotational speed of the generator, a value of the blade pitch angle and an actual value of a variable which is representative of a generator torque. The method includes recognizing a grid error; capturing the actual value of the generator torque and actual value of rotational speed of the generator when a grid error was recognized; determining a change in torque; capturing the pitch angle; determining a corrective value for the pitch angle in dependence upon the change in the generator torque and the value for the pitch angle; and, determining a corrected set-point for the pitch angle.

Abstract: The present invention relates to a wave power generator, and more particularly, to a wave power generator that has comparatively high energy conversion efficiency, so that it can induce active investment and research and development to overcome uncertainties about the natural environment, and which can enhance practicability and value as a clean energy source, especially by virtue of the improved return on investment thereof.

Abstract: A swimming pool water inlet generator operable to allow the generator to be attached to a swimming pool water inlet, a turbine assembly arranged and operable to generate electricity when water flows through the inlet and at least one electrically powered device operable to use the generated electricity in the operation thereof.

Abstract: A wind turbine configuration is constructed with a power cable having an electrical conductor with a plurality of copper clad aluminum strands that are highly flexible. The power cable includes a composite insulator including an insulating material surrounding the electrical conductor and a jacket surrounding the insulating material. The wind turbine configuration includes a wind turbine having a tower with a top and a bottom. A generator is located near the top of the tower, and a transformer is located outside of the wind turbine. A plurality of rotor blades is connected to the generator. The power cable electrically connects the generator of the wind turbine to the transformer. A method includes electrically connecting the power cable to a generator of the wind turbine and to a transformer conveying power supplied by the generator to a switchyard.

Abstract: A wind power turbine configured to generate electric energy, having a supporting structure; a nacelle; a blade assembly rotating with respect to the nacelle; a first and second electric machine having, respectively, a first and second stator, and a first and second rotor substantially coaxial with each other and fitted to the first and second stator to rotate about a first and second axis; and a transmission assembly for connecting the first and second rotor; the transmission assembly being deformable.