Abstract: A backlight unit according to an exemplary embodiment of the present disclosure includes a light emitting diode with a substrate, a light emitting unit disposed on the substrate, and a mold frame disposed on the substrate that surrounds the light emitting unit, and a light guide adjacent to the light emitting diode. The light emitting diode includes a light emitting window defined by the mold frame from which light generated by the light emitting unit is emitted, the vertical height of the light emitting window is the same as the thickness of the light guide, and the maximum vertical height of the mold frame is greater than the thickness of the light guide.

Abstract: A front and back reflector are arranged to form a hollow light recycling cavity having an output region, and one or more light sources (e.g. LEDs) are disposed to emit light into the cavity. In one aspect, the back reflector has a design characterized by a first and second parameter. The first design parameter is a ratio of the collective emitting area of the light sources Aemit to the area of the output region Aout, and Aemit/Aout is preferably from 0.0001 to 0.1. The second design parameter is SEP/H, where H is the depth of the recycling cavity, and SEP is an average plan view source separation associated with the light sources. Other aspects of the disclosed extended area light sources are also described.

Abstract: The present invention provides light-emitting diode (LED) devices comprises compositions and containers of hermetically sealed luminescent nanocrystals. The present invention also provides displays comprising the LED devices. Suitably, the LED devices are white light LED devices.

Abstract: Provided is a lighting device that can reduce the number of light sources while assuring brightness at the center part of an illuminated member. This lighting device (10) is provided with a plurality of light sources (11) and a light guide plate (13) that has light from the light sources incident thereto and guides the light from the light sources. The plurality of light sources are disposed along at least one side surface (13b) of the light guide plate, and the density of disposition of the light sources in the center in the direction of disposition of the plurality of light sources is higher than the density of the disposition of the light sources at the end parts in the direction of the disposition of the plurality of light sources.

Abstract: The light guide plate has a first light incidence surface and a second light incidence surface which are provided on end sides of a light exit surface and are orthogonal to each other. The light guide plate includes two or more layers superposed on each other in a direction substantially perpendicular to the light exit surface and containing scattering particles at different particle concentrations. The thicknesses of the two or more layers in the direction substantially perpendicular to the light exit surface change so that a combined particle concentration of the light guide plate has, in directions perpendicular to the light incidence surfaces, a first local maximum value located on sides closer to the light incidence surfaces and a second local maximum value located at positions farther from the light incidence surfaces than positions of the first local maximum value and being larger than the first local maximum value.

Abstract: A light guide comprising: a main light-guide housing that is elongated shaped, having a first end face, a second end face, and a first lateral face connecting the first end face and the second end face, and the main light-guide housing being elongated in a predetermined direction from the first end face to the second end face; and a protrusion that is connected to the main light-guide housing, having a third end face in an opposite direction from the predetermined direction and a second lateral face connecting the third end face to the first end face, and the protrusion projecting from the first end face in the opposite direction from the predetermined direction, wherein, light emitted toward the third end face by a light source in part exits the protrusion from the second lateral face, then enters the main light-guide housing from the first end face, and thereafter exits the light guide from the first lateral face.

Abstract: A current resonance type DC-DC converter includes a transformer that has a primary winding and a secondary winding, a switching circuit that has a pair of first switching elements and that is connected to the primary winding, an AC/DC transfer circuit that has four rectifying devices, which are connected in full bridge and include a pair of second switching elements, that is connected to the secondary winding, that converts an AC voltage, which is induced at the secondary winding, into a DC voltage and that outputs the DC voltage, and a control circuit that controls ON and OFF operations of the pairs of the first and second switching elements. The control circuit controls the ON and OFF operations so as to synchronize the pair of the first switching elements with the pair of the second switching elements.

Abstract: In controlling switching elements of a current source inverter, a switching loss in the switching element is prevented according to a normal switching operation for a commutation operation, without requiring any particular control. In the commutation operation of the current source inverter, a timing for driving the switching elements is controlled in such a manner that an overlap period is generated, during when both a switching element at the commutation source and a switching element at the commutation target are set to be the ON state, a resonant circuit is controlled based on the control of the switching elements having this overlap period, and resonant current of the resonant circuit reduces the switching loss upon commutation operation of the switching elements.

Abstract: A burst mode controller for a power converter and method of operating the same. In one embodiment, the burst mode controller includes a burst mode initiate circuit configured to initiate a burst mode of operation when a signal representing an output voltage of the power converter crosses a first burst threshold level. The burst mode controller also includes a voltage elevate circuit configured to provide a voltage elevate signal to raise the output voltage if a time window expires before the signal representing the output voltage of the power converter crosses a second burst threshold level.

Abstract: An electric power converter has a switching circuit section, a transformer, a rectifier, and a noise filtering element. The rectifier is connected to a secondary coil of the transformer. A closed circuit where the noise current flows is formed by the secondary coil, the rectifier, and the noise filtering element. The transformer and the noise filtering element are disposed in a position next to each other. The secondary coil and the noise filtering element are electrically connected to each other through a terminal for a coil that is a terminal of the secondary coil and a terminal for a filter that is a terminal of the noise filtering element. The terminal for the coil and the terminal for the filter are disposed in a position between the transformer and the noise filtering element.

Abstract: A control method for bidirectional DC-DC converter includes: operating a bidirectional DC-DC converter in a boost mode, the bidirectional DC-DC converter including a low voltage side and a high voltage side, the low voltage side including low-voltage-side switches, a voltage clamping switch and a voltage clamping capacitor and the high voltage side including high-voltage-side switches; switching the voltage clamping switch with a predetermined duty cycle prior to switching on all of the low-voltage-side switches; adjusting the duty cycle of the voltage clamping switch being smaller than a turn-off interval of the low-voltage-side switches to reduce the conduction loss of the low-voltage-side switches and the voltage clamping switch; alternatively, operating the DC-DC converter in a buck mode; adjusting and extending the duty cycle of the low-voltage-side switches to overlap a turn-off time of the high-voltage-side switches so as to reduce the conduction loss of the low-voltage-side switches.

Abstract: An exemplary embodiment of the present invention relates to a power supply. A power supply according to an exemplary embodiment of the present invention includes: a filter capacitor coupled to a line to which an input voltage rectified from an AC input passed through a dimmer is supplied; a discharge switch coupled to the filter capacitor through the line; and a main switch receiving the input voltage and controlling power transmission. The power supply performs input voltage control to shape the input voltage with a predetermined pattern and controls a switching operation time of the main switch.

Abstract: Embodiments disclose control methods and control apparatuses for a switched mode power supply. The switched mode power supply comprises a current-controllable device. A driving current is provided to turn ON the current-controllable device. A conduction current passing through the current-controllable device is detected. The driving current is controlled according to the conduction current. The higher the conduction current the higher the driving current.

Abstract: The present invention provides a switched-mode power converter with regulation demand pulses sent across a galvanic isolation barrier.

Abstract: A control circuit and a method for controlling a power converter are provided. The method for controlling the power converter includes the following steps. A detection signal is received from the secondary side of the power transformer and a first switching signal is generated in accordance with the detection signal. A second switching signal is generated in accordance with the first switching signal. A voltage signal is generated in accordance with the second switching signal. A comparison signal is generated in accordance with the first switching signal and the second switching signal. The voltage signal and the comparison signal are compared for outputting a comparison result. A gate signal is generated in accordance with the detection signal and the comparison result to control on and off states of a synchronization switch.

Abstract: Discloses are a constant current control unit and a control method, apt to a switched mode power supply with primary side control. The switched mode power supply comprises a power switch and an inductive device. A reflective voltage of the inductive device is detected to generate a feedback voltage signal. By delaying the feedback voltage signal, a delayed signal is generated. According to the feedback voltage and the delayed signal determining, a discharge time of the inductive device is determined when the power switch is OFF. According to the discharge time and a current-sense signal, a maximum average output current of the switched mode power supply is stabilized. The current-sense signal represents a current flowing through the inductive device.

Abstract: A controller for a power converter and method of operating the same. In one embodiment, the controller includes an inductor-inductor-capacitor (“LLC”) controller configured to receive an error signal from an error amplifier to control a switching frequency of an LLC stage of the power converter to regulate an output voltage thereof. The controller also includes a power factor correction (“PFC”) controller configured to control a bus voltage produced by a PFC stage of the power converter and provided to the LLC stage so that an average switching frequency thereof is substantially maintained at a desired switching frequency.

Abstract: The present application discloses methods, circuits and systems for power conversion, using a universal multiport architecture. When a transient appears on the power input (which can be, for example, polyphase AC), the input and output switches are opened, and a crowbar switch shunts the inductance which is used for energy transfer. This prevents this inductance from creating an overvoltage when it is disconnected from outside lines.

Abstract: A power flow controller with a fractionally rated back-to-back (BTB) converter is provided. The power flow controller provide dynamic control of both active and reactive power of a power system. The power flow controller inserts a voltage with controllable magnitude and phase between two AC sources at the same frequency; thereby effecting control of active and reactive power flows between the two AC sources. A transformer may be augmented with a fractionally rated bi-directional Back to Back (BTB) converter. The fractionally rated BTB converter comprises a transformer side converter (TSC), a direct-current (DC) link, and a line side converter (LSC). By controlling the switches of the BTB converter, the effective phase angle between the two AC source voltages may be regulated, and the amplitude of the voltage inserted by the power flow controller may be adjusted with respect to the AC source voltages.

Abstract: An AC tied inverter connectable to an AC source, the AC tied inverter including a DC to DC current fed push-pull converter operable to generate a current waveform from a DC voltage source, the current waveform being substantially synchronized to the AC source, the push-pull converter including a transformer including a first side connectable to a battery and a second side connectable to the AC source, wherein each of the two primary sides is connected to ground via a switching transistor; and respective voltage clamps are connected between the respective primary side of the transformer and the respective switching transistor, the voltage clamp commutating the current from the respective primary side of the transformer when the switching transistor is turned off.

Abstract: A feedback control circuit for a power converter and a power converter system, includes a sampling network, configured to sample an input or output of the power converter, and output a first sampled signal; a filtering network, configured to receive the first sampled signal and output a second sampled signal, the filtering network filtering a ripple signal at a preset frequency out from the first sampled signal, so as to remain signals therein outside the preset frequency, while maintaining a phase delay between the second sampled signal and the first sampled signal within a preset range; a control and drive circuit, configured to receive the second sampled signal, and regulate in accordance with the second sampled signal a control signal outputted from the control and drive circuit to the power converter.

Abstract: Aspects of the invention include a power conversion device control device, including multiple drive circuits having an alarm signal formation circuit that sets a pulse signal having as one cycle a period. The one cycle period includes a determination period, of which a different period is set for each of plural protection circuits that detect information for carrying out a protection operation of semiconductor elements configuring a power conversion device, and a constant period, in which a condition varies with respect to the determination period, takes a protection circuit for which it is first detected that a protection operation is necessary to be a first-come first-served protection circuit, and outputs the pulse signal corresponding to the first-come first-served protection circuit as an alarm signal, wherein the alarm signal formation circuit is such that a resetting condition of the alarm signal is a condition that a protection operation stopped condition.

Abstract: In a process of changing an AC voltage from zero to +Ed (or negative to positive) or from zero to ?Ed (or positive to negative), a control method in accordance with some aspects of the invention detects voltage across the capacitors and when the detected voltage is lower than a predetermined voltage value, switching operation pattern capable of charging the capacitor is given to the switching elements during a short period of time; when the detected voltage is higher than the predetermined voltage value, a switching operation pattern capable of discharging the capacitor is given to the switching elements during a short period of time. Thus, the width of voltage variation of the capacitors is limited within a specified variation range.

Abstract: A converter arrangement (C.5, C.7, C.8, C.9, C.11, C.12) with at least two single LLC converters (L), a pulse generator (2) per single LLC converter (L) wherein each pulse generator (2) is configured to supply switching pulses to one single LLC converter (L) and an output controller (11) configured to use switching frequency control and/or phase-shift control to control the pulse generators (2) comprises a load balancing control (7.5, 7.7, 7.8, 7.9, 7.11, 7.12) for overcoming unbalanced loading of the converter arrangement (C.5, C.7, C.8, C.9, C.11, C.12).

Abstract: According to one embodiment, an AC power system includes a first AC/DC converter to be coupled to a direct current (DC) load and a multi-phase AC power supply. The system further includes a second AC/DC converter coupled in parallel with the first AC/DC converter via an interphase transformer to the DC load and the multi-phase AC power supply. The system further includes a controller coupled to the first and second AC/DC converters, where the controller is configured to generate a gate trigger signal for firing each of the rectifiers for the first and second AC/DC converters. During a first power cycle, a rectifier of the first AC/DC converter is fired at a firing angle advanced to a firing angle of a corresponding rectifier of the second DC/DC converter. During a second power cycle, the rectifier of the first AC/DC converter is fired at a firing angle lagging to a firing angle of the corresponding rectifier of the second AC/DC converter.

Abstract: A method for controlling a converter for converting an n-phase AC input voltage into a DC output voltage, each phase of the AC input voltage being connected to a switch of the converter. The method includes determining the signs of j characteristic voltages (Va, Vb, Vc, Va-Vb, Vb-Vc, Va-Vc, Va+20°, Vb+20°, Vc+20°, Va?20°, Vb?20°, Vc?20°); determining a reference combination (C1-C12, C1-C18), to which the signs of j characteristic voltages (Va, Vb, Vc, Va-Vb, Vb-Vc, Va-Vc, Va+20°, Vb+20°, Vc+20°, Va?20°, Vb?20°, Vc?20°) correspond, by comparing the signs of the j characteristic voltages to data from a reference table; and (c) opening each switch for an opening time (t1, t2, t3) pre-determined according to the reference combination (C1-C12, C1-C18) identified during the determining of the reference combination.

Abstract: The multi-phase inverter modulating method provides for calculating a duty cycle vector (D) calculated as a function of electric parameters defining a rotating vector (Vo) representative of an output electric quantity required from the inverter, is multiplied for a stored modulation matrix to obtain a plurality of duty cycle signals for a plurality of electronic switches of said inverter.

Abstract: A switching power converter has a power converter connected between a DC power source and a load and having a power switch, a current detector detecting a load current, and a PWM controller outputting a first frequency to control the switching frequency of the power switch and outputting an adjustable second frequency to adjust the switching frequency of the power switch according to the load current and a condition of judgment. The condition of judgment serves to determine if the load is a heavy or light load. In the case of light load, the second frequency is reduced to lower the switching loss of the power switch. In the case of heavy load, the second frequency is raised to reduce the ripple of the load current. Accordingly, the conversion efficiency of the switching power converter can be enhanced.

Abstract: A method and apparatus for generating an arbitrary current waveform for use in characterizing power supply impedance for power delivery networks are provided. The method begins by providing an arbitrary waveform as an input to a test circuit. The current and voltage at an output of a device under test in then examined A frequency is then swept through a pre-determined range; and the frequency of the arbitrary voltage waveform is changed to match a predetermined frequency and impedance point.

Abstract: An array of vertically stacked tiers of non-volatile cross point memory cells includes a plurality of horizontally oriented word lines within individual tiers of memory cells. A plurality of horizontally oriented global bit lines having local vertical bit line extensions extend through multiple of the tiers. Individual of the memory cells comprise multi-resistive state material received between one of the horizontally oriented word lines and one of the local vertical bit line extensions where such cross, with such ones comprising opposing conductive electrodes of individual memory cells where such cross. A plurality of bit line select circuits individually electrically and physically connects to individual of the local vertical bit line extensions and are configured to supply a voltage potential to an individual of the global horizontal bit lines. Other embodiments and aspects are disclosed.

Abstract: Embodiments of the invention provide an integrated circuit system, which includes a first supporting substrate and a second supporting substrate, a logic chip disposed between the first supporting substrate and the second supporting substrate, and a plurality of memory stacks disposed adjacent to one another on a surface of the logic chip. The logic chip is separated from the first supporting substrate and the second supporting substrate by a distance such that at least a portion of a first memory stack in the plurality of memory stacks extending outwards past a first side edge of the logic chip is supported by the first supporting substrate, and at least a portion of a second memory stack in the plurality of memory stacks extending outwards past a second side edge of the logic chip that is opposite to the first side edge is supported by the second supporting substrate.

Abstract: Magnetic wires that include cobalt, nickel, and platinum layers show improved domain wall motion properties, when the domain walls are driven by pulses of electrical current. These wires exhibit perpendicular magnetic anisotropy, thereby supporting the propagation of narrow domain walls. The direction of motion of the domain walls can be influenced by the order in which the platinum and cobalt layers are arranged.

Abstract: Magnetic wires that include two antiferromagnetically coupled magnetic regions show improved domain wall motion properties, when the domain walls are driven by pulses of electrical current. The magnetic regions preferably include Co, Ni, and Pt and exhibit perpendicular magnetic anisotropy, thereby supporting the propagation of narrow domain walls. The direction of motion of the domain walls can be influenced by the order in which the wire's layers are arranged.

Abstract: An integrated circuit device (20, 60) includes a plurality of memory cells (22), which are configured to store data. Multiple P-N junctions (24) are arranged so that a single, respective P-N junction is disposed in proximity to each memory cell and is configured to emit optical radiation during readout from the memory cell with a wavelength matching an emission wavelength of the memory cell.

Abstract: There is provided a storage control device including a read processing unit that reads data and inversion state information indicating whether the data is in an inverted state or a non-inverted state from a specific region of a memory cell array that stores the data and the inversion state information with first intensity in association, and a write processing unit that writes data obtained by inverting the data and a state obtained by changing a state indicated by the inversion state information to an opposite state in the specific region with second intensity that is different from the first intensity.

Abstract: A semiconductor memory device including a memory cell array including a memory cell layer containing plural memory cells operative to store data in accordance with different resistance states; and an access circuit operative to make access to the memory cells, the memory cell changing the resistance state from a first resistance state to a second resistance state on application of a voltage of a first polarity, and changing the resistance state from the second resistance state to the first resistance state on application of a voltage of a second polarity, the access circuit applying voltages, required for access to the memory cell, to first and second lines connected to a selected memory cell, and bringing at least one of the first and second lines connected to non-selected memory cells into the floating state to make access to the selected memory cell.

Abstract: A memory cell including a memory element comprising an electrolytic insulator in contact with a conductive metal oxide (CMO) is disclosed. The CMO includes a crystalline structure and can comprise a pyrochlore oxide, a conductive binary oxide, a multiple B-site perovskite, and a Ruddlesden-Popper structure. The CMO includes mobile ions that can be transported to/from the electrolytic insulator in response to an electric field of appropriate magnitude and direction generated by a write voltage applied across the electrolytic insulator and CMO. The memory cell can include a non-ohmic device (NOD) that is electrically in series with the memory element. The memory cell can be positioned between a cross-point of conductive array lines in a two-terminal cross-point memory array in a single layer of memory or multiple vertically stacked layers of memory that are fabricated over a substrate that includes active circuitry for data operations on the array layer(s).

Abstract: A static random access memory apparatus and a bit-line voltage controller thereof are disclosed. The bit-line voltage controller includes a controller, a pull-up circuit, a pull-down circuit and a voltage keeping circuit. The controller receives a bank selecting signal and a clock signal, and decides a pull-up time period, a pull-down time period and a voltage keeping time period according to the bank selecting signal and the clock signal. The pull-up circuit pulls up a bit-line power according to a first reference voltage within the pull-up time period. The pull-down circuit pulls down the bit-line power according to a second reference voltage within the pull-down time period. The voltage keeping circuit keeps the bit-line power to equal to an output voltage during the voltage keeping time period. The voltage keeping time period is after the pull-up time period and the pull-down time period.

Abstract: Embodiments of an apparatus and method to improve power delivery including a pre-charge circuit that may include a first voltage supply rail configured to provide a first voltage amount to perform a first phase of a pre-charge of a bit line and a second voltage supply rail configured to provide a second voltage amount to perform a second phase of the pre-charge of the bit line are described herein. In embodiments, the pre-charge circuit may be a pre charge circuit for a static random-access memory (SRAM) memory cell.

Abstract: A capacitance coupled to a memory node and a word line of an SRAM cell provides an electrostatic capacitance between the memory node and the word line. The capacitance has a first electrostatic capacitance when the word line is in a nonselective state (usually a LOW level) and the memory node retains a HIGH level; the capacitance has a second electrostatic capacitance which is smaller than the first electrostatic capacitance when the word line is in the nonselective state (usually the LOW level) and the memory node retains the LOW level.

Abstract: A word line control circuit includes a first PMOS transistor having a gate coupled to a first selection signal; a first NMOS transistor, coupled between a second node and a second voltage terminal, having a gate coupled to an inverted first selection signal, wherein the inverted first selection signal is obtained by inverting the first selection signal; and a plurality of word line drivers, at least one of the word line drivers comprising a first inverter and a second inverter, wherein a positive power terminal of the first inverter is coupled to the first voltage terminal, a negative power terminal of the first inverter is coupled to the second node, a positive power terminal of the second inverter is coupled to the first node, and a negative power terminal of the second inverter is coupled to the second voltage terminal.

Abstract: A testing method is described that applies a sequence external magnetic fields of varying strength to MRAM cells (such as those with MTJ memory elements) in chips or wafers to selectively screen out cells with low or high thermal stability factor. The coercivity (Hc) is used as a proxy for thermal stability factor (delta). In the various embodiments the sequence, direction and strength of the external magnetic fields is used to determine the high coercivity cells that are not switched by a normal field and the low coercivity cells that are switched by a selected low field. In some embodiment the MRAM's standard internal electric current can be used to switch the cells. Standard circuit-based resistance read operations can be used to determine the response of each cell to these magnetic fields and identify the abnormal high and low coercivity cells.

Abstract: A magnetic memory includes: a base layer; a magnetization free layer; a barrier layer; and a magnetization reference layer. The magnetization free layer, with which the base layer is covered, has invertible magnetization and is magnetized approximately uniformly. The barrier layer, with which the magnetization free layer is covered, is composed of material different from material of the base layer. The magnetization reference layer is arranged on the barrier layer and has a fixed magnetization. When the magnetization of the magnetization free layer is inverted, a first writing current is made to flow from one end to the other end of the magnetization free layer in an in-plane direction without through the magnetization reference layer.

Abstract: Embodiments disclosed herein relate to operating a memory cell as an anti-fuse, such as for use in phase change memory, for example.

Abstract: A memory device includes a magnetic tunnel junction (MTJ) bitcell. The MTJ bitcell includes a first MTJ and a second MTJ. The memory device further includes programming circuitry configured to generate a non-reversible state at the bitcell by applying a program signal to a selected one of the first MTJ and the second MTJ of the bitcell. The non-reversible state corresponds to a value of the MTJ bitcell that is determined by comparing a first value read at the first MTJ and a second value read at the second MTJ.

Abstract: An electronic device includes a device isolation film formed to define an active region in a substrate, a first gate buried to traverse the active region and the device isolation film in a first direction, and a second gate coupled to the first gate buried in the device isolation film, and extended in a second direction.

Abstract: The present disclosure relates to a semiconductor memory device and a method of operation the semiconductor memory device, which sets an encoding value by sequentially defining ranges used for recognizing distribution of memory cells based on a middle range and then performing a read operation in an order from the middle ranges to an outermost range, thereby capable of using infinite ranges for recognizing the distribution of the memory cells without addition of a circuit to an inside of the semiconductor memory device.

Abstract: A system including a read module to perform a first read operation to determine a state of a memory cell, and in response to a first failure to decode data read from the memory cell, perform second and third read operations to determine the state of the memory cell. The memory cell has first and second threshold voltages when programmed to first and second states, respectively. A shift detection module detects, in response to a second failure to decode data read from the memory cell in the second and third read operations, a shift in a distribution of at least one of the first and second threshold voltages. A binning module divides the distribution into a plurality of bins. A log-likelihood ratio (LLR) module generates LLRs for the plurality of bins based on a variance of the distribution and adjusts the LLRs based on an amount of the shift.

Abstract: A memory includes first and second select gate transistors, memory cells, a source line, a bit line, a selected word line which is connected to a selected memory cell as a target of a verify reading, a non-selected word line which is connected to a non-selected memory cell except the selected memory cell, a potential generating circuit for generating a selected read potential which is supplied to the selected word line, and generating a non-selected read potential larger than the selected read potential, which is supplied to the non-selected word line, and a control circuit which classifies a threshold voltage of the selected memory cell to one of three groups by verifying which area among three area which are isolated by two values does a cell current of the selected memory cell belong, when the selected read potential is a first value.

Abstract: A memory cell including a tunnel insulator comprising a plurality of materials, a control gate, a charge blocking material between the tunnel insulator and the control gate, and a discrete trapping material embedded in one of the tunnel insulator or the charge blocking layer.