Abstract: An ovonic threshold switch may be formed of a continuous chalcogenide layer. That layer spans multiple cells, forming a phase change memory. In other words, the ovonic threshold switch may be formed of a chalcogenide layer which extends, uninterrupted, over numerous cells of a phase change memory.

Abstract: The invention relates to a process for preparing an electronic device using a protection layer, and to improved electronic devices prepared by this process, in particular organic field effect transistors (OFETs).

Abstract: A method for forming a thin film electrode for an organic thin film transistor of the invention provides a multi-layer mask on a substrate with an electrode area opening in a top layer of the mask that is undercut by openings in other layers of the mask. A thin film of metal is deposited in the electrode area on the substrate. Removing the multi-layer mask leaves a well-formed thin film electrode with naturally tapered edges. A preferred embodiment of the invention is a method for forming a thin film electrode for an organic thin film transistor. The method includes depositing a first layer of photoresist on a substrate. The photoresist of the first layer has a first etching rate. A second layer of photoresist is deposited on the first layer of photoresist. The photoresist of the second layer has a second etching rate that is lower than the first etching rate. The first and second layer of photoresist are patterned by exposure.

Abstract: Methods of transferring a metal and/or organic layer from a patterned stamp, preferably a soft, elastomeric stamp, to a substrate are provided. The patterned metal or organic layer may be used for example, in a wide range of electronic devices. The present methods are particularly suitable for nanoscale patterning of organic electronic components.

Abstract: The present disclosure provides a method for manufacturing a graphene nano array. The method includes: preparing a substrate having a graphene sheet disposed thereon; sequentially forming a protective layer, a sacrificial layer and a resist layer on the graphene sheet; forming a hole pattern in a surface of the resist layer; etching the sacrificial layer and the protective layer along the hole pattern to form a trench such that a portion of the protective layer adjacent to the graphene sheet can remain; forming a metal layer of a nanocup pattern along a sidewall of the trench while rotating the trench; removing a lower surface of the metal layer to form a metal layer in a nanotube pattern; removing the resist layer and the sacrificial layer; etching the protective layer and the graphene sheet adjacent to the protective layer along the nanotube pattern; and removing the protective layer and the metal layer, thereby providing a graphene nano array having a large area at low cost.

Abstract: Disclosed is a method to manufacture a thin film transistor having an oxide semiconductor as a channel formation region. The method includes; forming an oxide semiconductor layer over a gate insulating layer; forming a source and drain electrode layers over and in contact with the oxide semiconductor layer so that at least portion of the oxide semiconductor layer is exposed; and forming an oxide insulating film over and in contact with the oxide semiconductor layer. The exposed portion of the oxide semiconductor may be exposed to a gas containing oxygen in the presence of plasma before the formation of the oxide insulating film. The method allows oxygen to be diffused into the oxide semiconductor layer, which contributes to the excellent characteristics of the thin film transistor.

Abstract: An insulating layer which releases a large amount of oxygen is used as an insulating layer in contact with a channel region of an oxide semiconductor layer, and an insulating layer which releases a small amount of oxygen is used as an insulating layer in contact with a source region and a drain region of the oxide semiconductor layer. By releasing oxygen from the insulating layer which releases a large amount of oxygen, oxygen deficiency in the channel region and an interface state density between the insulating layer and the channel region can be reduced, so that a highly reliable semiconductor device having small variation in electrical characteristics can be manufactured. The source region and the drain region are provided in contact with the insulating layer which releases a small amount of oxygen, thereby suppressing the increase of the resistance of the source region and the drain region.

Abstract: A combined battery and device apparatus and associated method. This apparatus includes a first conductive layer, a battery comprising a cathode layer; an anode layer, and an electrolyte layer located between and electrically isolating the anode layer from the cathode layer, wherein the anode or the cathode or both include an intercalation material, the battery disposed such that either the cathode layer or the anode layer is in electrical contact with the first conductive layer, and an electrical circuit adjacent face-to-face to and electrically connected to the battery. Some embodiments further include a photovoltaic cell and/or thin-film capacitor. In some embodiments, the substrate includes a polymer having a melting point substantially below 700 degrees centigrade. In some embodiments, the substrate includes a glass. For example, some embodiments include a battery deposited directly on the back of a liquid-crystal display (LCD) device.

Abstract: A method of manufacturing a chip-stacked semiconductor package, the method including preparing a base wafer including a plurality of first chips each having a through-silicon via (TSV); bonding the base wafer including the plurality of first chips to a supporting carrier; preparing a plurality of second chips; forming stacked chips by bonding the plurality of second chips to the plurality of first chips; sealing the stacked chips with a sealing portion; and separating the stacked chips from each other.

Abstract: The invention relates in a general aspect to a method of making vertically protruding elements on a substrate, said elements having a tip comprising at least one inclined surface and an elongated body portion extending between said substrate and said tip. The method comprises an anisotropic, crystal plane dependent etch forming said inclined surface(s); and an anisotropic, non crystal plane dependent etch forming said elongated body portion; combined with suitable patterning processes defining said protruding elements to have a predetermined base geometry.

Abstract: Ball grid array to pin grid array conversion methods are provided. An example method can include coupling a plurality of solder balls to a respective plurality of pin grid array contact pads. Each of the plurality of solder balls is encapsulated in a fixed material. A portion of the plurality of solder balls and a portion of the fixed material is removed to provide a plurality of exposed solder balls. The exposed solder balls are softened and each of a plurality of pin members is inserted in a softened, exposed, solder ball. The plurality of pin members forms a pin grid array package.

Abstract: Methods and systems for altering the electrical resistance of a wiring path. The electrical resistance of the wiring path is compared with a target electrical resistance value. If the electrical resistance of the wiring path exceeds the target electrical resistance value, an electrical current is selectively applied to the wiring path to physically alter a portion of the wiring path. The current may be selected to alter the wiring path such that the electrical resistance drops to a value less than or equal to the target electrical resistance value.

Abstract: When a transistor including a conductive layer having a three-layer structure is manufactured, three-stage etching is performed. In the first etching process, an etching method in which the etching rates for the second film and the third film are high is employed, and the first etching process is performed until the first film is at least exposed. In the second etching process, an etching method in which the etching rate for the first film is higher than that in the first etching process and the etching rate for a “layer provided below and in contact with the first film” is lower than that in the first etching process is employed. In the third etching process, an etching method in which the etching rates for the first to the third films are higher than those in the second etching process is preferably employed.

Abstract: Actuating a semiconductor device includes providing a transistor that includes a substrate and a first electrically conductive material layer, including a reentrant profile, positioned on the substrate. An electrically insulating material layer is conformally positioned over the first electrically conductive material layer and at least a portion of the substrate. A semiconductor material layer conforms to and is in contact with the electrically insulating material layer. A second electrically conductive material layer and third electrically conductive material layer are nonconformally positioned over and in contact with a first portion of the semiconductor material layer and a second portion of the semiconductor material layer, respectively.

Abstract: A non-volatile bistable nano-electromechanical switch is provided for use in memory devices and microprocessors. The switch employs carbon nanotubes as the actuation element. A method has been developed for fabricating nanoswitches having one single-walled carbon nanotube as the actuator. The actuation of two different states can be achieved using the same low voltage for each state.

Abstract: A CMOS device with transistors having different gate dielectric materials and a method of manufacture thereof. A CMOS device is formed on a workpiece having a first region and a second region. A first gate dielectric material is deposited over the second region. A first gate material is deposited over the first gate dielectric material. A second gate dielectric material comprising a different material than the first gate dielectric material is deposited over the first region of the workpiece. A second gate material is deposited over the second gate dielectric material. The first gate material, the first gate dielectric material, the second gate material, and the second gate dielectric material are then patterned to form a CMOS device having a symmetric Vt for the PMOS and NMOS FETs.

Abstract: Embodiments of the present invention provide a method of forming fin-type transistors having replace-gate electrodes with self-aligned diffusion contacts. The method includes forming one or more silicon fins on top of an oxide layer, the oxide layer being situated on top of a silicon donor wafer; forming one or more dummy gate electrodes crossing the one or more silicon fins; forming sidewall spacers next to sidewalls of the one or more dummy gate electrodes; removing one or more areas of the oxide layer thereby creating openings therein, the openings being self-aligned to edges of the one or more fins and edges of the sidewall spacers; forming an epitaxial silicon layer in the openings; removing the donor wafer; and siliciding at least a bottom portion of the epitaxial silicon layer. A semiconductor structure formed thereby is also provided.

Abstract: FinFET devices and methods for the fabrication thereof are provided. In one aspect, a method for fabricating a FET device includes the following steps. A wafer is provided having an active layer on an insulator. A plurality of fin hardmasks are patterned on the active layer. A dummy gate is placed over a central portion of the fin hardmasks. One or more doping agents are implanted into source and drain regions of the device. A dielectric filler layer is deposited around the dummy gate. The dummy gate is removed to form a trench in the dielectric filler layer. The fin hardmasks are used to etch a plurality of fins in the active layer within the trench. The doping agents are activated. A replacement gate is formed in the trench, wherein the step of activating the doping agents is performed before the step of forming the replacement gate.

Abstract: Exemplary embodiments provide structures and methods for power devices with integrated clamp structures. The integration of clamp structures can protect the power device, e.g., from electrical overstress (EOS). In one embodiment, active devices can be formed over a substrate, while a clamp structure can be integrated outside the active regions of the power device, for example, under the active regions and/or inside the substrate. Integrating clamp structure outside active regions of power devices can maximize the active area for a given die size and improve robustness of the clamped device since the current will spread in the substrate by this integration.

Abstract: A semiconductor structure is provided, which includes multiple sections arranged along a longitudinal axis. Preferably, the semiconductor structure comprises a middle section and two terminal sections located at opposite ends of the middle section. A semiconductor core having a first dopant concentration preferably extends along the longitudinal axis through the middle section and the two terminal sections. A semiconductor shell having a second, higher dopant concentration preferably encircles a portion of the semiconductor core at the two terminal sections, but not at the middle section, of the semiconductor structure. It is particularly preferred that the semiconductor structure is a nanostructure having a cross-sectional dimension of not more than 100 nm.

Abstract: A memory array with data/bit lines extending generally in a first direction formed in an upper surface of a substrate and access transistors extending generally upward and aligned generally atop a corresponding data/bit line. The access transistors have a pillar extending generally upward with a source region formed so as to be in electrical communication with the corresponding data/bit line and a drain region formed generally at an upper portion of the pillar and a surround gate structure substantially completely encompassing the pillar in lateral directions and extending substantially the entire vertical extent of the pillar and word lines extending generally in a second direction and in electrical contact with a corresponding surround gate structure at at least a first surface thereof such that bias voltage applied to a given word line is communicated substantially uniformly in a laterally symmetric extent about the corresponding pillar via the surround gate structure.

Abstract: Methods of manufacturing a semiconductor device are provided. The method includes forming a preliminary mask pattern on an etch target layer. The preliminary mask pattern includes wave line type patterns, and each of the wave line type patterns includes main pattern portions and connection bar pattern portions. Node separation walls are formed on sidewalls of the preliminary mask patterns. The etch target layer is etched using the node separation walls as etch masks to form through holes penetrating the etch target layer. Nodes are formed in respective ones of the through holes.

Abstract: An amorphous carbon film and an interlayer insulation film are formed in a memory cell region and a peripheral circuit region, respectively. An insulating film is formed on the amorphous carbon film and the interlayer insulation film. A portion of the insulating film that corresponds to capacitors on the amorphous carbon film is removed so that lower electrodes of the capacitors are supported from opposite sides of the lower electrodes. An insulating film pattern continuously extends from the memory cell region to the peripheral circuit region wholly covered with the insulating film pattern. Subsequently, the amorphous carbon film is removed to leave the capacitors supported by the insulating film pattern on both sides of the lower electrodes.

Abstract: A method of forming improved spacer isolation in deep trench including recessing a node dielectric, a first conductive layer, and a second conductive layer each deposited within a deep trench formed in a silicon-on-insulator (SOI) substrate, to a level below a buried oxide layer of the SOI substrate, and creating an opening having a bottom surface in the deep trench. Further including depositing a spacer along a sidewall of the deep trench and the bottom surface of the opening, and removing the spacer from the bottom surface of the opening. Performing at least one of an ion implantation and an ion bombardment in one direction at an angle into an upper portion of the spacer. Removing the upper portion of the spacer from the sidewall of the deep trench. Depositing a third conductive layer within the opening.

Abstract: A memory cell according to the present invention comprises a bottom conductor, a doped semiconductor pillar, and a top conductor. The memory cell does not include a dielectric rupture antifuse separating the doped semiconductor pillar from either conductor, or within the semiconductor pillar. The memory cell is formed in a high-impedance state, in which little or no current flows between the conductors on application of a read voltage. Application of a programming voltage programs the cell, converting the memory cell from its initial high-impedance state to a low-impedance state. A monolithic three dimensional memory array of such cells can be formed, comprising multiple memory levels, the levels monolithically formed above one another.

Abstract: Method for producing an insulation layer between a first electrode and a second electrode in a trench of a semiconductor body, wherein the method comprises the following features: providing a semiconductor body with a trench formed therein, wherein a first electrode is formed in a lower part of the trench, producing an insulation layer on the first electrode and at the sidewalls of the trench in an upper part of the trench in such a way that the insulation layer is formed in a U-shaped fashion in the trench, producing a protective layer on the insulation layer at least at the bottom of the remaining void in the trench, removing the insulation layer at the sidewalls of the trench in the upper part of the trench, removing the protective layer, producing a second electrode at least on the insulation layer above the first electrode.

Abstract: Fabricating a semiconductor device includes: forming a gate trench in an epitaxial layer overlaying a semiconductor substrate; disposing gate material in the gate trench; forming a body in the epitaxial layer; forming a source in the body; forming an active region contact trench that has a varying trench depth; and disposing a contact electrode within the active region contact trench. Forming the active region contact trench includes performing a first etch to form a first contact trench depth associated with a first region, and performing a second etch to form a second contact trench depth associated with a second region. The first contact trench depth is substantially different from the second contact trench depth.

Abstract: An embodiment of a method for manufacturing a power device with conductive gate structures inside etched trenches. Such trenches include sidewalls and a bottom, wherein covering the sidewalls and the bottom of the trench is a first insulating coating layer. In the formation of the conductive gate structure, openings within the first material in the trench are made such that a conductive central region of a second conductive material having a different resistivity than the first conductive material are able to be electrically coupled together through a plurality of conductive bridges between said second conductive coating layer and said conductive central region.

Abstract: A high voltage trench MOS and its integration with low voltage integrated circuits is provided. Embodiments include forming, in a substrate, a first trench with a first oxide layer on side surfaces, a narrower second trench, below the first trench with a second oxide layer on side and bottom surfaces, and spacers on sides of the first and second trenches; removing a portion of the second oxide layer from the bottom surface of the second trench between the spacers; filling the first and second trenches with a first poly-silicon to form a drain region; removing the spacers, exposing side surfaces of the first poly-silicon; forming a third oxide layer on side and top surfaces of the first poly-silicon; and filling a remainder of the first and second trenches with a second poly-silicon to form a gate region on each side of the drain region.

Abstract: Non-planar Metal Oxide Field Effect Transistors (MOSFETs) and methods for making non-planar MOSFETs with asymmetric, recessed source and drains having improved extrinsic resistance and fringing capacitance. The methods include a fin-last, replacement gate process to form the non-planar MOSFETs and employ a retrograde metal lift-off process to form the asymmetric source/drain recesses. The lift-off process creates one recess which is off-set from a gate structure while a second recess is aligned with the structure. Thus, source/drain asymmetry is achieved by the physical structure of the source/drains, and not merely by ion implantation. The resulting non-planar device has a first channel of a fin contacting a substantially undoped area on the drain side and a doped area on the source side, thus the first channel is asymmetric. A channel on atop surface of a fin is symmetric because it contacts doped areas on both the drain and source sides.

Abstract: Methods are provided for fabricating a FINFET integrated circuit that includes epitaxially growing a first silicon germanium layer and a second silicon layer overlying a silicon substrate. The second silicon layer is etched to form a silicon fin using the first silicon germanium layer as an etch stop. The first silicon germanium layer underlying the fin is removed to form a void underlying the fin and the void is filled with an insulating material. A gate structure is then formed overlying the fin.

Abstract: In a method of manufacturing a transistor, a gate structure is formed on a substrate including silicon. An upper portion of the substrate adjacent to the gate structure is etched to form a first recess in the substrate. A preliminary first epitaxial layer including silicon-germanium is formed in the first recess. An upper portion of the preliminary first epitaxial layer is etched to form a second recess on the preliminary first epitaxial layer. In addition, a portion of the preliminary first epitaxial layer adjacent to the second recess is etched to thereby transform the preliminary first epitaxial layer into a first epitaxial layer. A second epitaxial layer including silicon-germanium is formed in the second recess located on the first epitaxial layer.

Abstract: A self-aligned carbon-nanotube field effect transistor semiconductor device comprises a carbon-nanotube deposited on a substrate, a source and a drain formed at a first end and a second end of the carbon-nanotube, respectively, and a gate formed substantially over a portion of the carbon-nanotube, separated from the carbon-nanotube by a dielectric film.

Abstract: A method of manufacturing a tunnel field effect transistor is disclosed. The method comprises forming a two-step profile in a silicon substrate (100) using a patterned hard mask (104) covering the higher steps of said profile; forming a gate stack (114, 116) against the side wall of the higher step; forming spacers (122) on either side of the gate stack (118); and implanting a first type impurity (124) in the higher step and an opposite type impurity in the neighboring lower step (120), wherein at least the first type impurity is implanted using an angled implanting step after removing the patterned hard mask (104). In a preferred embodiment, the method further comprises forming a sacrificial spacer (108) against a side wall of a higher step and the side wall of the hard mask (104); further etching the lower step (106, 110) next to said spacer (108) and subsequently growing a further semiconductor portion (112) on said lower step and removing the spacer (108) prior to forming the gate stack.

Abstract: To reduce dent defects formed in interlayer CMP process on a capacitor array after forming an interlayer insulating film on the capacitor array thicker than the height of a capacitor, the interlayer insulating film on the capacitor array is subjected to a step height reduction etching to form an opening with etching depth Hd, while remaining a first region that is a distance Lr in a horizontal direction from a rising point of a projected portion of the interlayer insulating film periphery to the capacitor array onto a part of the capacitor array, wherein an aspect ratio (Hd/Lr) of the Hd to the Lr is equal to or less than 0.6.

Abstract: Methods of forming and the resulting capacitors formed by these methods are shown. Monolayers that contain praseodymium are deposited onto a substrate and subsequently processed to form praseodymium oxide dielectrics. Monolayers that contain titanium or other metals are deposited onto a substrate and subsequently processed to form metal electrodes. Resulting capacitor structures includes properties such as improved dimensional control. One improved dimensional control includes thickness. Some resulting capacitor structures also include properties such as an amorphous or nanocrystalline microstructure. Selected components of capacitors formed with these methods have better step coverage over substrate topography and more robust film mechanical properties.

Abstract: A semiconductor component includes a semiconductor body, in which are formed: a substrate of a first conduction type, a buried semiconductor layer of a second conduction type arranged on the substrate, and a functional unit semiconductor layer of a third conduction type arranged on the buried semiconductor layer, in which at least two semiconductor functional units arranged laterally alongside one another are provided. The buried semiconductor layer is part of at least one semiconductor functional unit, the semiconductor functional units being electrically insulated from one another by an isolation structure which permeates the functional unit semiconductor layer, the buried semiconductor layer, and the substrate. The isolation structure includes at least one trench and an electrically conductive contact to the substrate, the contact to the substrate being electrically insulated from the functional unit semiconductor layer and the buried layer by the at least one trench.

Abstract: A description is given of a method. In one embodiment the method includes providing a semiconductor chip with semiconductor material being exposed at a first surface of the semiconductor chip. The semiconductor chip is placed over a carrier with the first surface facing the carrier. An electrically conductive material is arranged between the semiconductor chip and the carrier. Heat is applied to attach the semiconductor chip to the carrier.

Abstract: According to one embodiment, a method of manufacturing a semiconductor device including forming a metal film on aback surface of a glass substrate which supports a semiconductor substrate on a front surface thereof; forming a metal oxide film by oxidizing the whole or at least a portion of the metal film from the front surface; forming protective film, such as silicon nitride, on the metal oxide film; holding the front surface of the protective film with an electrostatic chuck; and forming a via for electrical connection in the semiconductor substrate while the front surface of the protective film is in contact with by the electrostatic chuck; then using a laser to delaminate the glass substrate from the semiconductor substrate.

Abstract: Aspects of the invention provide for preventing undercuts during wafer etch processing and enhancing back-gate to channel electrical coupling. In one embodiment, aspects of the invention include a semiconductor structure, including: a high-k buried oxide (BOX) layer atop a bulk silicon wafer, the high-k BOX layer including: at least one silicon nitride layer; and a high-k dielectric layer; and a silicon-on-insulator (SOI) layer positioned atop the high-k BOX layer.

Abstract: A method and system for cleaving a film of material utilizing thermal flux. The method includes providing a substrate having a face and an underlying cleave region including a prepared initiation region. Additionally, the method includes subjecting the initiation region to a first thermal flux to form a cleave front separating the cleave region of the substrate to a film portion and a bulk portion. The method further includes subjecting an area of the bulk portion substantially in the vicinity of the cleave front to a second thermal flux to cause a temperature difference above and below the cleave region for inducing a propagation of the cleave front expanding the film portion to the area at the expense of the bulk portion. Furthermore, the method includes determining a scan path for the second thermal flux based on the cleave front. Moreover, the method includes scanning the second thermal flux to follow the scan path to further propagate the cleave front.

Abstract: Methods of fabricating semiconductor structures include forming a plurality of openings extending through a semiconductor material and at least partially through a metal material and deforming the metal material to relax a remaining portion of the semiconductor material. The metal material may be deformed by exposing the metal material to a temperature sufficient to alter (i.e., increase) its ductility. The metal material may be formed from one or more of hafnium, zirconium, yttrium, and a metallic glass. Another semiconductor material may be deposited over the remaining portions of the semiconductor material, and a portion of the metal material may be removed from between each of the remaining portions of the semiconductor material. Semiconductor structures may be formed using such methods.

Abstract: Methods are disclosed to fabricate a transistor, for example a FinFET, by forming over a substrate at least one electrically conductive channel between a source region and a drain region; forming a gate structure to be disposed over a portion of the channel, the gate structure having a width and a length and a height defining two opposing sidewalls of the gate structure and being formed such that the channel said passes through the sidewalls; forming spacers on the sidewalls; forming a layer of epitaxial silicon over the channel; removing the spacers; and forming a dielectric layer to be disposed over the gate structure and portions of the channel that are external to the gate structure such that a capacitance-reducing air gap underlies the dielectric layer and is disposed adjacent to the sidewalls of said gate structure in a region formerly occupied by the spacers.

Abstract: According to one exemplary embodiment, a method for fabricating a high voltage durability transistor comprises forming a gate over a gate oxide layer formed over a substrate, aligning an exposure mask with the gate, and selectively blocking exposure of the gate during gate implant doping, by exposure shields formed in the exposure mask, thereby producing the high voltage durability transistor. In one embodiment, an exemplary high voltage durability transistor comprises a gate formed over a gate oxide layer, the gate oxide layer being situated over a semiconductor substrate, where the gate has a reduced doping implant due to selective implant blocking provided by exposure shields formed in an exposure mask. The selective implant blocking results in an enhanced dielectric barrier so as to produce a high voltage durability transistor. The enhanced dielectric barrier has a depletion region with an increased thickness.

Abstract: An electronic device includes a silicon carbide layer having a first conductivity type and a main junction adjacent a surface of the silicon carbide layer, and a junction termination region at the surface of the silicon carbide layer adjacent the main junction. Charge in the junction termination region decreases with lateral distance from the main junction, and a maximum charge in the junction termination region may be less than about 2×1014 cm?2.

Abstract: A circuit and a method of layout-designing a circuit based on circuit information. The method includes generating layout information including a core region based on the circuit information, laying out an I/O circuit in a region other than the core region on the layout information based on the circuit information, determining a layout-permitted region of pads, which is included in regions other than the core region and a layout region of said I/O circuit, based on circuit information, and laying out the pads in the layout-permitted region.

Abstract: A heat generating component of a semiconductor device is located between two heavily doped semiconductor regions in a semiconductor substrate. The heat generating component may be a middle portion of a diode having a light doping, a lightly doped p-n junction between a cathode and anode of a silicon controlled rectifier, or a resistive portion of a doped semiconductor resistor. At least one thermally conductive via comprising a metal or a non-metallic conductive material is place directly on the heat generating component. Alternatively, a thin dielectric layer may be formed between the heat generating component and the at least one thermally conductive via. The at least one thermally conductive via may, or may not, be connected to a back-end-of-line metal wire, which may be connected to higher level of metal wiring or to a handle substrate through a buried insulator layer.

Abstract: A method of making a memory array is provided that includes forming a layer over a substrate, forming features over the layer, forming sidewall spacers on each of the features, filling spaces between adjacent sidewall spacers with filler features, removing the sidewall spacers to leave the features and the filler features, and etching the layer using the features and the filler features as a mask to form pillar shaped nonvolatile memory cells. Numerous other aspects are provided.

Abstract: Metal gate structures and methods for forming thereof are provided herein. In some embodiments, a method for forming a metal gate structure on a substrate having a feature formed in a high k dielectric layer may include depositing a first layer within the feature atop the dielectric layer; depositing a second layer comprising cobalt or nickel within the feature atop the first layer; and depositing a third layer comprising a metal within the feature atop the second layer to fill the feature, wherein at least one of the first or second layers forms a wetting layer to form a nucleation layer for a subsequently deposited layer, wherein one of the first, second, or third layers forms a work function layer, and wherein the third layer forms a gate electrode.

Abstract: A method of manufacturing a semiconductor chip is disclosed. A die having a plurality of die-pads is attached to a substrate in a semiconductor package which includes a plurality of substrate-pads. The method involves forming conductive column bumps of differing volumes extending from the die-pads; attaching each of the column bumps to a corresponding substrate-pad to form a subassembly; and reflowing the subassembly so that the column bumps form robust electrical and mechanical connections between the die pads and the substrate pads.