Abstract: A clock generator includes a digitally controlled oscillator configured to generate an output clock having a frequency depending on an input code; a phase comparison section configured to output a phase difference signal by comparing a reference phase with a phase of the output clock, the reference phase being based on an input clock and a predetermined frequency multiplication number; a low-pass filter configured to provide the input code for the digitally controlled oscillator by filtering the phase difference signal; a waveform generating section configured to generate a predetermined spread spectrum wave, the predetermined spread spectrum wave being to be added with both of the frequency multiplication number and the input code; and a detection/compensation section configured to compensate the input code so that the phase difference is reduced, the phase difference being detected from the phase difference signal.

Abstract: This document discusses, among other things, a system and method for reducing electromagnetic interference of a switched signal. In an example, a switched input signal can be received at an input and a transition rate of an edge rate controlled, switched output signal can be controlled in response to the received switched input signal.

Abstract: Aspects of the invention provide for equalizing rise and fall slew rates at an output for a buffer. In one embodiment, a method includes: measuring, simultaneously, rise and fall slew rates at an input of the buffer and rise and fall slew rates at the output of the buffer; generating a slew reference based on at least one of the rise slew rate or the fall slew rate at the input of the buffer; comparing the rise slew rate and the fall slew rate at the output of the buffer to the slew reference; and generating at least one of a rise control signal or a fall control signal for adjusting at least one of the rise slew rate or the fall slew rate at the output of the buffer.

Abstract: A circuit can compensate for intra pair skew or mode conversion in a channel by applying a second or corrective mode conversion effect that counters the channel's mode conversion. The circuit can process the common mode signal with a frequency dependent filter prior to injection back into the differential mode. The circuit can implement the reverse mode conversion with passive circuits using integrated resistors and metal oxide semiconductor (MOS) switches. In certain embodiments, such actions can proceed effectively without necessarily consuming active power.

Abstract: Groups of phase shifted Pulse Width Modulation (PWM) signals are generated that maintain their duty-cycle and phase relationships as a function of the period of the PWM signal frequency. The multiphase PWM signals are generated in a ratio-metric fashion so as to greatly simplify and reduce the computational workload for a processor used in a PWM system. The groups of phase shifted PWM signals may also be synchronized with and automatically scaled to match external synchronization signals.

Abstract: A signal transmission circuit includes a first selection driver configured to generate a first drive signal in response to an input signal and a first selection signal and drive a transmission signal in response to the first drive signal, and a second selection driver configured to delay the input signal by a first delay time to generate a first delay signal. The second selection driver generates a second drive signal in response to the first delay signal and a second selection signal, generates a first code signal in response to the input signal and the second selection signal, and drives the transmission signal in response to the second drive signal and the first code signal.

Abstract: Systems and methods for generating pulse clocks with programmable edges and pulse widths configured for varying requirements of different memory access operations. A pulse clock generation circuit includes a selective delay logic to provide a programmable rising edge delay of the pulse clock, a selective pulse width widening logic to provide a programmable pulse width of the pulse clock, and a built-in level shifter for shifting a voltage level of the pulse clock. A rising edge delay for a read operation is programmed to correspond to an expected read array access delay, and the pulse width for a write operation is programmed to be wider than the pulse width for a read operation.

Abstract: A mode determination circuit is configured to determine whether there is a status change of the electric system associated with a frequency variation of a system control clock, and a clock change circuit is configured to change the system control clock from a system clock to a monitoring clock based on a determination result obtained by the mode determination circuit.

Abstract: A level-shift circuit, comprising: an input, for receiving a first voltage; an output, for outputting a second voltage; a resistor array comprising one or more resistors connected in series to the input; a current sink for providing a current that is independent of the first voltage; a switch arrangement comprising a plurality of switch connections for establishing a selected one from a plurality of force paths between the current sink and the input, the selected force path comprising a selected number of the one or more resistors of said resistor array; and at least one connection between the output and the resistor array that provides a sense path between the resistor array and the output that does not comprise any of the switch connections used to establish each of the plurality of force paths.

Abstract: A switch circuit can include an impedance selection switch and a multi-output-resistance switch driver. The impedance selection switch can electrically connect an impedance to an input of an amplifier in response to a driver output signal, and include at least one transistor. The multi-output-impedance switch driver may provide the driver output signal to the switch, and have a first, relatively higher output resistance when providing a first logic state of the driver output signal to turn on the switch, and a second, relatively lower output resistance when providing a second logic state of the driver output signal to turn off the switch. The ratio of the first output resistance to the second output resistance can be greater than a selected predetermined ratio value.

Abstract: Level shifting circuitry comprises a first level shifter and a second level shifter. In response to a falling edge transition of an input signal, the first level shifter generates a primary transition of a first intermediate signal faster than the second level shifter generates a secondary transition of a second intermediate signal. In response to a rising edge of the input signal, the second level shifter generates a primary transition of the second intermediate signal faster than the first level shifter generates a secondary transition of the first intermediate signal. Output switching circuitry is provided to switch an output signal between an output high voltage level and an output low voltage level in response to the primary transition of the first intermediate signal and the primary transition of the second intermediate signal.

Abstract: A signal transmitting apparatus that may suppress generation of a noise voltage attributable to a common mode voltage is provided. A transistor P1 is connected between a first terminal of a sending coil and a power supply voltage. A transistor N1 is connected between the first terminal and a ground voltage. A transistor P2 is connected between a second terminal of the sending coil and the power supply voltage. A transistor N2 is connected between the second terminal and the ground voltage. In a period-PE1 a coil current flowing in a positive direction is generated by turning on the transistors P1 and N2 and turning off the transistors P2 and N1, and then the transistor N1 is turned on in response to turning off the transistor P1. In a period PE2, a coil current flowing in a negative direction is generated by turning off the transistors P1 and N2 and turning on the transistors P2 and N1, and then the transistor N2 is turned on in response to turning off the transistor P2.

Abstract: Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals are described. Such devices and method include use of symmetrical compensation capacitances, symmetrical series capacitors, or symmetrical sizing of the elements of the stack.

Abstract: An integrated circuit (100) in which a voltage divider circuit is integrated comprises a first resistor (121), second resistor (122), control portion (130), switch (140), and switching portion (150). The first resistor (121) and second resistor (122) form a resistive voltage divider element for dividing a voltage obtained by rectifying an alternating-current voltage, or a direct-current voltage, supplied to a control portion (130). The switch (140) is provided in series with the resistive voltage divider element, and passes or cuts off current passing through the resistive voltage divider element. The switching portion (150) switches the switch (140) so as to pass current during driving of the control portion (130), and cut off current during standby of the control portion (130).

Abstract: Power control is facilitated. In accordance with one or more embodiments, power is supplied to power rails of an integrated circuit using a power control circuit including a power regulator and a reset circuit that is responsive to a supply voltage. The power regulator provides power to the power rails, based upon a control signal. The reset circuit controls the power regulator to provide power to the power rails independently of the control signal when the supply voltage is below an operational voltage level, and controls the power regulator to provide power to the power rails in response to the control signal when the supply voltage reaches the operational voltage level.

Abstract: A reference current generating circuit with high current mirror accuracy is provided by low power supply voltage operation. The reference current generating circuit includes a cascode current mirror circuit 1 outputting mirror currents I1 and I2, and a reference current Iref, a current-voltage converter circuit 2 converting the mirror current I1 into a voltage V1, a current-voltage converter circuit 3 converting the mirror current I2 into a voltage V2, a differential amplifier 4 in which the voltage V1 is input to a first input terminal and the voltage V2 is input to a second input terminal, a voltage-current converter circuit 5 converting a voltage V3 output from the differential amplifier 4 into currents I3 and I4, and a current-voltage converter circuit 6 converting the current I3 into a voltage V4 which is output to a gate of a transistor in the cascode current mirror circuit.

Abstract: A semiconductor device and a method of operating the semiconductor device. The semiconductor device includes a voltage generator configured to generate a test voltage, a graphene transistor configured to receive a gate-source voltage based on the test voltage, and a detector configured to detect whether the gate-source voltage is a Dirac voltage of the graphene transistor, and output a feedback signal applied to the voltage generator indicating whether the gate-source voltage is the Dirac voltage.

Abstract: An amplifier and a display driving circuit. The amplifier includes an input stage, a bias stage and an output stage. The input stage determines voltage levels of two nodes in correspondence to two input voltages received in response to a first bias voltage, and includes four path selecting switches, two input transistors and one bias transistor. The bias stage generates two class AB output voltages which correspond to the voltage levels of the two nodes, and includes current mirrors, ten path selecting switches, class AB bias circuits and two bias transistors. The output stage generates an output voltage VOUT that corresponds to the two class AB output voltages, and includes two coupling capacitors and two push-pull transistors. The plurality of path selecting switches operate by one signal of a first path selecting signal and a second path selecting signal that are exclusively enabled with respect to each other.

Abstract: A switched-capacitor DC blocking amplifier is disclosed. In an embodiment, an integrated circuit is provided that includes an amplifier having an amplifier input and an amplifier output, a capacitor connected to the amplifier input and configured to receive an input signal, and a switched capacitor circuit coupled to provide a resistance between the amplifier input and the amplifier output. In one implementation, the switched capacitor circuit is configured with a feed forward circuit to reduce aliasing. In another implementation, the switched capacitor circuit includes a switched impedance circuit to reduce noise.

Abstract: Apparatus and methods for notch filtering are provided. In certain implementations, an amplifier includes amplification stages for providing signal amplification, chopper circuitry for generating a chopped signal by chopping an amplified signal associated with the amplification stages at a chopping frequency, and a time-interleaved finite impulse response (FIR) notch filter for notching frequency components of the chopped signal near the chopping frequency. The time-interleaved FIR notch filter includes a plurality of FIR filters configured to sample the chopped signal at a sampling rate of about twice the chopping frequency. The FIR filters are interleaved in time to reduce sampling error. Additionally, the time-interleaved FIR notch filter includes an infinite impulse response (IIR) filter configured to average samples taken by respective ones of the FIR filters and to integrate the averaged samples to generate the time-interleaved FIR notch filter's output signal.

Abstract: An operational amplifier includes an input stage, an output stage, an output enable switch, an internal capacitor, a coupling effect reduction circuit. The input stage provides an intermediate signal according to an input signal. The output stage, including an output node, provides a driving signal according to the intermediate signal. The output enable switch is turned on during an output enable period, having a start time point, to drive a load with the driving signal. The internal capacitor is coupled between the input stage and the output stage. The coupling effect reduction circuit, coupled between the internal capacitor and the output node or between the internal capacitor and the input stage, is turned off during an operational period starting from the start time point, to prevent coupling charge generated when the output enable switch is turned on from affecting operational voltage levels of the input stage.

Abstract: Systems and methods for power amplification using multiple digital amplifiers are provided. A power amplifier includes a first digital amplifier configured to process a digital input signal to generate a first analog output signal. The first analog output signal is configured to have a magnitude corresponding to amplitude information of the digital input signal. The power amplifier further includes a second digital amplifier configured to process an adjusted digital input signal to generate a second analog output signal. The second analog output signal is configured to have a magnitude corresponding to amplitude information of the adjusted digital input signal. An adjustment module configured to adjust amplitude information and phase information of the digital input signal generates the adjusted digital input signal. The digital input signal is adjusted to control a relationship between the first analog output signal and the second analog output signal.

Abstract: A method and apparatus for providing a power supply for an amplifier is provided. The power conversion is achieved using synchronous rectifiers in a regulated half bridge power supply, taking the sum of the positive and negative rails as feedback, in order facilitate energy transfer between positive and negative output rails. This minimizes the effects of off side charging and rail sag, as well as achieving good line regulation, while allowing use of very small, low value output capacitors.

Abstract: A headphone driver amplifier operative from a single DC voltage supply, coupled directly to the headphone speakers without the need for DC coupling capacitors used for preventing DC reaching the headphones. An onboard power supply generates a negative voltage rail which powers the output amplifiers, allowing driver amplifier operation from both positive and negative rails. Since the amplifiers can be biased at ground potential (0 volts), no significant DC voltage exists across the speaker load and the need for DC coupling capacitors is eliminated.

Abstract: The invention relates to high power radiofrequency amplifiers, in particular to amplifiers having output impedance matching networks, exemplary embodiments of which include a radiofrequency amplifier having an active device mounted on a substrate within a device package, the amplifier having an output impedance matching network comprising a high pass network provided at least partly on the active device and a low pass network having a first inductive shunt connection between an output of the active device and a first output lead and a second inductive shunt connection between the output of the active device and a second output lead, wherein part of the second output lead forms an inductance contributing to the inductance of the low pass network.

Abstract: A local oscillator of an embodiment includes a digitally-controlled oscillator, a phase data generator, a subtractor, a loop filter, a multiplier, and a coefficient calculator. The digitally-controlled oscillator variably controls an oscillation frequency of an oscillation signal by using a first oscillator control value. The oscillation frequency is equal to a product of the first oscillator control value multiplied by an amount of change in the oscillation frequency per unit first oscillator control value. Set frequency data is calculated by dividing a set frequency by a reference frequency of a reference signal. The multiplier outputs the first oscillator control value obtained by multiplying a normalized control value from the loop filter by a first coefficient. The coefficient calculator divides, by the set frequency data, the first oscillator control value which makes the oscillation frequency roughly equal to the set frequency, and sets the quotient as a new first coefficient in the multiplier.

Abstract: A method of calibrating a phase-locked loop (PLL) while maintaining lock includes detecting that a control signal to an oscillator in a PLL has exceeded a threshold value while the PLL is locked to an input signal. In response, an operating current of the oscillator is adjusted to return the control signal below the threshold value while maintaining lock of the PLL to the input signal. Adjusting the operating current includes slowly varying an output current of a calibration circuit coupled to the PLL, enabling the PLL to maintain lock to the input signal during adjustment of the operating current.

Abstract: The invention relates to a digital signal generator for providing one or more phases of a local oscillator signal for use in digital to analogue converters and harmonic rejection mixers. Embodiments disclosed include a local oscillator signal generator (200) for a mixer of a radiofrequency receiver, the signal generator (200) comprising a bit sequence generator (201) having a plurality of parallel output lines (203), a digital signal generator (202) having a serial output line (204) and a plurality of input lines connected to respective output lines (203) of the bit sequence generator (201) and a clock signal input line (205), wherein the digital signal generator (202) is configured to provide an output bit sequence on the serial output line (204) at a rate given by a clock signal provided on the clock signal input line (205) and a sequence given by a sequence of bits from the bit sequence generator (201) on the plurality of input lines (203).

Abstract: A circuit including a first oscillator configured to oscillate at a first frequency; a second oscillator configured to oscillate at a second frequency, the second frequency being different from and one of a harmonic or sub-harmonic of the first frequency; and a coupling between the first oscillator and the second oscillator configured to injection lock at least one of the first oscillator and second oscillator to the other of the first oscillator and second oscillator.

Abstract: A slew rate enhancing system includes first and second modules. The first module is configured to generate a first output signal in response to complementary first and second input signals. The second module is configured to generate a second output signal in response to the first and second input signals. The first module is configured to switch between tracking the first input signal and not tracking the first input signal during each half cycle of the first input signal based on values of the first input signal, the second input signal, and a predetermined threshold of the first module. The second module is configured to switch between tracking the first input signal and not tracking the second input signal during each half-cycle of the second input signal based on values of the first input signal, the second input signal, and a predetermined threshold of the second module.

Abstract: An optical module for an atomic oscillator using a quantum interference effect includes a light source adapted to emit light including a fundamental wave having a predetermined wavelength, and sideband waves of the fundamental wave, a wavelength selection section receiving the light from the light source, and adapted to transmit the sideband waves, a gas cell encapsulating an alkali metal gas and irradiated with light transmitted through the wavelength selection section, and a light detection section adapted to detect an intensity of light transmitted through the gas cell, and the wavelength selection section including an optical filter section adapted to transmit light having a wavelength within a predetermined wavelength range, and an optical filter characteristic control section adapted to vary the wavelength range of light to be transmitted by the optical filter section.

Abstract: Methods of testing packaged thin-film piezoelectric-on-semiconductor (TPoS) microelectromechanical resonators having hermetic seals include measuring a quality factor (Q) of resonance of the packaged resonator at at least two unequal temperatures to determine whether a ?Q/?T is significantly different (e.g, by at least 50%) over a temperature range (?T) spanning a smallest and largest of the at least two temperatures. These measurements are performed for a packaged resonator having a QAIR<QTED, where QAIR is the quality factor of resonance of the packaged resonator due to air damping and QTED is the quality factor of resonance of the packaged resonator due to thermoelastic damping.

Abstract: Micromechanical resonating devices, as well as related methods, are described herein. The resonating devices can include a micromechanical resonating structure, an actuation structure that actuates the resonating structure, and a detection structure that detects motion of the resonating structure. A bias structure separated from the mechanical resonating structure is provided to tune a resonance frequency of the mechanical resonating structure.

Abstract: A method for manufacturing a piezoelectric vibrator is provided. The piezoelectric vibrator includes: a package in which a first substrate and a second substrate are superimposed so as to form a cavity therebetween; extraction electrodes which are formed on the first substrate so as to be extracted from the inner side of the cavity to an outer edge of the first substrate; a piezoelectric vibrating reed which is sealed in the cavity and electrically connected to the extraction electrodes at an inner side of the cavity; and outer electrodes which are formed on an outer surface of the package so as to be electrically connected to the extraction electrodes at the outer side of the cavity.

Abstract: A Guanella type balun with a conductive enclosure (for example, a re-entrant box) between its coupled lines and the magnetic material enclosing its coupled lines. Some embodiments use coupled strip lines. Some embodiments have dielectric material, such as printed circuit board material inside the re-entrant box along with the coupled strip lines. Preferably, the magnetic material is ferrimagnetic. Some preferred magnetic materials are non-conductive.

Abstract: A power multiplier and method are provided. The power multiplier includes a power multiplying network that is a multiply-connected, velocity inhibiting circuit constructed from a number of lumped-elements. The power multiplier also includes a launching network, and a directional coupler that couples the launching network to the power multiplying network. The power multiplier provides for power multiplication at nominal power generation frequencies such as 50 Hertz, 60 Hertz, and other power frequencies, in a compact circuit.

Abstract: A power switch includes switch contacts that are opened via a switch shaft, which, when the switch is triggered, is actuated by way of the trigger slider of a trigger unit, in particular a working current trigger unit. The trigger slider moves the switch shaft by way of the trigger shaft of a switch latch, the trigger unit including electric coil into which an armature extends that is drawn into the coil by electromagnetic forces of attraction when the switch is triggered. A stationary counter armature is disposed in the coil, which counter armature serves as a stop for the armature, so as to increase the forces of attraction. The movement of the armature is transmitted by way of a mechanism to the movement of the trigger slider so as to increase the displacement path of the trigger slider.

Abstract: An arc chute for a DC circuit breaker is disclosed which includes at least one stack of a plurality of substantially parallel metal plates, the at least one stack defining a first axis A in parallel to a stacking direction; an arc space adapted to allow an arc to extend along the first axis, wherein a second axis traversing in parallel to the metal plates the at least one stack and the arc space substantially orthogonal to the first axis. Further, an arc-chute housing having at least one side wall, the at least one side wall being substantially parallel to the second axis, wherein the distance between the at least one sidewall and the metal plates is, for example, less than 5 mm, such as less than 2 mm.

Abstract: A magnetically-sensitive switch includes a housing, a metal block, a sling block, a rigid link, a first plate and an electrical switch. The housing includes a top wall, a bottom wall and two opposite sidewalls. A pair of sliding grooves is defined in the opposite sidewalls. The metal block is placed on the bottom wall. The sliding block is slidably connected to the sliding grooves. The rigid link is pivotally interconnected between the metal block and the sliding block. The first plate is attached to the housing. When the metal block is attracted by a magnetic force generated by a magnet placed adjacent to the top wall. The metal block is movable adjacent to the top wall, thereby driving the rigid link to drive the sliding block to slide towards the side opening along the sliding grooves until the sliding block triggers the electrical switch to generate a switching signal.

Abstract: A magnetic array with a bowl-shaped array of magnets oriented to induce a structured and oriented ionic flow towards a focal point. The magnets include a north pole and a south pole oriented to induce the ionic flow. Either poles face inwardly from the array to induce an ionic flow. Varying the size, dimensions, strength, and orientation of the magnets manipulates the ionic flow to a desired strength and velocity. The ionic flow increases in strength and concentration when in proximity to the narrow end. The ionic flow forces objects inside the array towards a hole in the narrow end.

Abstract: An inductor includes a core formed of a magnetic material and a foil winding wound at least partially around or through at least a portion of the core. A first end of the winding extends away from the core to form an extended output tongue configured and arranged to supplement or serve as a substitute for a printed circuit board foil trace. A second end of the winding forms a solder tab. At least a portion of the extended output tongue and the solder tab are formed at a same height relative to a bottom surface of the core. Another inductor includes a core formed of a magnetic material, a winding wound at least partially around or through at least a portion of the core, and a ground return conductor attached to the core. The core does not form a magnetic path loop around the ground return conductor.

Abstract: A fusible link unit includes a retaining portion that retains a frame portion of a battery. The frame portion is located at a corner portion of the battery. The retaining portion has a pair of leg portions which abut against two side surfaces forming the corner portion of the battery.

Abstract: The present invention relates to a system for controlling an air conditioner and method for controlling the same, and more particularly, to a system for controlling an air conditioner and method for controlling the same which can make real time control for maintaining system reliability, can make real time control of air conditioners while minimizing a network load to minimize a load on a server, and can prevent transmission and reception delay of a data.

Abstract: In general, techniques and systems for defining a gesture with a computing device using short-range communication are described. In one example, a method includes obtaining position information from an array of position devices using near-field communication (NFC) during a movement of the computing device with respect to the array, wherein the position information identifies unique positions within the array for each position device from which position information was obtained. The method may also include determining sequence information associated with the position information, wherein the sequence information is representative of an order in which the position information was obtained from each position device, and performing, by the computing device, an action based at least in part on the position information and the sequence information, wherein the position information and the sequence information are representative of a gesture input associated with the movement of the computing device.

Abstract: A system for providing wireless remote control over one or more devices. Included in the system is at least one wireless button that can be placed at various locations and which communicates with at least one sensor when the wireless button and sensor are brought within close proximity to one another. According to one embodiment, a wireless button can only be activated when the button is located within an authorized activation area. In another embodiment, a wireless button can only be activated by an authorized user. In yet a further embodiment, a wireless button can only be activated by an authorized user when the button is located within an authorized activation area.

Abstract: A monitoring network system includes: a plurality of monitoring apparatuses; and a remote monitoring apparatus, connected to the plurality of monitoring apparatuses. At least one of the monitoring apparatuses is configured to acquire biological signals from a patient and includes: a first holder, configured to hold a first ID; and a transmitter, configured to transmit the biological signal to the remote monitoring apparatus.

Abstract: The invention relates to electronic radiofrequency identification in the ultra-high frequency (UHF) range for marking an article (4) that is to be identified in a constraining environment. For this purpose, an electronic device (2) comprises: a dielectric substrate (12) having a peripheral edge face (13) and a ground face (15); an electronic chip (16); and a curved and short-circuited antenna (9) (PIFA) that presents a radiating area defined by at least two dipoles (19, 20). The antenna (9) on a transmission surface (14) of the substrate (12) is connected by a short-circuiting element (17) presenting a short-circuiting area presenting an area in projection on the edge face (13) that is of the order of 3% to 5% of the radiating area of the curved antenna (PIFA).

Abstract: In certain embodiments, an RFID tag comprises a memory module and one or more processing units. The memory module stores a subscriber identification number shared by the tag and one or more other tags for accessing a WWAN. Each tag is operable to access the WWAN using the subscriber identification number at a corresponding unique timeslot, the corresponding unique timeslot for a tag being distinct from the timeslots at which the other tags can access the WWAN using the subscriber identification number. The one or more processing units access the WWAN using the subscriber identification number to initiate a tag session at the corresponding unique timeslot for the tag. The corresponding unique timeslot for the tag is distinct from timeslots at which the other tags may access the WWAN using the subscriber identification number. The one or more processing units are operable to communicate tag information during the tag session at the corresponding unique timeslot for the tag.

Abstract: A method and device for selecting one or more transponders, in particular backscatter-based transponders, from a plurality of transponders by a base station, which method is based on a slotted ALOHA method, in which the base station defines numbered time slots and a random number generated in a given transponder determines a time slot when the transponder transmits its transponder-specific identification to the base station.

Abstract: In a data carrier (1) for contactless communication with a base station (2) across an electromagnetic field (HF) generated by the base station (2), coil voltage control means (16) are arranged for controlling the unmodulated coil voltage (US) of the received signal (ES), the coil voltage control means (16) being arranged for control in response to an essentially decreasing coil voltage (US) when the field strength of the electromagnetic field (HF) increases.