Patents Issued in January 28, 2014
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Patent number: 8638096Abstract: A computer implemented method for magnetic resonance imaging is provided. A 3D Fourier Transform acquisition is performed with two phase encode directions, wherein phase code locations are chosen so that a total number of phase encodes is less than a Nyquist rate, and closest distances between phase encode locations takes on a multiplicity of values. Readout signals are received through a multi-channel array of a plurality of receivers. An autocalibrating parallel imaging interpolation is performed and a noise correlation is generated. The noise correlation is used to weight a data consistency term of a compressed sensing iterative reconstruction. An image is created from the autocalibration parallel imaging using the weighted data consistency term. The image is displayed.Type: GrantFiled: October 19, 2010Date of Patent: January 28, 2014Assignee: The Board of Trustees of the Leland Stanford Junior UniversityInventors: Tao Zhang, Michael Lustig, John M. Pauly, Shreyas S. Vasanawala
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Patent number: 8638097Abstract: A method for generating magnetic resonance (MR) images or MR spectra of at least one partial area of a moving object with at least one motion sequence that is repeated during consecutive motion states is proposed. In a learning measurement, a monitor signal of the repeating motion sequence is recorded, and MR test data of the partial area of the object are recorded under known measurement conditions, wherein the MR test data is associated with the motion states of the motion sequence. In an evaluation step, the MR test data of the motion states of the motion sequence are compared to each other with respect to at least one parameter, and the variation of the at least one parameter over the motion sequence is determined.Type: GrantFiled: February 3, 2011Date of Patent: January 28, 2014Inventor: Arno Nauerth
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Patent number: 8638098Abstract: In a magnetic resonance method and apparatus, a series of magnetic resonance exposures of an examination subject is generated by implementing multiple first measurements (data acquisitions) with variation of a measurement parameter from acquisition-to-acquisition, which strongly influences a contrast of the first material type excited in the first measurements, implementing multiple second measurements in which a second material type is essentially selectively imaged that is less contrast-dependent with regard to this measurement parameter in a processor calculating spatial correction values for image data of the first measurements based on spatial differences between image data of different second measurements, and, also in the processor, spatially correcting image data of the first measurements (Di) and/or registration of image data of different first measurements to one another on the basis of the correction values.Type: GrantFiled: September 13, 2011Date of Patent: January 28, 2014Assignee: Siemens AktiengesellschaftInventor: Thorsten Feiweier
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Patent number: 8638099Abstract: A method for reducing magnetic resonance temperature measurement errors, which is used for the high-intensity focused ultrasound device for monitoring magnetic resonance imaging includes obtaining a magnetic resonance phase diagram as a reference image before the high-intensity focused ultrasound device heats the heating area; obtaining another magnetic resonance phase diagram as a heating image during or after the heating process of the high intensity focused ultrasound device; calculating the temperature changes in the heating area according to said heating image and reference image. The method further includes measuring the magnetic field changes caused by the position changes of the ultrasonic transducer of said high-intensity focused ultrasound device, and then compensating for the temperature changes according to said magnetic field changes. The present invention can significantly reduce the temperature errors caused by the position changes of the ultrasonic transducer.Type: GrantFiled: May 31, 2011Date of Patent: January 28, 2014Assignee: Siemens AktiengesellschaftInventors: Cheng Ni, Xiao Dong Zhou
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Patent number: 8638100Abstract: An assembly for mounting and unmounting a surface coil of a magnetic resonance tomography apparatus includes an upper part, a lower part, a locking element to fix the upper part and the lower part to one another, and contact elements at the upper part and at the lower part. The contact elements at the upper part can be brought into an electrically conductive connection with contact elements at the lower part and the upper part and the lower part can be fixed to one another by a movement of the locking element.Type: GrantFiled: August 3, 2010Date of Patent: January 28, 2014Assignee: Siemens AktiengesellschaftInventor: Daniel Driemel
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Patent number: 8638101Abstract: In a method and device for compensating the insufficient homogeneity of a magnetic field in a magnetic resonance system, the spatial position and size of a basic magnetic field region and at least one additional magnetic field region in a field to be homogenized and determined. An optimization calculation is implemented on the basic magnetic field region and the at least one additional magnetic field region. A homogenized magnetic field at the main magnetic field region and the at least one additional magnetic field region is output according to the result of the optimization calculation.Type: GrantFiled: August 24, 2010Date of Patent: January 28, 2014Assignee: Siemens AktiengesellschaftInventors: Jin Jun Chen, Cheng Ni
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Patent number: 8638102Abstract: A parametric amplifier device has a two port parametric amplifier, a DC voltage generator and a DC bias regulator. The bias regulator has a voltage regulator, an attenuator and a summer. Output voltages from the regulator and the attenuator are added in the summer.Type: GrantFiled: April 2, 2010Date of Patent: January 28, 2014Assignee: Siemens AktiengesellschaftInventors: Peter Cork, Anthony Peter Hulbert, John Hunt
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Patent number: 8638103Abstract: The present disclosure relates to determining a property, such as resistivity, of an earth formation. A transmitter is disposed in a wellbore penetrating the formation, and a plurality of receivers are distributed on or near the earth's surface. The transmitter sends electromagnetic energy into the formation and the resulting signal, after passing through the formation, is detected by the array of receivers. The received signal is used to determine the property of the formation. This is often achieved using an inversion or numerical model of the formation being measured. The inversion takes into account changes in the background formation model due to transmitting from various locations. The measurements made on the formation can be performed while drilling the wellbore or subsequent to the drilling.Type: GrantFiled: October 21, 2009Date of Patent: January 28, 2014Assignee: Schlumberger Technology CorporationInventors: Richard Rosthal, Edward Nichols, John Lovell, Christopher Bogath
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Patent number: 8638104Abstract: A method for determining spatial distribution of fluid injected into a subsurface rock formation includes injecting the fluid into the rock formation. The fluid includes therein electrically conductive solid particles dispersed in an electrolyte. An electromagnetic response of the formation is measured. The measured electromagnetic response is used to determine spatial distribution of the injected fluid.Type: GrantFiled: June 17, 2010Date of Patent: January 28, 2014Assignee: Schlumberger Technology CorporationInventors: Thomas D. Barber, Barbara I. Anderson, Reza Taherian, Martin G. Luling
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Patent number: 8638105Abstract: A system and methods for cell telemetry are disclosed. An average magnetizing current in a sampling transformer is forced to about zero amperes by balancing volt-seconds using a voltage clamp mechanism. Furthermore, a pulse driven switch and a synchronized sampling switch are activated, and substantially simultaneously the voltage clamp mechanism deactivated.Type: GrantFiled: November 9, 2010Date of Patent: January 28, 2014Assignee: The Boeing CompanyInventor: Robert Matthew Martinelli
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Patent number: 8638106Abstract: A microdischarge-based pressure sensor that includes an anode, two cathodes, a drive circuit connected to the electrodes, and a measurement circuit that permits sensing of transient current pulses flowing through at least one of the electrodes. One of the cathodes is interposed between the anode and other cathode, and it includes a central opening which permits a microdischarge to occur between the anode and each cathode in response to applied voltage pulses from the drive circuit. Changes in relative current between the two cathodes are indicative of changes in ambient pressure in the microdischarge chamber. In other embodiments, a sealed chamber can be used with one of the electrodes acting as a diaphragm which deflects based on external pressure and changes its inter-electrode spacing, thereby altering the relative cathode currents.Type: GrantFiled: May 28, 2010Date of Patent: January 28, 2014Assignee: The Regents of the University of MichiganInventors: Yogesh B. Gianchandani, Scott Andrew Wright
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Patent number: 8638107Abstract: A transcapacitive sensing device has and ohmic seam which sections a plurality of transmitter electrodes and also sections a plurality of receiver electrodes. A processing system is communicatively coupled with the transmitter electrodes and the receiver electrodes and configured to: transmit a first transmitter signal with a first transmitter electrode disposed on a first side of the ohmic seam; transmit a second transmitter signal with a second transmitter electrode disposed on a second side of the ohmic seam; receive a first response corresponding to said first transmitter signal with a first receiver electrode disposed on the first side of the ohmic seam; and receive a second response corresponding to said second transmitter signal with a second receiver electrode disposed on the second side of the ohmic seam.Type: GrantFiled: December 16, 2010Date of Patent: January 28, 2014Assignee: Synaptics IncorporatedInventors: Adam Schwartz, Kirk Hargreaves, Joseph Kurth Reynolds, Richard R. Schediwy
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Patent number: 8638108Abstract: The present invention relates to a contact free arrangement for determining an absolute position of a member adapted for setting an amount of medicament to be injected from a medication delivery device, or adapted for determining an amount of medicament injected from a medication delivery device. The arrangement according to the present invention comprises at least one track of reflector means, at least one emitter means, and at least one receiver means. The at least one emitter means and the at least one receiver means are adapted to electrically couple to a number of the reflector means. The electrical coupling may be capacitive or inductive. In addition, the present invention relates to a medication delivery device or a syringe having such arrangement.Type: GrantFiled: September 22, 2006Date of Patent: January 28, 2014Assignee: Novo Nordisk A/SInventors: Preben Nielsen, Bodo von Munchow
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Patent number: 8638109Abstract: A capacitive sensing system having two or more capacitive sensors, one or more AC power sources for energizing the capacitive sensors, and a signal processing circuit for processing signals from the sensors. The sensors are arranged in pairs, wherein the one or more AC power sources are arranged to energize a first sensor of a pair of the sensors with an alternating current or voltage 180 degrees out of phase to a current or voltage for a second sensor of the pair of sensors, and wherein a pair of the sensors provides a measuring unit for a single measured distance value, the signal processing circuit receiving an output signal from each sensor of the pair and generating a measured value related to the average distance between the sensors of the pair and the target.Type: GrantFiled: December 23, 2010Date of Patent: January 28, 2014Assignee: Mapper Lithography IP B.V.Inventors: Guido De Boer, Johnny Joannes Jacobus Van Baar, Kaustubh Prabodh Padhye, Robert Mossel, Niels Vergeer, Stijn Willem Herman Karel Steenbrink
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Patent number: 8638110Abstract: There is provided a high resolution circuit for converting a capacitance-to-time deviation including a capacitance deviation detecting unit generating two detection signals having a phase difference corresponding to variations of capacitance of an micro electro mechanical system (MEMS) sensor; a capacitance deviation amplifying unit dividing frequencies of the two detection signals to amplify the phase difference corresponding to the capacitance deviation; and a time signal generating unit generating a time signal having a pulse width corresponding to the amplified phase difference.Type: GrantFiled: July 21, 2008Date of Patent: January 28, 2014Assignee: Electronics and Telecommunications Research InstituteInventors: Sung Sik Lee, Myung Lae Lee, Gunn Hwang, Chang Auck Choi
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Patent number: 8638111Abstract: A measurement system is disclosed for determining a sulfur concentration in a liquid, such as a liquid fuel. The measurement system includes a first electrode that is at least partially coated with zinc oxide and, more specifically, zinc oxide microstructures. The zinc oxide microstructures have a crystal lattice structure that is oriented in the (002) plane. The first electrode may be connected to an electrometer which, in turn, may be connected to a second electrode. The second electrode may be disposed on a common substrate with the first electrode or may be in the form of a plate disposed substantially parallel to the first electrode.Type: GrantFiled: January 20, 2012Date of Patent: January 28, 2014Assignee: Caterpillar Inc.Inventors: Douglas Alexander Rebinsky, Yong Tian, Orhan Altin, Xiaodong Liu
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Patent number: 8638112Abstract: An input device is disclosed, including a first drive electrode comprising a resistive material and a first sense electrode disposed proximate to the first drive electrode. The input device further includes a processing system which is coupled with the first drive electrode and the first sense electrode. In one embodiment, the processing system is configured for electrically driving a first end of the first drive electrode and electrically driving a second end of the first drive electrode to cause a change in a voltage gradient along a length of the first drive electrode. In such an embodiment, the change in the voltage gradient generates a first electrical signal in the first sense electrode. The processing system also acquires a first measurement of the first electrical signal and determines positional information along the length of the first drive electrode based upon the first measurement, wherein the positional information is related to an input object.Type: GrantFiled: September 10, 2010Date of Patent: January 28, 2014Assignee: Synaptics IncorporatedInventors: Shawn P. Day, Patrick Worfolk
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Patent number: 8638113Abstract: A wafer-scale probe card for temporary electrical contact to a sample wafer or other device, for burn-in and test. The card includes a plurality of directly metallized single-walled or multi-walled nanotubes contacting a pre-arranged electrical contact pattern on the probe card substrate. The nanotubes are arranged into bundles for forming electrical contacts between areas of the device under test and the probe card. The bundles are compressible along their length to allow a compressive force to be used for contacting the probe card substrate to the device under test. A strengthening material may be disposed around and/or infiltrate the bundles. The nanotubes forming the bundles may be patterned to provide a pre-determined bundle profile. Tips of the bundles may be metallized with a conductive material to form a conformal coating on the bundles; or metallized with a conductive material to form a continuous, single contact surface.Type: GrantFiled: May 4, 2010Date of Patent: January 28, 2014Assignee: FormFactor, Inc.Inventors: Douglas E. Crafts, Jyoti K. Bhardwaj
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Patent number: 8638114Abstract: A wafer test probe for testing integrated circuitry on a die is disclosed. The wafer test probe includes a membrane core. The wafer test probe also includes circuitry within the membrane core. The circuitry within the membrane core includes at least one portion of an inductor. The wafer test probe further includes a probe tip.Type: GrantFiled: December 8, 2009Date of Patent: January 28, 2014Assignee: QUALCOMM IncorporatedInventors: John T Josefosky, Yiwu Tang, Roger Hayward
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Patent number: 8638116Abstract: A probe card having a configurable structure for exchanging/swapping electronic components for impedance matching and an impedance method therefore are provided. In the probe card, an applied force is exerted on the electronic component so as to make the electronic component electrically connected with at least one conductive contact pad of a supporting unit. The supporting unit is a circuit board or a space transformer. In order to facilitate the exchange or swap of the electronic component, the applied force can be removed. The probe card includes a pressing plate which can be moved between a pressing position and a non-pressing position. The pressing plate has a pressing surface which is contacted with the top end of the electronic component while the pressing plate is in the pressing position. Therefore, the applied force can be generated or removed by changing the positioning of the pressing plate.Type: GrantFiled: March 10, 2011Date of Patent: January 28, 2014Assignee: MPI CorporationInventors: Chao-Ching Huang, Chih-Hao Ho, Wei-Cheng Ku
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Patent number: 8638117Abstract: Provided is a manufacturing apparatus that manufactures an integrated circuit package by packaging an integrated circuit chip, the manufacturing apparatus comprising a flattening section that flattens the integrated circuit chip; a holding section that holds a base substrate; a transporting section that transports the flattened integrated circuit chip to load the integrated circuit chip on the base substrate held by the holding section; and a packaging section that packages the integrated circuit chip and the base substrate as the integrated circuit package.Type: GrantFiled: September 9, 2010Date of Patent: January 28, 2014Assignee: Advantest CorporationInventors: Yoshinari Kogure, Seiichi Takasu, Sadaki Tanaka
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Patent number: 8638118Abstract: A wafer inspection device, which inspects the electrical properties of a semiconductor wafer on which a semiconductor integrated circuit is formed, and the wafer inspection device has: a holding mechanism for holding a probe card; a wafer stage that holds the semiconductor wafer on the upper surface and is movably provided; and a pressing mechanism that are held and press the wafer stage against the probe card. The wafer stage is provided on the outer periphery with a seal ring. The seal ring forms a sealed space in a state where the wafer and the probe card are brought close to each other by contacting the probe card and is provided in such a manner as to reduce the pressure of the sealed space.Type: GrantFiled: February 13, 2013Date of Patent: January 28, 2014Assignee: Panasonic CorporationInventors: Yoshirou Nakata, Satoshi Sasaki
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Patent number: 8638119Abstract: Some embodiments of the invention provide a configurable integrated circuit (IC). The IC includes a logic circuit for receiving input data sets and configuration data sets and performing several functions on the input data sets. Each configuration data set specifies a particular function that the logic circuit has to perform on the input data set. The IC also includes a connection circuit for supplying sets of the configuration data to the logic circuit at a particular rate for at least a particular time period. At least two supplied configuration data sets are different and configure the logic circuit to perform two different functions on the input data.Type: GrantFiled: May 21, 2012Date of Patent: January 28, 2014Assignee: Tabula, Inc.Inventors: Herman Schmit, Michael Butts, Brad L. Hutchings, Steven Teig
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Patent number: 8638120Abstract: Aspects of the invention provide for improving a success rate of an engineering design change (ECO) for an integrated circuit. In one embodiment, aspects of the invention include a method for improving a success rate of an engineering design change (ECO) for an integrated circuit, including: identifying a plurality of spare latches within the integrated circuit; determining an input driver for each of the spare latches; and replacing each input driver with a programmable gate array, such that the programmable gate array is programmed to a functionality of the input driver.Type: GrantFiled: September 27, 2011Date of Patent: January 28, 2014Assignee: International Business Machines CorporationInventors: Ashish Jaitly, Sridhar H. Rangarajan, Thomas E. Rosser
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Patent number: 8638121Abstract: A device is disclosed herein, which may be used a level-shift circuit. The device includes first, second and third power supply lines supplied respectively with first, second and third power voltages that are different from one another, first and second input terminals and an output terminal, an output circuit coupled to the first power supply line, the first and second input terminals and the output terminal, a first inverter including an input node coupled to the first input terminal and an output node coupled to the second input terminal, a first transistor coupled in series to the first inverter between the second and third power supply lines, the first transistor being rendered non-conductive to deactivate the first inverter, and a control circuit configured to prevent the output terminal from being brought into an electrical floating state during deactivation of the first inverter.Type: GrantFiled: March 23, 2012Date of Patent: January 28, 2014Inventors: Takamasa Suzuki, Akira Kotabe, Tomonori Sekiguchi, Riichiro Takemura
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Patent number: 8638122Abstract: A metastability-hardened storage circuit includes at least one inverting circuit. The inverting circuit has a logical input. The logical input of the inverting circuit is split into a pair of physical inputs.Type: GrantFiled: April 18, 2011Date of Patent: January 28, 2014Assignee: Altera CorporationInventors: Bruce B. Pedersen, Sivaraman Chokkalingam
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Patent number: 8638123Abstract: A circuit in which a storage function and an arithmetic function are combined is proposed by using a transistor with low off-state current for forming a storage element. When the transistor with low off-state current is used, electric charge can be held, for example, in a node or the like between a source or a drain of the transistor with low off-state current and a gate of another transistor. Thus, the node or the like between one of the source or the drain of the transistor with low off-state current and the gate of the another transistor can be used as a storage element. In addition, leakage current accompanied by the operation of an adder can be reduced considerably. Accordingly, a signal processing circuit consuming less power can be formed.Type: GrantFiled: May 16, 2012Date of Patent: January 28, 2014Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Tatsuya Ohnuki
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Patent number: 8638124Abstract: A clock phase shift detector circuit may include a phase detector for generating a phase signal based on a phase difference between first and second clock signals. A current mirror having a first, a second, and a third integrator may be coupled to the phase detector, whereby the first integrator integrates the first clock signal and generates a first voltage, the second integrator integrates the first clock signal and generates a second voltage, and the third integrator integrates the phase signal and generates a third voltage. A first comparator receives the first and the third voltage, and generates a first control signal. A second comparator receives the second and the third voltage, and generates a second control signal. The first and second control signals may detect a change between the phase difference of the first and the second clock signal and an optimized phase difference.Type: GrantFiled: December 7, 2012Date of Patent: January 28, 2014Assignee: International Business Machines CorporationInventors: Kai D. Feng, Jon-ru Guo, Trushil N. Shah, Ping-Chuan Wang, Zhijian Yang
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Patent number: 8638125Abstract: A low voltage differential signal (LVDS) driver circuit with reduced power consumption. A pre-driver stage, implemented as a differential current mode amplifier, is driven by the differential input signal and provides a corresponding differential drive signal, which drives the output stage, implemented as a differential voltage mode amplifier, which, in turn, provides the differential output signal for the load. Total current consumption equals the load current, which is provided by the output stage, plus a much smaller current used by the pre-driver stage.Type: GrantFiled: June 14, 2011Date of Patent: January 28, 2014Assignee: Texas Instruments IncorporatedInventors: Khaldoon Abugharbieh, Jitendra Mohan, Ivan Duzevik
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Patent number: 8638126Abstract: The present invention discloses a rail-to-rail comparator. The rail-to-rail comparator includes: a positive voltage rail providing a positive supply voltage, a ground voltage rail providing a ground voltage, an input stage, and an output stage. The input stage includes: a positive and a negative input terminals for receiving a first input signal and a second input signal; a first differential amplifier circuit, which includes a pair of depletion NMOS transistors to generate a first pair of differential currents; and a second differential amplifier circuit, which includes a pair of native NMOS transistors to generate a second pair of differential currents. The output stage is coupled to the first differential amplifier circuit and the second differential amplifier circuit, and generates an output signal related to a difference between the first input signal and the second input signal.Type: GrantFiled: January 18, 2012Date of Patent: January 28, 2014Assignee: Richtek Technology Corporation, R.O.C.Inventors: Chieh-Min Lo, Tzu-Huan Chiu, Chien-Sheng Chen, Chien-Ping Lu
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Patent number: 8638127Abstract: Embodiments related to an undervoltage detector are described and depicted. An undervoltage detector is formed to detect a low input bias voltage with a voltage divider network including first and second series circuits of semiconductor devices coupled to terminals of the input bias voltage source, and a resistor voltage divider including first and second voltage divider resistors coupled in series with the first and second series circuits. A ratio representing the numbers of semiconductor devices in the series circuits is substantially equal to a ratio of resistances in the resistor voltage divider. The equality of the ratios may be corrected by the presence of other resistances in the undervoltage detector. The semiconductor devices are each coupled in a diode configuration. The first series circuit is coupled to a current mirror to provide a bias current for a comparator that produces an output signal for the undervoltage detector.Type: GrantFiled: November 29, 2010Date of Patent: January 28, 2014Assignee: STMicroelectronics (Shenzhen) R&D Co., LtdInventors: Ni Zeng, Da Song Lin
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Patent number: 8638128Abstract: Aspects of the disclosure provide a sampling circuit with reduced sampling distortions. The sampling circuit can include a switch and a first driving module configured to drive a first signal in response to an input signal onto a first channel terminal of the switch. The sampling circuit also can include a bootstrap module coupled to a control terminal of the switch and a second driving module coupled to the bootstrap module. The second driving module can be configured to drive a second signal in response to the input signal to the bootstrap module, such that the bootstrap module can vary a control voltage on the control terminal based on the input signal for turning on the switch and causing an output voltage on a second channel terminal of the switch to track the first signal on the first channel terminal of the switch.Type: GrantFiled: May 16, 2012Date of Patent: January 28, 2014Assignee: Marvell International Ltd.Inventor: Kenneth Thet Zin Oo
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Patent number: 8638129Abstract: A power circuit. One embodiment provides a circuit for driving a power transistor having a control electrode and a load path. The circuit includes a driver circuit configured to change the power transistor to a completely on or off state with the aid of a control signal supplied to the control electrode. A series circuit includes a semiconductor switching element and a capacitor. The series circuit is connected in parallel with the load path and the capacitor provides a supply voltage for the driver circuit.Type: GrantFiled: August 20, 2008Date of Patent: January 28, 2014Assignee: Infineon Technologies AGInventors: Peter Kanschat, Uwe Jansen, Gerald Deboy
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Patent number: 8638130Abstract: Low headroom line driver circuits are disclosed. In several embodiments, the line driver circuits include a first transistor, a second transistor, a third transistor and a fourth transistor, where the first transistor and second transistors; and the third and fourth transistors are matched, first and second matched impedances, first and second driver controls circuit configured to apply control signals to the gates of the first and second transistors; and the third and fourth transistors respectively. In addition, the first and third transistors; and the second and fourth transistors are configured as a pair of stacked transistors connected between the voltage supplies Vdd and Vss, the second and fourth transistors are configured as a pair of stacked transistors connected between the voltage supplies Vdd and Vss, the matched impedances are connected in series between nodes formed by the connection between the first and third transistors; and the second and fourth transistors.Type: GrantFiled: February 17, 2011Date of Patent: January 28, 2014Assignee: Entropic Communications, Inc.Inventor: Espen Olsen
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Patent number: 8638131Abstract: In examples, apparatus and methods are provided that mitigate buffer slew rate variations due to variations in output capacitive loading, a fabrication process, a voltage, and/or a temperature (PVT). An exemplary embodiment includes an inverting buffer having an input and an output, as well as an active resistance series-coupled with a capacitor between the input and the output. The resistance of the active resistance varies based on a variation in a fabrication process, a voltage, and/or temperature. The active resistance can be a passgate. In another example, a CMOS inverter's output is coupled to the input of the inverting buffer, and two series-coupled inverting buffers are coupled between the input of the CMOS inverter and the output of the inverting buffer.Type: GrantFiled: February 23, 2011Date of Patent: January 28, 2014Assignee: QUALCOMM IncorporatedInventors: Wilson J. Chen, Chiew-Guan Tan
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Patent number: 8638132Abstract: A transmission channel includes at least one high voltage buffer block having buffer transistors and respective buffer diodes, being electrically coupled between respective voltage reference terminals, these buffer transistors being also coupled to a clamping block, in turn including clamping transistors connected to at least one output terminal of this transmission channel through diodes coupled to prevent the body diodes of the clamping transistors from conducting. The transmission channel includes at least one reset circuit having diodes and being electrically coupled between circuit nodes of the high voltage buffer block and of the clamping block, these circuit nodes being in correspondence with conduction terminals of the transistors comprised into the high voltage buffer block and into the clamping block.Type: GrantFiled: June 29, 2012Date of Patent: January 28, 2014Assignee: STMicroelectronics S.r.l.Inventors: Sandro Rossi, Giulio Ricotti
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Patent number: 8638133Abstract: Disclosed is an electronic circuit. The electronic circuit includes a transistor having a control terminal to receive a drive signal, and a load path between a first and a second load terminal. A voltage protection circuit is coupled to the transistor, has a control input, is configured to assume one of an activated state and a deactivated state as an operation state dependent on a control signal received at the control input, and is configured to limit a voltage between the load terminals or between one of the load terminals and the control terminal. A control circuit is coupled to the control input of the voltage protection circuit and is configured to deactivate the voltage protection circuit dependent on at least one operation parameter of the transistor and when a voltage across the load path or a load current through the load path is other than zero.Type: GrantFiled: June 15, 2011Date of Patent: January 28, 2014Assignee: Infineon Technologies AGInventors: Steffen Thiele, Andreas Peter Meiser, Franz Hirler
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Patent number: 8638134Abstract: A gate drive circuit capable of operating at high speed and with low loss without erroneously operating the switching element is provided with a small number of components and a simple and easy circuit configuration. A primary side of a transformer is connected to an output terminal of a low-side gate drive circuit, and a secondary side of the transformer is connected to a gate input side of a high-side switching element. As a positive gate drive voltage is output from the low-side drive circuit, a negative voltage is applied between the gate and source of a high-side switching element, and a gate voltage is suppressed to be equal to or lower than a threshold value. Therefore, the high-side switching element maintains a turn-off state when the low-side switching element is turned on.Type: GrantFiled: August 31, 2011Date of Patent: January 28, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Kazuto Takao, Masamu Kamaga
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Patent number: 8638135Abstract: An integrated circuit includes first and second transistors, a switch, and a power-on reset (POR) circuit. The first transistor has a first current electrode, a second current electrode, and a control electrode. The second transistor has a first current electrode coupled to the second current electrode of the first transistor, a second current electrode, and a control electrode. The switch is for coupling the first and second transistors to receive a power supply voltage in response to an asserted bias control signal. The POR circuit has a latch-up detection circuit coupled to receive the power supply voltage and to a control terminal of the switch. The latch-up detection circuit is for detecting a low voltage condition of the power supply voltage, and in response, deasserting the bias control signal to decouple the first and second transistors from the power supply voltage.Type: GrantFiled: October 13, 2011Date of Patent: January 28, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Jose A. Camarena, Dale J. McQuirk, Miten H. Nagda
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Patent number: 8638136Abstract: A switching voltage regulator system and method for providing a start-up mode. An on-chip voltage regulator can be integrated with an on-chip digital logic circuit to provide a core supply voltage to the on-chip digital logic circuit along with an off-chip inductor and capacitor. A clock less start-up circuit automatically operates the on-chip voltage regulator in a start-up mode in order to maintain an equilibrium voltage supply with respect to the on-chip digital logic circuit. Such clock less start-up circuit provides soft start-up operation with respect to the on-chip voltage regulator without a clock signal.Type: GrantFiled: December 28, 2010Date of Patent: January 28, 2014Assignee: LSI CorporationInventors: Prasad Sawarkar, Srinivas Reddy Chokka
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Patent number: 8638137Abstract: A semiconductor device includes a delay unit configured to delay an inputted clock to generate a delay clock, a selection unit configured to select and output one of the inputted clock and the delay clock, a delay locked loop configured to perform a delay locking operation using a signal delivered from the selection unit, and a selection control unit configured to control the selection unit in response to a comparison of one period of the inputted clock and a maximum delay value of the delay locked loop.Type: GrantFiled: April 17, 2012Date of Patent: January 28, 2014Assignee: Hynix Semiconductor Inc.Inventor: Jin Il Chung
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Patent number: 8638138Abstract: Methods, systems, and circuits for forming and operating a global hierarchical clock tree are described. The global hierarchical clock tree may comprise a clock circuit that operates to provide clock signals to a core circuit surrounded by the clock circuit. The clock circuit may include two or more first and second clock generator modules to generate a first and a second set of clock signals, respectively. The first and second clock modules may be located so that the first set of clock signals experience approximately equal first latencies and the second set of clock signals experience approximately equal second latencies. Additional methods, systems, and circuits are disclosed.Type: GrantFiled: September 14, 2009Date of Patent: January 28, 2014Assignee: Achronix Semiconductor CorporationInventors: Ravi Sunkavalli, Rahul Nimaiyar, Ravi Kurlagunda, Vijay Bantval
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Patent number: 8638139Abstract: A phase locked loop (PLL) based frequency sweep generator and methods for performing a frequency sweep are disclosed. In one implementation, the frequency sweep generator includes a circuit configured to generate a signal having a saw-tooth wave frequency ramp. The saw-tooth wave frequency ramp includes a rising portion and a resetting portion. The resetting portion has a shorter duration than the rising portion and includes a plurality of steps for decrementing the frequency of the signal.Type: GrantFiled: September 9, 2011Date of Patent: January 28, 2014Assignee: Analog Devices, Inc.Inventors: Michael Keaveney, Patrick Walsh
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Patent number: 8638140Abstract: A phase locked loop (PLL) circuit including a phase comparator for comparing a phase of a reference signal with a phase of a feedback signal, an oscillator for outputting an output signal at a frequency in accordance with an output of the phase comparator, a feedback loop for returning the output signal of the oscillator and supplying the output signal as the feedback signal, and a delay circuit for delaying the phase of the output signal output from the oscillator to a load circuit, wherein the delay circuit is provided outside the feedback loop.Type: GrantFiled: July 26, 2012Date of Patent: January 28, 2014Assignee: Spansion LLCInventor: Koji Okada
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Patent number: 8638141Abstract: A phase-locked loop for generating an output signal including a signal generator arranged to generate an output, a comparison unit arranged to compare the output with a reference signal so as to provide a digital signal, and a loop filter arranged to generate a control signal for controlling the signal generator in dependence on the digital signal. The loop filter includes a proportional path having a digital filter arranged to generate a first component of the control signal for controlling the phase of the output generated by the signal generator, and an analogue integral path arranged to generate a second component of the control signal for controlling the frequency of the output generated by the signal generator.Type: GrantFiled: August 30, 2012Date of Patent: January 28, 2014Assignee: Cambridge Silicon Radio LimitedInventors: Pasquale Lamanna, Nicolas Sornin, Davide Orifiamma, Cristian Pavao Moreira
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Patent number: 8638142Abstract: The present invention provides ABS precision improving means under ADPLL environment or environment close to the ADPLL environment and realizes shortening of process time of the ABS. In a digital frequency comparator in an ABS circuit, a DFF for storing an initial phase difference in a DPE signal output from a DPFD is prepared. Immediately after start of ABS operation, a DPE signal output from the DPFD is recorded as a signal expressing an initial phase difference in an internal circuit of the DPFD into the DFF. After that, the digital frequency comparator performs ABS by using a signal obtained by subtracting the initial phase error recorded in the DFF from an input DPE signal, thereby realizing high-speed and stabilized ABS operation.Type: GrantFiled: September 14, 2012Date of Patent: January 28, 2014Assignee: Renesas Electronics CorporationInventors: Ryo Endo, Jiro Shimbo, Tomomitsu Kitamura
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Patent number: 8638143Abstract: A phase locked loop frequency synthesizer comprises a voltage controlled oscillator; a loop filter for supplying a control voltage to the oscillator; a phase frequency detector arranged to detect a phase difference between a reference signal and a feedback signal generated from the oscillator signal and generate pulses on detector signals (UP/DN) dependent on the sign of the phase difference; and a charge pump (61) comprising current generating means and controlled switches (64, 65) arranged to convert pulses on the detector signals to current pulses from a reference voltage (Vdd?) to a common terminal (Vloop) connected to the loop filter or to current pulses from the common terminal to ground. The current generating means comprises at least one resistor (62, 63) connected between the common terminal and the switches, and the charge pump comprises an operational amplifier (66) coupled to keep the reference voltage at twice the voltage at the common terminal.Type: GrantFiled: November 16, 2010Date of Patent: January 28, 2014Assignee: ST-Ericsson SAInventors: Magnus Nilsson, Nikolaus Klemmer
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Patent number: 8638144Abstract: Systems and methods associated with control of clock signals are disclosed. In one exemplary implementation, there is provided a delay-lock-loop (DLL) and/or a delay/phase detection circuit. Moreover, such circuit may comprise digital phase detection circuitry, digital delay control circuitry, analog phase detection circuitry, and analog delay control circuitry. Implementations may include configurations that prevent transition back to the unlocked state due to jitter or noise.Type: GrantFiled: December 30, 2010Date of Patent: January 28, 2014Assignee: GSI Technology, Inc.Inventors: Jyn-Bang Shyu, Yoshinori Sato, Jae Hyeong Kim, Lee-Lean Shu
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Patent number: 8638145Abstract: A method and apparatus for synchronizing a delay line to a reference clock includes a delay line that receives a clock input signal based on a reference clock and outputs a delay edge signal according to a control adjustment. An injector receives a first rise edge of the reference clock and in response to a first trigger, sends the clock input signal to the delay line. A synchronizer determines that the rise edge has passed through the delay line, and in response, sends the injector a second trigger to send a next single fall edge of the clock input signal to the delay line. A charge pump determines a timing difference between the delay edge signal and a reference edge signal sent from the injector. The charge pump sends the control signal to the delay line to adjust the delay setting of the delay line based on the timing difference.Type: GrantFiled: June 21, 2012Date of Patent: January 28, 2014Assignee: Advanced Micro Devices, Inc.Inventor: Shawn Searles
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Patent number: 8638146Abstract: A method of measuring a phase difference for use in a phase locked loop (PLL) that includes a binary phase detector (BPD), a time-to-digital converter (TDC) and a signal generator, the phase difference being that between a reference signal and a generated signal output from the signal generator. The method includes inputting the reference signal and the generated signal into the TDC; measuring the magnitude of the phase difference at the TDC; if the measured magnitude of the phase difference is less than a threshold value, operating the PLL according to a first operational mode in which the output of the BPD controls the signal generator; and if the measured magnitude of the phase difference is greater than the threshold value, operating the PLL according to a second operational mode in which the output of the TDC and the BPD controls the signal generator.Type: GrantFiled: July 31, 2012Date of Patent: January 28, 2014Assignee: Cambridge Silicon Radio LimitedInventors: Pasquale Lamanna, Davide Orifiamma