Abstract: A component having a robust, but acoustically sensitive microphone structure is provided and a simple and cost-effective method for its production. This microphone structure includes an acoustically active diaphragm, which functions as deflectable electrode of a microphone capacitor, a stationary, acoustically permeable counter element, which functions as counter electrode of the microphone capacitor, and an arrangement for detecting and analyzing the capacitance changes of the microphone capacitor. The diaphragm is realized in a diaphragm layer above the semiconductor substrate of the component and covers a sound opening in the substrate rear. The counter element is developed in a further layer above the diaphragm. This further layer generally extends across the entire component surface and compensates level differences, so that the entire component surface is largely planar according to this additional layer.

Abstract: A spin MOSFET includes: a first ferromagnetic layer provided on a semiconductor substrate, and having a fixed magnetization direction perpendicular to a film plane; a semiconductor layer provided on the first ferromagnetic layer, including a lower face opposed to the upper face of the first ferromagnetic layer, an upper face opposed to the lower face, and side faces different from the lower and upper faces; a second ferromagnetic layer provided on the upper face of the semiconductor layer, and having a variable magnetization direction perpendicular to a film plane; a first tunnel barrier provided on the second ferromagnetic layer; a third ferromagnetic layer provided on the first tunnel barrier; a gate insulating film provided on the side faces of the semiconductor layer; and a gate electrode provided on the side faces of the semiconductor layer with the gate insulating film being interposed therebetween.

Abstract: A memory element includes a layered structure and a negative thermal expansion material layer. The layered structure includes a memory layer, a magnetization-fixed layer, and an intermediate layer. The memory layer has magnetization perpendicular to a film face in which a magnetization direction is changed depending on information, and includes a magnetic layer having a positive magnetostriction constant. The magnetization direction is changed by applying a current in a lamination direction of the layered structure to record the information in the memory layer. The magnetization-fixed layer has magnetization perpendicular to a film face that becomes a base of the information stored in the memory layer. The intermediate layer is formed of a non-magnetic material and is provided between the memory layer and the magnetization-fixed layer.

Abstract: A photovoltaic device including a semiconductor substrate having a first surface and a second surface, the second surface being opposite to the first surface; a first passivation layer on the first surface; and a second passivation layer on the second surface, wherein each of the first passivation layer and the second passivation layer comprises an aluminum-based compound, is disclosed. A method of preparing a photovoltaic device, the method including: forming a semiconductor substrate to have a first surface and a second surface, the second surface being opposite to the first surface; forming an emitter region and a back surface field (BSF) region at the second surface; and forming a first passivation layer on the first surface and a second passivation layer on the second surface, wherein the first passivation layer and the second passivation layer are formed concurrently, is also disclosed.

Abstract: A method includes forming a wafer assembly of a semiconductor wafer and a light transmissible optical wafer which are fixed to each other, cutting the wafer assembly at a spacer unit to individually divide the wafer assembly into a plurality of camera modules each comprising a sensor chip and a lens chip bonded to each other by a spacer, forming a light shieldable mask film to determine a lens aperture of each of plural lens units on the light transmissible optical wafer; forming a groove in the light transmissible optical wafer that reaches the spacer unit and filling the groove with a light shieldable resin to form a light shieldable resin layer; and cutting the light shieldable resin layer at a width less than the groove to individually divide the camera modules in each of which the light shieldable resin layer is provided at a side of the lens chip.

Abstract: A semiconductor device has first wiring layers and a plurality of dummy wiring layers that are provided on the same level as the first wiring layers. The semiconductor device defines a row direction, and first virtual linear lines extending in a direction traversing the row direction. The row direction and the first virtual linear lines define an angle of 2-40 degrees, and the dummy wiring layers are disposed in a manner to be located on the first virtual linear lines. The semiconductor device also defines a column direction perpendicular to the row direction, and second virtual linear lines extending in a direction traversing the column direction. The column direction and the second virtual linear lines define an angle of 2-40 degrees, and the dummy wiring layers are disposed in a manner to be located on the second virtual linear lines.

Abstract: A semiconductor light receiving element comprises: a substrate, a semiconductor layer of a first conductivity type formed on the substrate, a non-doped semiconductor light absorbing layer formed on the semiconductor layer of the first conductivity type, a semiconductor layer of a second conductivity type formed on the non-doped semiconductor light absorbing layer, and an electro-conductive layer formed on the semiconductor layer of the second conductivity type. A plurality of openings, periodically arrayed, are formed in a laminated body composed of the electro-conductive layer, the semiconductor layer of the second conductivity type, and the non-doped semiconductor light absorbing layer. The widths of the openings are less than or equal to the wavelength of incident light, and the openings pass through the electro-conductive layer and the semiconductor layer of the second conductivity type to reach the non-doped semiconductor light absorbing layer.

Abstract: According to one embodiment, a semiconductor device includes a semiconductor substrate, a first conductivity type region, a device isolation insulating film, a second conductivity type region, and a low concentration region. The first conductivity type region is formed in part of the semiconductor substrate. The device isolation insulating film is formed in an upper surface of the semiconductor substrate and includes an opening formed in part of an immediately overlying region of the first conductivity type region. The second conductivity type region is formed in the opening and is in contact with the first conductivity type region. The low concentration region is formed along a side surface of the opening, has second conductivity type, has an effective impurity concentration lower than an effective impurity concentration of the second conductivity type region, and separates an interface of the first conductivity type region and the second conductivity type region from the device isolation insulating film.

Abstract: An fabrication of three-dimensional integrated devices and three-dimensional integrated devices fabricated therefrom are described. A device side of a donor wafer is coated with a polymer film and exposure of a substrate side to an oxidizing plasma creates a continuous SiO2 film. Portions of the substrate side are selectively coated with a polymer film and etching of uncoated areas removes at least a substantial portion of the crystalline substrate. A plasma etch tool etches a crystalline substrate to within a pre-determined thickness. The silicon portions of the substrate side are etched by exposure to TMAH. After etching, the donor semiconductor wafer is supported by portions of the substrate that were not etched. The supporting structure allows flexing of the donor semiconductor wafer within the etched areas to enable conformality and reliable bonding to the device surfaces of an acceptor wafer to form a three dimensional integrated device.

Abstract: A semiconductor die includes a substrate, a first device region and a second device region. The first device region includes an epitaxial layer on the substrate and one or more semiconductor devices of a first type formed in the epitaxial layer of the first device region. The second device region is spaced apart from the first device region and includes an epitaxial layer on the substrate and one or more semiconductor devices of a second type formed in the epitaxial layer of the second device region. The epitaxial layer of the first device region is different than the epitaxial layer of the second device region so that the one or more semiconductor devices of the first type are formed in a different epitaxial layer than the one or more semiconductor devices of the second type.

Abstract: A semiconductor structure is formed with a NFET device and a PFET device. The NFET device is formed by masking the PFET device regions of a substrate, forming a screen layer through epitaxial growth and in-situ doping, and forming an undoped channel layer on the screen layer through epitaxial growth. The PFET device is similarly formed by masking the NFET regions of a substrate, forming a screen layer through epitaxial growth and in-situ doping, and forming an undoped channel layer on the screen layer through epitaxial growth. An isolation region is formed between the NFET and the PFET device areas to remove any facets occurring during the separate epitaxial growth phases. By forming the screen layer through in-situ doped epitaxial growth, a reduction in junction leakage is achieved versus forming the screen layer using ion, implantation.

Abstract: A shallow isolation trench structure and methods of forming the same wherein the method of formation comprises a layered structure of a buffer film layer over a dielectric layer that is atop a semiconductor substrate. The buffer film layer comprises a material that is oxidation resistant and can be etched selectively to oxide films. The layered structure is patterned with a resist material and etched to form a shallow trench. A thin oxide layer is formed in the trench and the buffer film layer is selectively etched to move the buffer film layer back from the corners of the trench. An isolation material is then used to fill the shallow trench and the buffer film layer is stripped to form an isolation structure. When the structure is etched by subsequent processing step(s), a capped shallow trench isolation structure that covers the shallow trench corners is created.

Abstract: An anti-fuse structure is provided in which an anti-fuse material liner is embedded within one of the openings provided within an interconnect dielectric material. The anti-fuse material liner is located between a first conductive metal and a second conductive metal which are also present within the opening. A diffusion barrier liner separates the first conductive metal from any portion of the interconnect dielectric material. The anti-fuse structure is laterally adjacent an interconnect structure that is formed within the same interconnect dielectric material as the anti-fuse structure.

Abstract: A structure and method for forming isolation and a buried plate for a trench capacitor is disclosed. Embodiments of the structure comprise an epitaxial layer serving as the buried plate, and a bounded deep trench isolation area serving to isolate one or more deep trench structures. Embodiments of the method comprise angular implanting of the deep trench isolation area to form a P region at the base of the deep trench isolation area that serves as an anti-punch through implant.

Abstract: The invention discloses a vertical parasitic PNP transistor in a BiCMOS process and manufacturing method of the same, wherein an active region is isolated by STIs. The transistor includes a collector region, a base region, an emitter region, pseudo buried layers, and N-type polysilicon. The pseudo buried layers, formed at the bottom of the STIs located on both sides of the collector region, extend laterally into the active region and contact with the collector region, whose electrodes are picked up through making deep-hole contacts in the STIs. The N-type polysilicon is formed on the base region and contacts with it, whose electrodes are picked up through making metal contacts on the N-type polysilicon. The transistors can be used as output devices in high-speed and high-gain circuits, efficiently reducing the transistors area, diminishing the collector resistance, and improving the transistors performance. The method can reduce the cost without additional technological conditions.

Abstract: A nitride semiconductor substrate is provided in which leak current reduction and improvement in current collapse are effectively attained when using Si single crystal as a base substrate. The nitride semiconductor substrate is such that an active layer of a nitride semiconductor is formed on one principal plane of a Si single crystal substrate through a plurality of buffer layers made of a nitride, in the buffer layers, a carbon concentration of a layer which is in contact with at least the active layer is from 1×1018 to 1×1020 atoms/cm3, a ratio of a screw dislocation density to the total dislocation density is from 0.15 to 0.3 in an interface region between the buffer layer and the active layer, and the total dislocation density in the interface region is 15×109 cm?2 or less.

Abstract: A method for making an actuator device includes providing a wafer comprising a layer of an electrically conductive material and forming a plurality of rotationally symmetrical dies in the electrically conductive material, each die including a plurality of radial tabs and complementarily sized radial recesses arranged in alternating fashion and at equal angular increments around the circumfery of the die. To maximize the use of available wafer space, the dies are arranged in a pattern on the wafer in which each die is rotated relative to adjacent dies through an angle of 360 degrees divided by twice the number of tabs or recesses on the die and, except for dies located at an outer periphery of the wafer, each die is disposed in edge-to-edge near abutment with an adjacent die and each tab of each die is nested within a complementary recess of an adjacent die.

Abstract: Semiconductor dice comprise at least one bond pad on an active surface of the semiconductor die. At least one blind hole extends from a back surface of the semiconductor die opposing the active surface, through a thickness of the semiconductor die, to an underside of the at least one bond pad. At least one quantity of passivation material covers at least a sidewall surface of the at least one blind hole. At least one conductive material is disposed in the at least one blind hole adjacent and in electrical communication with the at least one bond pad and adjacent the at least one quantity of passivation material.

Abstract: A semiconductor device is disclosed including an electromagnetic radiation shield. The device may include a substrate having a shield ring defined in a conductance pattern on a surface of the substrate. One or more semiconductor die may be affixed and electrically coupled to the substrate. The one or more semiconductor die may then be encapsulated in molding compound. Thereafter, a metal may be plated around the molding compound and onto the shield ring to form an EMI/RFI shield for the device.

Abstract: A power module includes a substrate including an insulating member and a patterned metallization on the insulating member. The patterned metallization is segmented into a plurality of spaced apart metallization regions. Adjacent ones of the metallization regions are separated by a groove which extends through the patterned metallization to the insulating member. A first power transistor circuit includes a first power switch attached to a first one of the metallization regions and a second power switch attached to a second one of the metallization regions adjacent a first side of the first metallization region. A second power transistor circuit includes a third power switch attached to the first metallization region and a fourth power switch attached to a third one of the metallization regions adjacent a second side of the first metallization region which opposes the first side. The second power transistor circuit mirrors the first power transistor circuit.

Abstract: The semiconductor device includes a tab including a chip supporting surface, and a back surface opposite to the chip supporting surface; a plurality of suspension leads supporting the tab; a plurality of leads arranged between the suspension leads; a semiconductor chip mounted on the chip supporting surface of the tab, the semiconductor chip including a main surface, a plurality of pads formed on the main surface, and a rear surface opposite to the main surface; a seal portion sealing the semiconductor chip such that a part of each of the leads is exposed from the seal portion; and a Pb-free solder formed on the part of each of the leads. A part of the rear surface of the semiconductor chip is contacted with the seal portion.

Abstract: In a QFP with a chip-stacked structure in which a lower surface of a die pad is exposed from a lower surface of a sealing member, a semiconductor chip having a BCB film, which is made of a polymeric material containing at least benzocyclobutene in its backbone as an organic monomer and formed on its surface, is mounted at a position (second stage) that is away from the die pad. As a result, even when moisture invades through the interface between the die pad and the sealing member, it is possible to prolong the time required for the moisture to reach the semiconductor chip, and subsequently to make moisture absorption defect less likely to occur.

Abstract: A method includes structuring a semiconductor substrate to produce a number semiconductor chips. Each of the semiconductor chips includes a first main face and a number of side faces. An indentation is formed at a transition between the first main face and the side faces.

Abstract: A microelectronic assembly can include first and second microelectronic elements each embodying active semiconductor devices adjacent a front surface thereof, and having an electrically conductive pad exposed at the respective front surface. An interposer of material having a CTE less than 10 ppm/° C. has first and second surfaces attached to the front surfaces of the respective first and second microelectronic elements, the interposer having a second conductive element extending within an opening in the interposer. First and second conductive elements extend within openings extending from the rear surface of a respective microelectronic element of the first and second microelectronic elements towards the front surface of the respective microelectronic element.

Abstract: A method of forming a semiconductor package having a large capacity and a reduced or minimized volume includes: attaching a semiconductor substrate on a support substrate using an adhesive layer, wherein the semiconductor substrate includes a plurality of first semiconductor chips and a chip cutting region, wherein first and second ones of the plurality of first semiconductor chips are separated each other by the chip cutting region, and the semiconductor substrate includes a first surface on which an active area is formed and a second surface opposite to the first surface; forming a first cutting groove having a first kerf width, between the first and second ones of the plurality of first semiconductor chips, so that the semiconductor substrate is separated into a plurality of first semiconductor chips; attaching a plurality of second semiconductor chips corresponding to the first semiconductor chips, respectively, to the plurality of first semiconductor chips; forming a molding layer so as to fill the first

Abstract: An embodiment of the present invention relates to a chip package and fabrication method thereof, which includes a chip protection layer or an additional etching stop layer to cover conducting pads to prevent dicing residue from damaging or scratching the conducting pads. According to another embodiment, a chip protection layer, an additional etching stop layer formed thereon, or a metal etching stop layer level with conducting pads or combinations thereof may be used when etching an intermetal dielectric layer at a structural etching region and a silicon substrate to form an opening for subsequent semiconductor manufacturing processes.

Abstract: A semiconductor device includes a housing made of a thermoplastic resin and having an internal space that is opened on one side and an inner wall portion that has an inner peripheral surface defining the internal space; and a core portion engaged in the internal space of the housing. The core portion includes a substrate, a semiconductor element mounted on the substrate, a wire electrically connecting the substrate and the semiconductor element, and a mold resin sealing the substrate, the semiconductor element and the wire. The core portion has a side surface provided with a convex portion that is in contact with the inner peripheral surface of the inner wall portion. Accordingly, a semiconductor device allowing a lengthened life and improved productivity, and a method of manufacturing the semiconductor device can be provided.

Abstract: A semiconductor die substrate panel is disclosed including a minimum kerf width between adjoining semiconductor package outlines on the panel, while ensuring electrical isolation of plated electrical terminals. By reducing the width of a boundary between adjoining package outlines, additional space is gained on a substrate panel for semiconductor packages.

Abstract: A microelectronic component package includes a plurality of electrical leads which are coupled to a microelectronic component and which have exposed lengths extending outwardly beyond a peripheral edge of an encapsulant. A plurality of terminals may be positioned proximate a terminal face of the encapsulant and these terminals may be electrically coupled to the same leads. This can facilitate connection of the microelectronic component to a substrate using the leads as a conventional leaded package. The terminals, however, can facilitate stacking of the leaded package with one or more additional microelectronic components, e.g., a BGA package.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a die attach pad integrally connected to a connector portion and a lead; attaching an integrated circuit die to the die attach pad; connecting an internal interconnect to the integrated circuit die and the lead; forming an encapsulation over the integrated circuit die; removing the connector portion to separate the die attach pad and the lead; and forming an isolation cover between the die attach pad and the lead.

Abstract: A semiconductor device includes a semiconductor die. The semiconductor die includes a first bond pad having a plurality of connection points, the first bond pad arranged on a first portion of the semiconductor die, wherein the first portion corresponds to an outer periphery of the semiconductor die, and a second bond pad and a third bond pad arranged within a second portion of the semiconductor die, wherein the second portion is within the outer periphery of the semiconductor die. A lead external to the semiconductor die is configured to provide a voltage potential to the semiconductor die. A first lead wire is connected between the lead and a first connection point. A second lead wire is connected between the second bond pad and a second connection point. A third lead wire is connected between the third bond pad and a third connection point.

Abstract: A semiconductor device in which a semiconductor chip, a lead frame and metal wires for electrically connecting the lead frame are sealed with sealing resin. The lead frame has a plurality of lead terminal portions, a supporting portion for supporting the semiconductor chip, and hanging lead portions supporting the supporting portion. Each of the lead terminal portions adjacent to the hanging lead portion is a chamfered lead terminal portion having, at its head, a chamfered portion formed substantially in parallel with the hanging lead portion so as to avoid interference with the hanging lead portion.

Abstract: A method and apparatus of packaging a semiconductor device with a clip is disclosed. The clip defines a first contact region and a second contact region on a same face of the at least one clip. The chip defines a first face, and a second face opposite to the first face, the first contact region being attached to the first face of the chip and the second contact region being located within a same plane with the second face of the clip.

Abstract: A system-in-a-package based flash memory card including an integrated circuit package occupying a small overall area within the card and cut to conform to the shape of a lid for the card. An integrated circuit may be cut from a panel into a shape that fits within and conforms to the shape of lids for a finished memory card, such as for example an SD Card. The integrated circuit package may be a system-in-a-package, a multi-chip module, or other arrangement where a complete electronic system is formed in a single package.

Abstract: A semiconductor device includes a semiconductor chip having a first main surface and a second main surface; a stacked structure on which the semiconductor chip is disposed; and a cooling body on which the stacked structure is disposed. The stacked structure includes a first thermal conductor fixed to the cooling body, an insulator disposed on the first thermal conductor, and a second thermal conductor disposed on the insulator and having the semiconductor chip disposed thereon. The first main surface of the semiconductor chip opposite to the second main surface in contact with the stacked structure is sealed with an insulation material. At least a part of the first thermal conductor protrudes outwardly of the insulation material in plan view.

Abstract: An assembly includes an integrated circuit die coupled to another component of the assembly with an alkali silicate glass material. The alkali silicate material may include particles for modifying the thermal, mechanical, and/or electrical characteristics of the material.

Abstract: According to an exemplary embodiment, a dual compartment semiconductor package includes a conductive clip having first and second compartments. The first compartment is electrically and mechanically connected to a top surface of the first die. The second compartment electrically and mechanically connected to a top surface of a second die. The dual compartment semiconductor package also includes a groove formed between the first and second compartments, the groove preventing contact between the first and second dies. The dual compartment package electrically connects the top surface of the first die to the top surface of the second die. The first die can include an insulated-gate bipolar transistor (IGBT) and the second die can include a diode. A temperature sensor can be situated adjacent to, over, or within the groove for measuring a temperature of the dual compartment semiconductor package.

Abstract: A semiconductor fabrication technique cuts loops formed in a spacer pattern. The spacer pattern is a split loop pattern which generally includes a symmetric arrangement of one or more loops in each of four quadrants which are defines with respect to a reference point. The loops can be peaks or trenches. Each quadrant can include one loop, or multiple nested loops. Further, the space pattern includes a single cross, or multiple nested crosses, which extend between the loops. A cut out area is defined which extends outward from the reference point to closed ends of the loops, also encompassing a central portion of the cross. When a metal wiring layer pattern is formed using the spacer pattern with the cut out area, metal wiring is excluded from the cut out area. The loop ends in the metal wiring layer are broken and can be used as independent active lines.

Abstract: An integrated circuit (IC) product includes a redistribution layer (RDL) having at least one conductive layer configured to distribute electrical information from one location to another location in the IC. The RDL also includes a plurality of wire bond pads and a plurality of solder pads. The plurality of solder pads each includes a solder wettable material that is in direct electrical communication with the RDL.

Abstract: A semiconductor device has a substrate having a first plurality of substrate bonding pads disposed on a bonding surface thereof. A plurality of semiconductor dice is disposed on the substrate. Each die of the plurality of dice has a first plurality of die bonding pads arranged along at least one first edge thereof. A plurality of bonding pillars extends substantially vertically from the substrate bonding pads. Each bonding pillar electrically connects one of the first plurality of substrate bonding pads to a corresponding one of the first plurality of die bonding pads. A method of assembling a semiconductor device is also described.

Abstract: A method for electrically coupling an anti-tamper mesh to an electronic module or device using wire bonding equipment and a device made from the method. Stud bumps or free air ball bonds are electrically coupled to conductive mesh pads of an anti-tamper mesh. Respective module pads have a conductive epoxy disposed thereon for the receiving of the stud bumps or free air ball bonds, each of which are aligned and bonded together to electrically couple the anti-tamper mesh to predetermined module pads.

Abstract: A semiconductor device which includes a first semiconductor chip 10, a first electrode 12 formed on the first semiconductor chip 10, a second semiconductor chip 20 to which the first semiconductor chip 10 is mounted, a second electrode 22 with a protrusion 24, which is formed on the second semiconductor chip 20, and a solder bump 14 which bonds the first electrode 12 and the second electrode 22 to cover at least a part of a side surface of the protrusion 24, and a method for manufacturing thereof are provided.

Abstract: Various embodiments of semiconductor assemblies with multi-level substrates and associated methods of manufacturing are described below. In one embodiment, a substrate for carrying a semiconductor die includes a first routing level, a second routing level, and a conductive via between the first and second routing levels. The conductive via has a first end proximate the first routing level and a second end proximate the second routing level. The first routing level includes a terminal and a first trace between the terminal and the first end of the conductive via. The second routing level includes a second trace between the second end of the conductive via and a ball site. The terminal of the first routing level and the ball site of the second routing level are both accessible for electrical connections from the same side of the substrate.

Abstract: There is provided a semiconductor device comprising, a first metal pattern formed at a first metal level and extending in a first direction, a second metal pattern formed at the first metal level, extending in a second direction that is different than the first direction, and disposed on a side of the first metal pattern to be separated from the first metal pattern, a first via structure formed on the first metal pattern, a third metal pattern formed at a second metal level that is different than the first metal level and electrically connected to the first metal pattern by the first via structure, and a first pad electrically connected to the first metal pattern and a second pad electrically connected to the third metal pattern.

Abstract: A semiconductor device includes a semiconductor substrate and a via electrode. The via electrode has a first portion on the substrate and extends towards the substrate and has a plurality of spikes that extends from the first portion into the substrate, each of the spikes being spaced apart form one another.

Abstract: A semiconductor device includes a word line, a bit line crossing the word line, an active region arranged in an oblique direction at the word line and the bit line, and a contact pad contacting the active region, where the contact pad extends in the oblique direction.

Abstract: A package for a microelectronic element, such as a semiconductor chip, has a dielectric mass overlying the package substrate and microelectronic element and has top terminals exposed at the top surface of the dielectric mass. Traces extending along edge surfaces of the dielectric mass desirably connect the top terminals to bottom terminals on the package substrate. The dielectric mass can be formed, for example, by molding or by application of a conformal layer.

Abstract: A microelectronic package can include a substrate having a first surface and a plurality of substrate contacts at the first surface and a microelectronic element having a front surface and contacts arranged within a contact-bearing region of the front surface. The contacts of the microelectronic element can face the substrate contacts and can be joined thereto. An underfill can be disposed between the substrate first surface and the contact-bearing region of the front surface of the microelectronic element. The underfill can reinforce the joints between the contacts and the substrate contacts. A joining material can bond the substrate first surface with the front surface of the microelectronic element. The joining material can have a Young's modulus less than 75% of a Young's modulus of the underfill.

Abstract: A method of forming an integrated circuit device includes providing a substrate including an active device, forming a through silicon via into the substrate, forming a device contact to the active device, forming a conductive layer over the through silicon via and the device contact, and forming a connecting via structure for electrically connecting the conductive layer with the through silicon via. An integrated circuit device includes a through silicon via formed into a substrate silicon material, a conductive layer formed over the through silicon via, and a connecting via structure formed between the conductive layer and the through silicon via for electrically connecting the conductive layer with the through silicon via. The connecting via structure comprises a first series of via bars intersected with a second series of via bars.

Abstract: Microfeature workpieces having alloyed conductive structures, and associated methods are disclosed. A method in accordance with one embodiment includes applying a volume of material to a target location of a microfeature workpiece, with the volume of material including at least a first metallic constituent. The method can further include elevating a temperature of the volume of material while the volume of material is applied to the microfeature workpiece to alloy the first metallic constituent and a second metallic constituent so that the second metallic constituent is distributed generally throughout the volume of material. In further particular embodiments, the second metallic constituent can be drawn from an adjacent structure, for example, a bond pad or the wall of a via in which the volume of material is positioned.