Abstract: Address spaces are resized concurrent to accessing those address spaces. The size of an address space can be increased or decreased concurrent to performing read or write operations on the address space. Further, cache entries associated with an address space being decreased in size are purged.

Abstract: The invention provides a method of transferring data from a data array within a main memory of a computer to an accelerator for processing, the embodiment of the method comprising: at the accelerator, requesting data from the main memory and generating a data stream between the main memory and the accelerator, the generated data stream including data from the data array; and, using an offset to determine the scheduling of array elements within the generated data stream.

Abstract: A data transfer system includes: a processor; a main memory that is connected to the processor; a peripheral controller that is connected to the processor; and a peripheral device that is connected to the peripheral controller and includes a register set, wherein the peripheral device transfers data stored in the register set to a predetermined memory region of the main memory or the processor by a DMA (Direct Memory Access) transfer, and the processor reads out the data transferred to the memory region by the DMA transfer without accessing to the peripheral device.

Abstract: A method, computer program product, and computing system for combining a plurality of discrete IO write requests to form a combined IO write request, wherein the plurality of IO write requests define data to be written to a storage network. The combined IO write request is provided to a pseudo multi-write device included within the storage network.

Abstract: A system and method are provided for using queue status to manage power in a system-on-chip (SoC). Messages to be processed are accepted in an SoC with a plurality of selectively enabled processors, and queued. The message traffic can be from an external source via an input/output (IO) interface, or intra-SoC messages between processors. The number of queued messages is monitored and, in response to the number of queued messages exceeding a subscription threshold, one or more processors are enabled. Then, the queued messages are distributed to the enabled processors. Enabling a processor is defined by an action such as supplying power to an unpowered processor, increasing the power supply voltage levels to a processor, increasing the operating frequency of a processor, or a combination of the above-mentioned actions. Likewise, processors can be disabled in response to the number of queued messages falling below the subscription threshold.

Abstract: In one embodiment of the invention, a replaceable memory apparatus is disclosed. The replaceable memory apparatus includes a first rectangular multilayer printed circuit board having a first side and a second side opposite the first side; a first male pluggable electrical connector mounted to the first side near a first edge; a first female pluggable electrical connector mounted to the second side; and first non-volatile memory mounted to the first side and the second side. The first female pluggable electrical connector is coupled to the first male pluggable electrical connector to feed through first signals. The first non-volatile memory is coupled to the first female pluggable electrical connector and the first male pluggable electrical connector to receive the first signals.

Abstract: A diplex FPGA is utilized to fan out a single high speed host universal asynchronous receiver transmitter (“UART”) channel into a number of diplex UART channels. The diplex FPGA includes a microprocessor, memory, a host UART and a number of diplex UARTs. In operation, the microprocessor polls each of the UARTs in a “round robin” manner and accepts packets from the host UART for transmission downstream and from the diplex UARTs for transmission upstream.

Abstract: Apparatuses and methods of calibrating a memory interface are described. Calibrating a memory interface can include loading and outputting units of a first data pattern into and from at least a portion of a register to generate a first read capture window. Units of a second data pattern can be loaded into and output from at least the portion of the register to generate a second read capture window. One of the first read capture window and the second read capture window can be selected and a data capture point for the memory interface can be calibrated according to the selected read capture window.

Abstract: Various exemplary systems and methods for dividing a communications channel are disclosed. In at least some embodiments the method may comprise: coupling a plurality of storage devices to a communication channel, detecting whether the communication channel has been divided into multiple sub-channels, and coupling either a first backplane controller or a second backplane controller to the storage devices based on whether the communication channel has been divided.

Abstract: A method for bus arbitration is for use when working with multi-carrier modulation methods. Each user on a bus is assigned a unique address which identifies the user and which is transmitted upon each initiation of communication. The address is represented as a sequence of binary numerals, the number of bits of the binary numerals being equal to the number of carriers used in the multi-carrier modulation method. This sequence of binary numerals is transmitted successively for the arbitration via the multi-carrier modulation method, a user being eliminated from the arbitration when a further user at the same time has transmitted a binary numeral having higher priority. The transmission of the binary numeral may be repeated if the arbitration of the numeral does not lead to a result in one step. The method for bus arbitration may be used advantageously in a system for contactless energy supply. A redundant sending of phase-shifted signals reduces the failure rate because of random destructive interference.

Abstract: The present disclosure includes systems and techniques relating to customization of a bus adapter card. In some implementations, an apparatus includes a processor and a program memory, a bus adapter card coupled with the computing apparatus and configured to connect with a storage device, the bus adapter card comprising a cache memory and a controller to cache in the cache memory data associated with the storage device, where the program memory includes a driver to communicate with the bus adapter card responsive to requests corresponding to the storage device, and the driver is configured to modify its communications with the bus adapter card responsive to information provided separate from the requests.

Abstract: A portable control unit may be quickly coupled and decoupled from docking stations on a plurality of process system components, such as cylindrical grinding machines. The portable control unit may be used to control the process system component and receive and output data produced by the process system component. The ability to quickly couple and decouple the portable control unit may allow a single portable control unit to be used to control numerous process system components, thereby saving cost and space. Various communications interfaces and attachment mechanisms may be used to communicatively and mechanically couple the portable control unit to a docking station.

Abstract: Systems and methods for retrieving data stored on a peripheral storage device such as a magnetic tape drive or disk drive include string searching using the peripheral storage device resources without transferring data to the requesting host computer and transferring only data blocks with matching data to the associated host computer to conserve host resources and data channel and/or network bandwidth.

Abstract: A method of partitioning a data storage device that has a plurality of memory chips includes determining a number memory chips in the data storage device, defining, via a host coupled to the data storage device, a first partition of the data storage device, where the first partition includes a first subset of the plurality of memory chips, defining a second partition of the data storage device via the host where the second partition includes a second subset of the plurality of memory chips, such that the first subset does not include any memory chips of the second subset and wherein the second subset does not include any memory chips of the first subset.

Abstract: A hybrid drive is disclosed comprising a head actuated over a disk comprising a plurality of data tracks, where each data track comprises a plurality of data sectors. The hybrid drive further comprises a non-volatile semiconductor memory (NVSM) comprising a plurality of memory segments. When a write command is received from a host including write data, the write data is written to one of a disk cache and a NVSM cache, wherein the write data is eventually flushed to a non-cache area of the disk.

Abstract: A detachable storage device can comprise a ram cache, a device controller, and a storage system. The ram cache may be configured to receive data from a digital device. The device controller may be configured to transfer the data from the ram cache to the storage system. The storage system may be configured to store the data at a predetermined event.

Abstract: A computer memory, having one or more of a semiconductor memory device having an internal memory array comprising a plurality of semiconductor dynamic random access memory (DRAM) cells arranged in a matrix of rows and columns, and provided as a memory module rank of such memory devices arranged in an array on a DIMM of one or more of said semiconductor memory device on a substrate which can be coupled via a memory device data interface to a memory system as a memory subsystem, each of said memory device having a low power shut-down state that can be activated using a common memory data interface. Control of power to a DRAM issues over the data interface two commands to a DRAM power control command decode, a power-state program signal and a power-state reset signal as a power-state control commands to control the power state of said DRAM, and to activate for READ/WRITE a memory cell as a normal active or spare device.

Abstract: A CAM-based search engine is disclosed that reduces power consumption during a plurality of different search operations concurrently performed in a plurality of device pipelines by selectively applying one of a number of different power reduction techniques for each pipeline in response to configuration data indicating the type of search operation that is being performed in the pipeline.

Abstract: Method, apparatus, and computer program product embodiment for allocating a plurality of extents in a thinly provisioned computing storage environment are provided. In one such embodiment, subsequent to a write request and previous to entering a cache of the computing storage environment, a determination is made, for a logical extent, whether a real extent is available. Pursuant to determining the availability of the real extent, the logical extent is allocated to the real extent by updating system metadata associated with the logical extent.

Abstract: A computational device allocates a plurality of solid state disks to a plurality of redundant array of independent disk (RAID) ranks, wherein a different solid state disk is absent in each RAID rank of the plurality of RAID ranks. The computational device determines at least one selected solid state disk from the plurality of solid state disks, wherein the at least one selected solid state disk is estimated to have undergone a greater amount of wear in comparison to other solid state disks in the plurality of solid state disks. Relatively more data and parity information is written to those RAID ranks in which the at least one selected solid state disk is absent in comparison to those RAID ranks in which the at least one selected solid state disk is present.

Abstract: A system, method, apparatus, and computer-readable medium are described for providing redundancy in a storage system. According to one method, maps are generated and stored that define stripe patterns for storing data on the storage nodes of a storage cluster. The maps are defined such that when a new storage node is added to the cluster, no movement of data occurs between two storage nodes that existed in the cluster prior to the addition of the new storage node during re-striping, and such that the data stored on each storage node is mirrored on another storage node. Storage nodes may also be designated as an owner or a peer for each storage zone. Input/output operations received at an owner node are fielded directly and mirrored to the peer node, while input/output operations received at a peer node are redirected to the owner node for processing.

Abstract: Method and apparatus for optimally placing memory devices within a computer system. A memory controller may include circuitry configured to retrieve or one or more performance metrics a plurality of memory devices connected thereto. Based on the performance metrics and one or more predefined rules for placing memory devices, the circuitry may determine an optimal placement of the memory devices in the system.

Abstract: Embodiments for managing data in a hierarchical storage server storing data blocks of a database system comprising primary storage devices being in an active mode and secondary storage devices being in one of an active and passive mode are provided. In response to read and write requests for data blocks at logical storage locations, a block mapping device determines physical storage locations on the storage devices. Read requests switch over secondary storage devices to the active mode when they are in the passive mode. Write requests write data blocks only to the primary storage devices. Secondary storage devices that have not been accessed for a minimum activation time may be switched over from the active to the passive mode to save power consumption and cooling. Data migration and data recall policies control moving of data blocks between the primary and secondary storage devices and are primarily based on threshold values.

Abstract: According to one embodiment, an information processing apparatus includes a memory includes a buffer area, a first storage, a second storage and a driver. The buffer area is reserved in order to transfer data between the driver and a host system that requests for data writing and data reading. The driver is configured to write data into the second storage and read data from the second storage in units of predetermined blocks using the first storage as a cache for the second storage. The driver is further configured to reserve a cache area in the memory, between the buffer area and the first external storage, and between the buffer area and the second storage. The driver is further configured to manage the cache area in units of the predetermined blocks.

Abstract: Methods and apparatus for source operand collector caching. In one embodiment, a processor includes a register file that may be coupled to storage elements (i.e., an operand collector) that provide inputs to the datapath of the processor core for executing an instruction. In order to reduce bandwidth between the register file and the operand collector, operands may be cached and reused in subsequent instructions. A scheduling unit maintains a cache table for monitoring which register values are currently stored in the operand collector. The scheduling unit may also configure the operand collector to select the particular storage elements that are coupled to the inputs to the datapath for a given instruction.

Abstract: Embodiments of the invention are directed to reducing write amplification in a cache with flash memory used as a write cache. An embodiment of the invention includes partitioning at least one flash memory device in the cache into a plurality of logical partitions. Each of the plurality of logical partitions is a logical subdivision of one of the at least one flash memory device and comprises a plurality of memory pages. Data are buffered in a buffer. The data includes data to be cached, and data to be destaged from the cache to a storage subsystem. Data to be cached are written from the buffer to the at least one flash memory device. A processor coupled to the buffer is provided with access to the data written to the at least one flash memory device from the buffer, and a location of the data written to the at least one flash memory device within the plurality of logical partitions. The data written to the at least one flash memory device are destaged from the buffer to the storage subsystem.

Abstract: Systems and methods are disclosed for multi-threading computer systems. In a computer system executing multiple program threads in a processing unit, a first load/store execution unit is configured to handle instructions from a first program thread and a second load/store execution unit is configured to handle instructions from a second program thread. When the computer system executing a single program thread, the first and second load/store execution units are reconfigured to handle instructions from the single program thread, and a Level 1 (L1) data cache is reconfigured with a first port to communicate with the first load/store execution unit and a second port to communicate with the second load/store execution unit.

Abstract: A processor may include several processor cores, each including a respective higher-level cache, wherein each higher-level cache includes higher-level cache lines; and a lower-level cache including lower-level cache lines, where each of the lower-level cache lines may be configured to store data that corresponds to multiple higher-level cache lines. In response to invalidating a given lower-level cache line, the lower-level cache may be configured to convey a sequence including several invalidation packets to the processor cores via an interface, where each member of the sequence of invalidation packets corresponds to a respective higher-level cache line to be invalidated, and where the interface is narrower than an interface capable of concurrently conveying all invalidation information corresponding to the given lower-level cache line. Each invalidation packet may include invalidation information indicative of a location of the respective higher-level cache line within different ones of the processor cores.

Abstract: A system and method to optimize runahead operation for a processor without use of a separate explicit runahead cache structure. Rather than simply dropping store instructions in a processor runahead mode, store instructions write their results in an existing processor store queue, although store instructions are not allowed to update processor caches and system memory. Use of the store queue during runahead mode to hold store instruction results allows more recent runahead load instructions to search retired store queue entries in the store queue for matching addresses to utilize data from the retired, but still searchable, store instructions. Retired store instructions could be either runahead store instructions retired, or retired store instructions that executed before entering runahead mode.

Abstract: A mechanism for dynamically altering a request received at a hardware component is provided. The request is received at the hardware component, and the request includes a mode option. It is determined whether an action of the request requires an unavailable resource and it is determined whether the mode option is for the action requiring the unavailable resource. In response to the mode option being for the action requiring the unavailable resource, the action is automatically removed from the request. The request is passed for pipeline arbitration without the action requiring the unavailable resource.

Abstract: A system includes a cache and a processor. The processor is configured to utilize a first thread to continually determine a desired scan time for scanning the plurality of storage tracks in the cache and utilize a second thread to continually control an actual scan time of the plurality of storage tracks in the cache based on the continually determined desired scan time. One method includes utilizing a first thread to continually determine a desired scan time for scanning the plurality of storage tracks in the cache and utilizing a second thread to continually control an actual scan time of the plurality of storage tracks in the cache based on the continually determined desired scan time.

Abstract: One embodiment provides a cached memory system including a memory cache and a plurality of read-claim (RC) machines configured for performing read and write operations dispatched from a processor. According to control logic provided with the cached memory system, a hazard is detected between first and second read or write operations being handled by first and second RC machines. The second RC machine is suspended and a subset of the address bits of the second operation at specific bit positions are recorded. The subset of address bits of the first operation at the specific bit positions are broadcast in response to the first operation being completed. The second operation is then re-requested.

Abstract: Systems and methods for implementing a distributed shared memory (DSM) in a computer cluster in which an unreliable underlying message passing technology is used, such that the DSM efficiently maintains coherency and reliability. DSM agents residing on different nodes of the cluster process access permission requests of local and remote users on specified data segments via handling procedures, which provide for recovering of lost ownership of a data segment while ensuring exclusive ownership of a data segment among the DSM agents detecting and resolving a no-owner messaging deadlock, pruning of obsolete messages, and recovery of the latest contents of a data segment whose ownership has been lost.

Abstract: The method of operating the data storage device includes performing channel distribution non-sequentially based on a logical address included in a data signal and outputting a channel address, and at least one of writing data to and reading stored data from a memory connected to one of a plurality of channels based on the channel address.

Abstract: Circuits, methods, and apparatus that inhibit the collection or updating of page characteristics where such information is not useful. One example inhibits the updating of page usage information for pages that are to be kept resident in memory and not swapped to disk. The pages for which page usage or other characteristic updates are to be suppressed can be identified in a number of ways, including using a set range of addresses, bits in page directory entries, bits in page table entries, one or more address registers, or one or more segments.

Abstract: An information processing apparatus includes an operation detector that detects an operation performed on information, a history memory controller that controls a history memory such that the history memory stores as history information an operator and information, serving as an operation target, in a mapped state if the operation detector has detected the operation, an extractor that extracts from the history memory an operator having performed the operation if the operation detector has detected the operation, and a notifier that notifies the operator extracted by the extractor that the operation has been performed on the information.

Abstract: Computer readable media, methods and apparatuses are disclosed that may be configured for sequentially reading data of a file stored on a storage medium. The disclosure also provides for alternating transferring of fixed size portions of the file data to a first buffer and a second buffer, alternating processing of data blocks of the fixed sized portions in parallel from the first and second buffers by a plurality of processing threads, and outputting the processed data blocks.

Abstract: A memory protection unit (MPU) is configured to store a plurality of region descriptor entries, each region descriptor entry defining an address region of a memory, an attribute corresponding to the region, and an attribute override control corresponding to the attribute. A memory access request to a memory address is received and determined to be within a first address region defined by a first region descriptor entry and within a second address region defined by a second region descriptor entry. When the attribute override control of the first region descriptor entry indicates that override is to be performed, the value of the attribute of the first region descriptor entry is applied for the memory access. When the attribute override control of the second region descriptor entry indicates that override is to be performed, the value of the attribute of the second region descriptor entry is applied for the memory access.

Abstract: A core dump is processed to locate and optionally alter sensitive information. A core dump copy is created from at least a portion of an original core dump. Also, at least one input parameter is provided that corresponds to select information to be identified in the core dump copy and address information associated with the core dump copy is defined that corresponds to at least one of addresses where the select information can be altered and addresses where the select information should not be altered. Each occurrence of the select information located within the core dump copy is identified and optionally replaced with predetermined replacement data if the occurrence of the select information is within the addresses where the select information can be altered.

Abstract: A method, computer readable medium, and apparatus for creating and using backups which allow restoration of applications and/or specific content using volume image backup files. A directory of applications and application specific content is created which, along with metadata associated therewith, allows selection and restoration of such content using data stored in a volume image backup file, thereby reducing the time needed to create backups which are restorable at the application level.

Abstract: A storage apparatus connectable to another storage apparatus so as to copy the data thereto, for providing a first virtual volume including at least a first block, includes at least a storage unit having storage areas, each storage area being allocatable as a one of the first blocks; a memory storing information for indicating a relationship between each first block and each the storage area, at least one of the storage areas being allocated to the at least one of the first blocks according to a usage pattern of the first virtual volume; and a controller configured to receive an instruction for copying data, determine whether each first block is allocated to any of the storage areas or not in reference to the information, transmit data indicating that one of the first blocks is unallocated to any of the first storage areas on the basis of the determination.

Abstract: A storage apparatus providing a logical storage area for storing data to an external apparatus, includes a plurality of storage devices each providing a physical storage area for storing the data, the storage devices being different from each other in device property including data input/output performance, a capacity virtualization part managing the physical storage areas of the storage devices as unit physical storage areas each having a predetermined storage capacity and managing the unit physical storage areas in association with a plurality of unit logical storage areas forming the logical storage area, a tier controller managing the plurality of unit physical storage areas by classifying into a plurality of tiers the unit physical storage areas provided by the storage devices having the different device properties, and a redundant data management part managing redundant unit storage areas which are a plurality of the unit physical storage areas storing the same data.

Abstract: In a computer-implemented data storage system comprising at least one storage control and data storage, wherein data is stored in the form of volumes, at least a plurality of volumes having at least some freespace, and a grouping of a plurality of volumes comprises a pool. In response to a defragmentation request, the storage control initiates migration of data from a pool to generate additional freespace. Subsequent to the migration of data, fragmentation of data of the pool is computed, and the amount of existing freespace of the pool is determined. The amount of existing freespace is compared to a freespace threshold, where the freespace threshold is related to the computed fragmentation. If the comparison indicates the amount of freespace is below the threshold, spill volumes are added to the pool; and, else, the pool is kept intact without adding spill volumes. Then, defragmentation of the pool is initiated.

Abstract: A memory controller (MC) is associated with a remapping table to enable access to content in a memory system that includes asymmetric memory. The MC receives a request for a memory read or an Input/Output (I/O) write from a central processing unit (CPU) for a physical address specified by the system's memory management unit (MMU). The CPU uses the MMU to manage memory operations for the CPU, by translating the virtual addresses associated with CPU instructions into physical addresses representing system memory or I/O locations. The MC for asymmetric memories is configured to process the MMU-specified physical addresses as an additional type of virtual addresses, creating a layer of abstraction between the physical address specified by the MMU and the physical memory address with which that address is associated by the MC. The MC shields the CPU from the computational complexities required to implement a memory system with asymmetric components.

Abstract: Memory access requests are successively received in a memory request queue of a memory controller. Any conflicts or potential delays between temporally proximate requests that would occur if the memory access requests were to be executed in the received order are detected, and the received order of the memory access requests is rearranged to avoid or minimize the conflicts or delays and to optimize the flow of data to and from the memory data bus. The memory access requests are executed in the reordered sequence, while the originally received order of the requests is tracked. After execution, data read from the memory device by the execution of the read-type memory access requests are transferred to the respective requestors in the order in which the read requests were originally received.

Abstract: A memory device and method of programming the same comprising partitioning memory into two or more chunks of information. At least a first portion of a first of the information chunks can be programmed while concurrently determining whether a first portion of a second of the information chunks should be set or reset. Further, the first portion of the second information chunk can be sequential programmed following the programming of the first portion of the first information chunk. The memory device can include different types of memory, such as PCM memory.

Abstract: A method and system for dynamically allocating memory, the method comprising maintaining a record of allocated memory that should be considered free in a child process, and designating as free any copy of memory identified by the record and created in a forking process.

Abstract: A microcontroller in which respective CPUs execute different applications so as to improve processing performance, and the respective CPUs execute an application that requires safety and mutually compare the results thereof so as to enhance the reliability of write data is provided. The microcontroller has a plurality of processing systems made up of a first CPU, a second CPU, a first memory and a second memory, and for the instruction processing about specific processing set in advance, the write to peripheral modules which are not multiplexed is executed twice, and the write data of the first time and the second time are mutually collated.

Abstract: A determination is made as to whether a first indicator is configured to allow borrowing of storage space to a first type of storage pool from a second type of storage pool. In response to determining that the first indicator is configured to allow borrowing of storage space from the second type of storage pool, a logical unit is created in the second type of storage pool and a listener application is initiated. The listener application determines that free space that is adequate to store the logical unit has become available in the first type of storage pool. The logical unit is moved from the second type of storage pool to the first type of storage pool, in response to determining, via the listener application, that free space that is adequate to store the logical unit has become available in the first type of storage pool.

Abstract: A storage apparatus and method configured to improve efficiency of data access utilizing dynamically adjusting storage zone boundary within a disk are disclosed. A process capable of implementing the flexible zone boundary, in one example, allocates a first zone of a first disk operable to store data. While the first zone can be referred to as a Redundant Array of Independent Disks 0 (“RAID 0”) zone, the implementation of RAID 0 can be carried out in the first zone. Upon allocating a second zone of the first disk operable to store secured data, the process allocates a third zone of the first disk wherein the storage boundary of the first zone can be dynamically expanded into the third zone in response to the availability of free storage capacity of the first zone of the first disk.