Patents Issued in January 28, 2014
-
Patent number: 8639958Abstract: Embodiments of the invention relate to dynamic power management of storage volumes and disk arrays in a storage subsystem to mitigate loss of performance resulting from the power management. The volumes and arrays are prioritized, and in real-time power is selectively reduced in response to both the prioritization and an energy savings goal. A feedback loop is provided to dynamically measure associated power gain based upon a lowering of power consumption, and device selection may be adjusted based upon received feedback.Type: GrantFiled: July 7, 2011Date of Patent: January 28, 2014Assignee: International Business Machines CorporationInventors: Wendy A Belluomini, David D Chambliss, Joseph S. Glider, Himabindu Pucha, Rui Zhang
-
Patent number: 8639959Abstract: A first switch is arranged between a judgment unit and a signal line. The first switch is turned on during a period in which the judgment unit judges a device, after which the first switch is turned off. A second switch is turned off during a period in which the judgment unit judges the device, after which the second switch is turned on. The signal line connects a communication interface port, which allows various different kinds of devices to be connected, and a communication terminal of a processor configured to perform data communication with the device. The judgment unit monitors the electrical state of the signal line, and judges the device connected to the port.Type: GrantFiled: October 4, 2010Date of Patent: January 28, 2014Assignee: Rohm Co., Ltd.Inventor: Koichi Miyanaga
-
Patent number: 8639960Abstract: A data processing apparatus is provided comprising data processing circuitry configured to perform data processing operations. A plurality of state retention circuits forms part of the data processing circuitry and these circuits are configured to hold respective state values at respective nodes of the data processing circuitry it enters a low power mode. One or more scan paths connect the plurality of state retention circuits together in series, such that the state values may be scanned into and out of the respective nodes. A plurality of parity information generation elements are coupled to the scan path(s) and configured to generate parity information indicative of the respective state values held at those respective nodes by the state retention circuits.Type: GrantFiled: May 27, 2011Date of Patent: January 28, 2014Assignee: ARM LimitedInventors: David Walter Flynn, Sachin Satish Idgunji
-
Patent number: 8639961Abstract: A participant response system (50) comprises at least one host computer (52) and a plurality of battery-powered remote units (62) communicating wirelessly with the host computer (52). Each remote unit (62) executes a diagnostic routine in response to a received status request broadcast by the host computer (52) to detect the status thereof. Any remote unit (62) that detects an unhealthy state, returns health information to the host computer (52).Type: GrantFiled: January 10, 2008Date of Patent: January 28, 2014Assignee: SMART Technologies ULCInventors: Hannah Doerksen, Michael Boyle
-
Patent number: 8639962Abstract: A method, system, and software instructions for allocating power in a information handling system are operable to respond to a power profiling request by transitioning a processing resource to a first power consumption state and obtaining and storing a first power consumption value. The first power consumption value is then retrieved and used to allocate power to the first processing resource in response to a power on request. The first power consumption state may be a state in which power consumption approximates a maximum power consumption. The processing resource may be further transitioned to a second power consumption state and a second power consumption value obtained. The second power consumption state may be a reduced performance state. Thereafter, responsive to determining that the system lacks sufficient power budget to fulfill a pending request for power, the processing resource is throttled and power is allocated using the second power consumption value.Type: GrantFiled: March 6, 2013Date of Patent: January 28, 2014Assignee: Dell Products L.P.Inventors: Michael A. Brundridge, Alan Brumley
-
Patent number: 8639963Abstract: A system and method for indirect throttling of a system resource by a processor are disclosed. An information handling system includes a chassis that receives modular components, a processor disposed in the chassis and a system resource in communication with the processor. A management module associated with the chassis generates a throttle signal that throttles operation of the processor in response to receiving an alarm such that the processor reduces the throughput of the system resource.Type: GrantFiled: May 5, 2005Date of Patent: January 28, 2014Assignee: Dell Products L.P.Inventors: Michael A. Brundridge, Paul T. Artman, Bryan Krueger, Abhishek Mehta
-
Patent number: 8639964Abstract: In one aspect, a method for improving reliability and availability of an information handling system is disclosed. Operational data associated with an operating margin may be captured. A threshold specified by a pre-defined profile may be identified. The pre-defined profile may be useable in adjusting the operating margin. The captured operational data may be compared to the pre-defined threshold. A parameter specified by the pre-defined profile may be identified. The operation of a component of the information handling system may be modified based, at least in part, on the identified parameter specified by the pre-defined profile. The modification may result in adjusting the operating margin.Type: GrantFiled: March 17, 2010Date of Patent: January 28, 2014Assignee: Dell Products L.P.Inventors: Stuart Allen Berke, Mukund Purshottam Khatri
-
Patent number: 8639965Abstract: A message queue (MQ) failover handler receives a message and a configuration file from a client application. The configuration file provides an indication of which of a number of queue managers (QMs) is the first choice for receipt and delivery of the message to a server application. The configuration file also provides an indication of which of the QMs is the second choice for receipt and delivery of the message to the server application, should the first choice of the QMs be unavailable.Type: GrantFiled: July 20, 2011Date of Patent: January 28, 2014Assignee: Cellco PartnershipInventors: Sabitha Anugu, Shankar Kulkarni, Henry H. Li
-
Patent number: 8639966Abstract: A backup image generator can create a primary image and periodic delta images of all or part of a primary server. The images can be sent to a network attached storage device and a remote storage server. In the event of a failure of the primary server, the failure can be diagnosed to develop a recovery strategy. Based on the diagnosis, at least one delta image may be applied to a copy of the primary image to generate an updated primary image at either the network attached storage or the remote storage server. The updated primary image may be converted to a virtual server in a physical to virtual conversion at either the network attached storage device or remote storage server and users may be redirected to the virtual server. The updated primary image may also be restored to the primary server in a virtual to physical conversion. As a result, the primary data storage may be timely backed-up, recovered and restored with the possibility of providing server and business continuity in the event of a failure.Type: GrantFiled: May 1, 2012Date of Patent: January 28, 2014Assignee: DSSDR, LLCInventor: Andrew Bensinger
-
Patent number: 8639967Abstract: A controlling apparatus for controlling an information processing apparatus, the controlling apparatus includes a first controller including a first data transfer unit that communicates data between the information processing apparatus, and a first processing unit that generates a command to instruct the first data transfer unit to communicate data between the information processing apparatus, and a second controller including a second data transfer unit that communicates data between the information processing apparatus, and a second processing unit that generates a command to instruct the second data transfer unit to communicate data between the information processing apparatus.Type: GrantFiled: August 16, 2011Date of Patent: January 28, 2014Assignee: Fujitsu LimitedInventors: Tamaki Imakawa, Hitoshi Matsumori, Toshiharu Maekawa, Michio Numata, Satoru Sakai
-
Patent number: 8639968Abstract: Systems, methods, and computer-readable and executable instructions are provided for computing system reliability. A method for computing system reliability can include storing, on one of a plurality of devices, a checkpoint of a current state associated with the one of the plurality of devices. The method may further include storing the checkpoint in an erasure-code group across the plurality of devices.Type: GrantFiled: January 17, 2011Date of Patent: January 28, 2014Assignee: Hewlett-Packard Development Company, L. P.Inventors: Doe Hyun Yoon, Naveen Muralimanohar, Jichuan Chang, Parthasarathy Ranganathan, Norman Paul Jouppi
-
Patent number: 8639969Abstract: A storage system comprises a first storage device having a first plurality of hard disk drives and a first controller. The first controller stores data in the first plurality of hard disk drives by stripes. Each stripe includes M data and N parity data allocated to M+N hard disk drives of the first plurality of hard disk drives. A first hard disk drive includes data or parity data of both a first stripe of the stripes and a second stripe of the stripes, while a second hard disk drive includes data or parity data of only one of the first stripe or the second stripe. During data recovery involving failure of one of the first plurality of hard disk drives, the data in the failed hard disk drive is recovered for each stripe by calculation using data and parity data in other hard disk drives for each stripe.Type: GrantFiled: July 9, 2012Date of Patent: January 28, 2014Assignee: Hitachi, Ltd.Inventor: Tomohiro Kawaguchi
-
Patent number: 8639970Abstract: Disclosed is a method of detecting a product data error in a storage system. First and second vital product data (VPD) EEPROMs are read. Indicators of whether wither or both reads failed are received. Based on these indicators, the contents of the VPD EEPROMs may be compared. Based on a result of the comparing indicating a match, an arbitrary one of the VPD EEPROMS is used. Based on an indicator indicating an error with the first VPD EEPROM, the second VPD EEPROM is used.Type: GrantFiled: April 25, 2011Date of Patent: January 28, 2014Assignee: LSI CorporationInventor: Ashish Batwara
-
Patent number: 8639971Abstract: Maintaining consistency and freshness of information about an operational system, assuring consistent actions by system actors, assuring that system elements use only a single global status of the system for any particular status time, assuring that each pair of elements acts only upon consistent status values, assuring that system elements operate only with status values measured sufficiently recently to be reliable. Information collectors respond to status values. Information containers respond to information collectors, maintaining status values and metadata indicating whether those status values are reliable, or are consistent with respect to known correct values. Information conditions respond to information collectors or information containers, maintaining logical consistency with a unified global status. System actors respond to information containers or information conditions, acting logically consistent with that global status.Type: GrantFiled: February 17, 2011Date of Patent: January 28, 2014Assignee: Scale ComputingInventor: Philip White
-
Patent number: 8639972Abstract: Each of a plurality of image processing apparatuses includes a module storing unit that stores therein a registered function module and a backup unit that backs up the stored function module and restores a function module based on backup data of the function module. An external storage device stores therein the backup data of the function module. When an error occurs in a first image processing apparatus, the backup unit of a second image processing apparatus restores the function module corresponding to the first image processing apparatus based on the backup data of the function module stored in the external storage device.Type: GrantFiled: February 9, 2009Date of Patent: January 28, 2014Assignee: Ricoh Company, Ltd.Inventor: Mitsugu Matsushita
-
Patent number: 8639973Abstract: Some embodiments of the invention provide techniques whereby a user may perform a system reset (e.g., to address system performance and/or reliability degradation, such as which may be caused by unused applications that unnecessarily consume system resources, an attempted un-install of an application that left remnants of the application behind, and/or other causes). In some embodiments, performing a system reset replaces a first instance of an operating system on the system with a new instance of the operating system, and removes any applications installed on the system, without disturbing the user's data.Type: GrantFiled: December 14, 2010Date of Patent: January 28, 2014Assignee: Microsoft CorporationInventors: Desmond T. Lee, Vinit Ogale, Keshava Prasad Subramanya, Sri Sai Kameswara Pavan Kumar Kasturi, Hongliu Zheng, Yunan Yuan, Gregory W. Nichols, Stephan Doll, Kiran Kumar Dowluru, Calin Negreanu
-
Patent number: 8639974Abstract: A data management system (“DMS”) provides an automated, continuous, real-time, substantially no downtime data protection service to one or more data sources. A host driver embedded in an application server captures real-time data transactions, preferably in the form of an event journal. The driver functions to translate traditional file/database/block I/O and the like into a continuous, application-aware, output data stream. The host driver includes an event processor that can perform a recovery operation to an entire data source or a subset of the data source using former point-in-time data in the DMS. The recovery operation may have two phases. First, the structure of the host data in primary storage is recovered to the intended recovering point-in-time. Thereafter, the actual data itself is recovered. The event processor enables such data recovery in an on-demand manner, by allowing recovery to happen simultaneously while an application accesses and updates the recovering data.Type: GrantFiled: December 20, 2012Date of Patent: January 28, 2014Assignee: Dell Software Inc.Inventor: Siew Yong Sim-Tang
-
Patent number: 8639975Abstract: A data processing system 2 is used to perform processing operations to generate a result value. The processing circuitry which generates the result value has an error resistant portion 32 and an error prone portion 30. The probability of an error in operation of the error prone portion for a given set of operating parameters (clk, V) is greater than the probability of an error for that same set of operating parameters within the error resistant portion. Error detection circuitry 38 detects any errors arising in the error prone portion. Parameter control circuitry 40 responds to detected errors to adjust the set of operating parameters to maintain a non-zero error rate in the errors detected by the error detection circuitry. Errors within the one or more bits generated by the error prone portion are not corrected as the apparatus is tolerant to errors occurring within such bit values of the result value.Type: GrantFiled: November 17, 2010Date of Patent: January 28, 2014Assignee: ARM LimitedInventors: Paul Nicholas Whatmough, David Michael Bull, Shidhartha Das, Daniel Kershaw
-
Patent number: 8639976Abstract: A storage area network (SAN) is provided with redundancy and recovery mechanism. A primary storage switch performs dynamic address translation between logical storage addresses received from host devices and physical addresses of SAN storage arrays. When power failure in the primary storage switch is detected, metadata associated with the dynamic address translation operation is sent to a secondary storage switch via a network connection to provide the dynamic address translation in lieu of the primary storage switch. A storage array experiencing power failure similarly sends cached data to another storage array via a network connection so that the other storage array can substitute the failed storage array. During the power failure, a data backup module in the primary storage switch or the storage array is powered by a temporary power source.Type: GrantFiled: February 15, 2011Date of Patent: January 28, 2014Assignee: Coraid, Inc.Inventors: Brantley Coile, Alan Beltran, Robert Przykuki
-
Patent number: 8639977Abstract: The control device has a receiving device, an output stage, a checking device and a reset device. The receiving device is used to receive at least one data block including control commands from a data bus, the output stage is used to output an output signal in response to the control commands, the checking device is used to output an error signal if the at least one received data block is faulty and/or if no data block is received within a predetermined time, and the reset device is used to reset the output stage in a predefined state if the checking device outputs the error signal. The control device is thus able to react automatically to faultily transmitted data blocks without having to wait for return messages from a transmitting central processor unit.Type: GrantFiled: February 9, 2007Date of Patent: January 28, 2014Assignee: Robert Bosch GmbHInventors: Bernd Tepass, Bernd Nottebom
-
Patent number: 8639978Abstract: An automation process verifies that a test bed includes a set of devices specified by at least one script which are to be executed by the automation process on the test bed. The test bed is locked and the set of devices is allocated to the automation process. Performance data collection and logging for the set of devices is started and the at least one script is executed on the set of devices. After executing the at least one script, the set of devices is de-allocated and the test bed is unlocked. A notification is generated indicating that the at least one script has been executed.Type: GrantFiled: May 4, 2011Date of Patent: January 28, 2014Assignee: Aruba Networks, Inc.Inventors: Mohan Verma, Ajay Singh, Ishaan Gokhale, Pavel Semernin, Prabhat Regmi, Abhinethra T. Maras, Pragadesh Rajasekar, Sreenivasulu Lekkala
-
Patent number: 8639979Abstract: A method and system for providing immunity to a computer system wherein the system includes an immunity module, a recovery module, a maintenance module, an assessment module, and a decision module, wherein the immunity module, the recovery module, the maintenance module and the assessment module are each linked to the decision module. The maintenance module monitors the system for errors and sends an error alert message to the assessment module, which determines the severity of the error and the type of package required to fix the error. The assessment module sends a request regarding the type of package required to fix the error to the recovery module. The recovery module sends the package required to fix the error to the maintenance module, which fixes the error in the system.Type: GrantFiled: August 22, 2012Date of Patent: January 28, 2014Assignee: International Business Machines CorporationInventor: Mehmet Yildiz
-
Patent number: 8639980Abstract: Administering incident pools including receiving, by an incident analyzer from an incident queue, a plurality of incidents from one or more components of the distributed processing system; assigning, by the incident analyzer, each received incident to a pool of incidents; assigning, by the incident analyzer, to each incident a particular combined minimum time for inclusion in one or more pools, each particular combined minimum time corresponding to a particular incident; in response to the pool closing, determining, by the incident analyzer, for each incident in the pool whether the incident has met its combined minimum time for inclusion in one or more pools; and if the incident has been in the pool for its combined minimum time, including, by the incident analyzer, the incident in the closed pool; and if the incident has not been in the pool for its combined minimum time, including the incident in a next pool.Type: GrantFiled: January 15, 2013Date of Patent: January 28, 2014Assignee: International Business Machines CorporationInventors: Mark G. Atkins, James E. Carey, Philip J. Sanders
-
Patent number: 8639981Abstract: A system and method of various SoC design verification techniques. A model of an SoC design is simulated in an emulator, and the emulator is connected to a debugger. Scripts are conveyed from a host computer to the debugger. The debugger translates the commands in the scripts from a first language into commands in a second language. The debugger then conveys the commands in the second language to the emulator. The debugger is also configured to utilize the same scripts to perform tests on an actual SoC on a development board.Type: GrantFiled: August 29, 2011Date of Patent: January 28, 2014Assignee: Apple Inc.Inventor: Andrew K. Chong
-
Patent number: 8639982Abstract: An apparatus, system, and method are disclosed for probing a computer process. A probe parameter module determines a process identifier, a probe interval, and a probe action. The process identifier uniquely identifies a computer process. A start timer module starts a timer with a timer interval in response to the computer process entering an executing state on a processor core. The timer interval is based on the probe interval and on an amount of time elapsed between a probe start time and the computer process entering the executing state on the processor core. An action module executes the probe action in response to the timer satisfying the timer interval while the computer process is in the executing state on the processor core.Type: GrantFiled: June 20, 2011Date of Patent: January 28, 2014Assignee: International Business Machines CorporationInventors: Kavana N. Bhat, Muthulakshmi P. Srinivasan
-
Patent number: 8639983Abstract: An architecture and techniques for implementing a unified and extensible meta-testing framework within a distributed environment. This framework allows entities within the distributed environment to run tests written in different testing frameworks in a unified way. In addition, this disclosure describes techniques for allowing an entity within the distributed environment to test itself, both from its own perspective as well as from the perspective of other entities within the distributed environment.Type: GrantFiled: September 27, 2010Date of Patent: January 28, 2014Assignee: Amazon Technologies, Inc.Inventors: Nirav P Desai, Stanislav Fritz, Kyle Andrew Farrell, Michael C. Moore
-
Patent number: 8639984Abstract: A system of debugging computer code includes a processor: obtaining state information corresponding to a first machine at a checkpoint initiated during execution of the computer code on the first machine; and configuring the second machine to a same operating state as the first machine at the checkpoint to create a mirrored version of the first machine. The system also includes receiving a notification that execution of the program on a first machine has failed, and in response to receiving the notification: triggering a processor of the second machine to initiate execution of a copy of the code from a specific code execution point at which the checkpoint was; activating a debugger module to run concurrently with the execution of the program on the second machine and collect and store the debug data as corresponding to execution failure of the computer code at the first machine.Type: GrantFiled: August 9, 2011Date of Patent: January 28, 2014Assignee: International Business Machines CorporationInventor: Adam J. McNeeney
-
Patent number: 8639985Abstract: A Universal Serial Bus (USB) testing apparatus includes a Central Processing Unit (CPU); a Southbridge; a Baseboard Management Controller (BMC), connected with the Southbridge via USB. The BMC determines if a test starts or finishes, generates a first instruction of creating a virtual control computer when determining the test starts, creates a control module and a comparing module in a memory unit which are running to become the virtual control computer, and connects the memory unit with the BMC according to the first instruction. The control module sends control data to the CPU. The comparing module obtains feedback data from the CPU and compares the control data with the obtained data to determine if the control data is consistent with the obtained data, thereby determining whether the USB is working normally.Type: GrantFiled: December 14, 2011Date of Patent: January 28, 2014Assignees: Hong Fu Jin Precision Industry (ShenZhen) Co., Ltd, Hon Hai Precision Industry Co., Ltd.Inventor: Yu-Gang Zhang
-
Patent number: 8639986Abstract: A method includes generating trace data at a device associated with data communication to and from a computer storage device through an appropriate communication link therefor and transmitting the trace data through the appropriate communication link. The trace data is configured to enable debugging of a set of instructions associated with the device. The method also includes capturing the trace data transmitted through the appropriate communication link through a protocol analyzer, a host system or the protocol analyzer coupled to the host system and analyzing the trace data therein to obtain information associated with the set of instructions associated with the device. The protocol analyzer, the host system or the protocol analyzer coupled to the host system is configured to be external to the device associated with the data communication to and from the computer storage device.Type: GrantFiled: September 28, 2010Date of Patent: January 28, 2014Assignee: LSI CorporationInventor: Abhijit Suhas Aphale
-
Patent number: 8639987Abstract: A data processing apparatus and method are provided that use monitoring circuitry to control operating parameters of the data processing apparatus. The data processing apparatus has functional circuitry for performing data processing, the functional circuitry including error correction circuitry configured to detect errors in operation of the functional circuitry and to repair those errors in operation. Tuneable monitoring circuitry monitors a characteristic indicative of changes in signal propagation delay within the functional circuitry and produces a control signal dependent on the monitored characteristic. In a continuous tuning mode operation, the tuneable monitoring circuitry modifies the dependency between the monitored characteristic and the control signal in dependence upon certain characteristics of the errors detected by the error correction circuitry.Type: GrantFiled: February 18, 2011Date of Patent: January 28, 2014Assignee: ARM LimitedInventors: Paul Nicholas Whatmough, David Michael Bull, Shidhartha Das
-
Patent number: 8639988Abstract: A device detects and diagnoses correlated anomalies of a network. The device includes an anomaly detection module receiving a first data stream including an event-series related to the network. The anomaly detection module executes at least one algorithm to detect a potential anomaly in the event-series. The device further includes a correlating module receiving a second data stream including other event-series related to the network. The correlating module determines whether the potential anomaly is false and determines whether the potential anomaly is a true anomaly.Type: GrantFiled: December 13, 2012Date of Patent: January 28, 2014Assignee: AT&T Intellectual Property I, L.P.Inventors: Jia Wang, Ashwin Lall, Ajay Mahimkar, Jun Xu, Jennifer Yates, Qi Zhao
-
Patent number: 8639989Abstract: Methods, apparatus, and computer-accessible storage media for remotely monitoring and diagnosing storage gateways. Status information may be collected locally on the gateways and uploaded to a service provider via gateway-initiated connections. The uploaded information may be stored to status data store(s). Status proxy(s) on the provider network may analyze the information in the status data store(s) for one or more gateways to detect error conditions on individual gateways or patterns or error conditions on multiple gateways. Upon detecting an error condition on a gateway, the proxy may alert another process, for example an administrator process on the local network that includes the respective gateway. The other process may then message the gateway to address the condition. Information for particular gateways may be provided to clients on request. Information collected from multiple gateways may be viewed and analyzed by the service provider to detect patterns related to gateway design.Type: GrantFiled: June 30, 2011Date of Patent: January 28, 2014Assignee: Amazon Technologies, Inc.Inventors: James Christopher Sorenson, III, Yun Lin, Ardis G. Maison, Nishanth Alapati
-
Patent number: 8639990Abstract: An information processing apparatus capable of overwrite-recording time-series logs indicating an operation history and efficiently holding log information on operations relating to an occurring error. When an error is detected, a filtering object area is set that contains log information for a predetermined time period immediately before the error detection. Then, a type of the occurring error is identified, and log types to be protected are decided based on the identified error type. Among the filtering object area, log recording areas for the decided log types are decided as a to-be-protected log recording area. Subsequently, further log information is recorded so as to avoid the to-be-protected log recording area.Type: GrantFiled: September 27, 2010Date of Patent: January 28, 2014Assignee: Canon Kabushiki KaishaInventor: Takuma Yasukawa
-
Patent number: 8639991Abstract: An indication of a start of an execution of a process can be received, and a time counter associated with measuring a time elapsed can be initiated by the execution of the process. The time elapsed by the execution of the process can be compared with a predetermined threshold timeout value, and a report indicating the time elapsed by the execution of the process and whether the elapsed time exceeded the predetermined threshold timeout value can be automatically generated.Type: GrantFiled: December 17, 2010Date of Patent: January 28, 2014Assignee: SAP AGInventors: Udo Klein, Martin Hartig
-
Patent number: 8639992Abstract: The soft error rate (SER) detector circuit presented here can be used to measure SER in combinatorial logic devices caused by radiation. The SER detector circuit includes a plurality of detector arrays coupled in series, and each having a plurality of SER test structures coupled in series. Each of the SER test structures includes a plurality of detector elements coupled in series. Each of the SER test structures is configured to detect single event transients (SETs) in a first operating mode and single event upsets (SEUs) in a second operating mode. The SER detector circuit also has control logic elements to control operation of the plurality of detector arrays.Type: GrantFiled: May 16, 2011Date of Patent: January 28, 2014Assignee: Globalfoundries, Inc.Inventors: Christian Haufe, Jens Pika, Jörg Winkler
-
Patent number: 8639993Abstract: Techniques involving failure management of storage devices are described. One representative technique includes encoding data to enable it to be stored in a storage block that includes at least one storage failure. The data is encoded such that it traverses the storage failures when stored in the storage block. When it is determined that a storage access request has requested the data stored in a storage block having such failures, the data is decoded to restore it to its original form.Type: GrantFiled: November 11, 2010Date of Patent: January 28, 2014Assignee: Microsoft CorporationInventor: Karin Strauss
-
Patent number: 8639994Abstract: Integrated circuits with memory built-in self test (MBIST) circuitry and methods are disclosed that employ enhanced features. In one aspect of the invention, an integrated circuit is provided having MIBST circuitry configured to serially test multiple arrays of memory elements within a component of the integrated circuit and to also conduct parallel initialization of the serially tested arrays. In another aspect of the invention, the MBST circuitry is used set the memory elements of the arrays to a first state and then to an inverse state during a burn-in operation to maintain each of the two opposing states for a desired time in order to either force a failure of the integrated circuit component or produce a pre-stressed component beyond an infancy stage.Type: GrantFiled: March 15, 2013Date of Patent: January 28, 2014Assignee: Advanced Micro Devices, Inc.Inventors: Wei-Yu Chen, Kevin Badgett, Kay Hesse
-
Patent number: 8639995Abstract: Signature circuits are used during testing of an integrated circuit. Test vectors are applied as inputs to a circuit under test. A signature circuit stores a “signature” for the circuit under test based on a combination of signals from the circuit under test in response to test vectors and a previous stored state of the signature register. The value contained in the signature register at the end of the test is the signature. A fault-free circuit generates a particular signature for the applied test vectors. Faults can be determined by detecting variances from the expected signature. In one embodiment, the signature circuit uses a combination of two error detection codes.Type: GrantFiled: February 11, 2010Date of Patent: January 28, 2014Assignee: PMC-Sierra, Inc.Inventor: Steven Scott Gorshe
-
Patent number: 8639996Abstract: Systems, methods, apparatus, devices and computer program products enhance uplink inter-cell interference cancellation with HARQ retransmissions. The decoding of a data packet depends on whether the interfering packet was decoded. Since the interfering packet is itself transmitted using a HARQ process, the transmission by the victim UT can be accomplished to take this situation into account. The latency of the victim UT can be varied based on the need for energy efficient transmission. In accordance with one specific aspect, if the receiver can decode multiple packets simultaneously, high data rates can be achieved using packet pipelining.Type: GrantFiled: May 7, 2009Date of Patent: January 28, 2014Assignee: QUALCOMM IncorporatedInventors: Petru C. Budianu, Ravi Palanki
-
Patent number: 8639997Abstract: Systems and methodologies are described that facilitate utilizing timers in conjunction with transmitting buffer status reports (BSR). A prohibit timer can be utilized to determine when BSRs can be transmitted to an eNB. The prohibit timer can be initialized or restarted upon transmitting a BSR to an eNB. A BSR retransmit timer can be used to determine when to retransmit a BSR. The BSR retransmit timer can be initialized upon transmitting a BSR to an eNB and restarted each time an uplink resource allocation is received from the eNB. Once the timer expires, if an uplink transmission buffer contains data (e.g., size>0), the BSR can be retransmitted to the eNB. Control data feedback can additionally be used to determine when to retransmit the BSR. In addition, in either case, the timer duration values can be provided by the eNB.Type: GrantFiled: September 1, 2009Date of Patent: January 28, 2014Assignee: QUALCOMM IncorporatedInventors: Aleksandar Damnjanovic, Sai Yiu Duncan Ho
-
Patent number: 8639998Abstract: Methods and apparatus are described for determining, via a Hybrid Automatic Repeat Request (HARQ) module, that a maximum number of retransmissions has been reached for a HARQ packet. The HARQ module may communicate an internal NACK to a message retransmission module indicating a transmission failure. The message retransmission module may retransmit at least a part of the message. The retransmission may be performed prior to the expiration of a timer.Type: GrantFiled: February 22, 2013Date of Patent: January 28, 2014Assignee: Wi-LAN, Inc.Inventor: Peter Graumann
-
Patent number: 8639999Abstract: To suppress deterioration of retransmission efficiency and retransmit a transmission signal efficiently even when the system bandwidth is extended, provided are a base station apparatus (20) which divides, in a retransmission block dividing section (21), a transmission signal into retransmission blocks according to a retransmission block table in which the number of the retransmission blocks each of which is a retransmission unit of a transmission signal is increased corresponding to the number of transmission antennas and registered, and retransmits in downlink transmission signals associated with the divided retransmission blocks, and a mobile terminal apparatus (10) which receives the transmission signals associated with the retransmission blocks from the base station apparatus (20), and combines the retransmission blocks to restore the transmission signal prior to division.Type: GrantFiled: October 29, 2009Date of Patent: January 28, 2014Assignee: NTT DoCoMo, Inc.Inventors: Nobuhiko Miki, Satoshi Nagata, Yoshihisa Kishiyama, Mamoru Sawahashi
-
Patent number: 8640000Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for skewed orthogonal coding techniques. In one aspect, a method includes receiving a block of data comprising a plurality of data chunks. One or more rows of word code chunks are generated using a first linear error-correcting code in systematic form and the data chunks. For each of m rows of the data chunks, one or more split row code chunks are generated using the data chunks of the row, wherein the split row code chunks are generated so that a linear combination of m split row code chunks from different rows forms a first word code chunk of a first codeword including the data chunks and the word code chunks. The rows of data chunks and the split row code chunks and the word code chunks are stored.Type: GrantFiled: June 16, 2011Date of Patent: January 28, 2014Assignee: Google Inc.Inventor: Robert Cypher
-
Patent number: 8640001Abstract: Normally ordered robust VSB data are reordered in accordance with a first interleave to produce reordered robust VSB data. The reordered robust VSB data and ATSC data are reordered in accordance with a second interleave to produce normally ordered robust VSB data and reordered ATSC data. The normally ordered robust VSB data and reordered ATSC data are time multiplexed for transmission to a receiver. The receiver discards the reordered ATSC data or the normally ordered robust VSB data depending upon receiver type or user selection. A robust VSB receiver is able to process the normally ordered robust VSB data upstream of an outer decoder without an interleave thereby avoiding the delay associated with an interleave.Type: GrantFiled: October 31, 2007Date of Patent: January 28, 2014Assignee: Zenith Electronics LLCInventors: Wayne E. Bretl, Richard W. Citta, Mark Fimoff
-
Patent number: 8640002Abstract: Apparatuses and methods for resolving trapping sets are provided. One example method can include attempting to decode a codeword using initial values for confidence levels associated with digits of the codeword. For a trapping set, the confidence levels associated with the digits corresponding to a failed parity check are adjusted. The method further includes attempting to decode a codeword using the adjusted value for the confidence levels of the digits corresponding to the failed parity check.Type: GrantFiled: July 10, 2012Date of Patent: January 28, 2014Assignee: Micron Technology, Inc.Inventor: Chandra C. Varanasi
-
Patent number: 8640003Abstract: A mobile station for performing radio communication with a radio base station, the mobile station includes an information generation section which generates information indicative of a result of error detection on a downlink signal received; and a sending section which sends the information via a physical uplink control channel, and sends uplink data via a physical uplink shared channel at a different transmission frequency from the physical uplink control channel and in a same transmission time period as the physical uplink control channel; whereby the information generation section and the sending section operate when the mobile station receives downlink scheduling information and uplink allocation grant in a same subframe.Type: GrantFiled: April 25, 2013Date of Patent: January 28, 2014Assignee: Fujitsu LimitedInventors: Tetsuya Yano, Kazuhisa Obuchi, Tsuyoshi Shimomura
-
Patent number: 8640004Abstract: There is provided a solution for rearranging data to a decoder of a receiver. The solution comprises receiving data, writing the data to one or more memory slots in parts, first in an ascending order of addresses and then in a descending order of addresses. The solution further comprises reading the full memory slots in a descending order of addresses and forwarding the read data to the decoder.Type: GrantFiled: April 24, 2009Date of Patent: January 28, 2014Assignee: Nokia CorporationInventor: Petros Oikonomakos
-
Patent number: 8640005Abstract: A cache memory system uses multi-bit Error Correcting Code (ECC) with a low storage and complexity overhead. In an embodiment, error correction logic may include a first error correction logic to determine a number of errors in data that is stored in a cache line of a cache memory, and a second error correction logic to receive the data from the first error correction logic if the number of errors is determined to be greater than one and to perform error correction responsive to receipt of the data. The cache memory system can be operated at very low idle power, without dramatically increasing transition latency to and from an idle power state due to loss of state. Other embodiments are described and claimed.Type: GrantFiled: May 21, 2010Date of Patent: January 28, 2014Assignee: Intel CorporationInventors: Christopher B. Wilkerson, Alaa R. Alameldeen, Zeshan A. Chishti, Dinesh Somasekhar, Wei Wu, Shih-Lien Lu
-
Patent number: 8640006Abstract: An apparatus includes a processor, a memory, and an error module operable on the processor. The error module is configured to perform a memory scrub of the memory across a scrub cycle of multiple scrub cycles. The error module is configured to identify correctable errors of symbols in the memory that are a result of accesses from a section of the memory in response to the memory scrub. The error module is configured to perform an analysis across the multiple scrub cycles, wherein the analysis comprises a determination whether at least two symbols across the multiple scrub cycles have at least one correctable error. The error module is configured to responsive to a determination that at least two symbols across the multiple scrub cycles have at least one correctable error, execute at least one repair of the memory that includes the section of memory.Type: GrantFiled: June 29, 2011Date of Patent: January 28, 2014Assignee: International Business Machines CorporationInventors: Jay W. Carman, Marc A. Gollub, Anshuman Khandual, Jyotindra Patel
-
Patent number: 8640007Abstract: A test system including a storage device and a protocol analyzer coupled to the storage device. The storage device can include a diagnostic data transmission unit configured to transmit diagnostic data related to an operation of the storage device, and a host interface unit including a first selector configured to receive idle characters and the diagnostic data, wherein the first selector selectively transmits the idle characters or the diagnostic data. The protocol analyzer can be configured to autonomously receive the idle characters or the diagnostic data via the host interface unit.Type: GrantFiled: September 29, 2011Date of Patent: January 28, 2014Assignee: Western Digital Technologies, Inc.Inventor: Martin E. Schulze