Abstract: Separation directives for integrated circuit layout design data are formed based upon one or more printing feasibility analyses performed on the layout design data. At least one printing feasibility analysis is performed on layout design data to identify portions of the design that may not be correctly formed or “printed” during a photolithographic process. The geometric element edges involved in a potential printing defect are then identified as edges to be formed using separate masks. Further, separation directives may be created to specifically designate the identified edges as edges to be formed using separate masks in a photolithographic manufacturing process.

Abstract: There is provided a computer-implemented method of creating a recipe for a manufacturing tool and a system thereof. The method comprises: upon obtaining data characterizing periodical sub-arrays in one or more dies, generating candidate stitches; identifying one or more candidate stitches characterized by periodicity characteristics satisfying, at least, a periodicity criterion, thereby identifying periodical stitches among the candidate stitches; and aggregating the identified periodical stitches and the periodical sub-arrays into periodical arrays, said periodical arrays to be used for automated recipe creation.

Abstract: Methods and apparatuses to automatically synthesize circuits. In one aspect of an embodiment, a method implemented on a data processing system for circuit synthesis comprises determining a Read Only Memory (ROM) of a design of a circuit, the ROM having predefined data when the circuit is initialized, and automatically generating an initialization circuit and a Random Access Memory (RAM) to implement the ROM, the initialization circuit to load the predefined data into the RAM when the circuit is initialized.

Abstract: A mechanism is provided for rapid estimation of temperature rise in wires due to Joule heating. The mechanism provides fast and accurate estimation of temperature rise in wires due to self heating. Fast estimation is important to handle millions of nets at the full-chip level. The mechanism models lateral heat flow by considering longitudinal heat flow along the wire and lateral thermal coupling to the other wires in the same level. Lateral heat flow can have a significant effect on the temperature rise. The mechanism also models vertical heat flow to the substrate and the heat sink by considering thermal conductivities of vias and inter-layer dielectric (ILD). The mechanism efficiently solves the thermal system to enable physical design optimizations (e.g., wire sizing, etc.) for fixing electromigration violations.

Abstract: The method for synthesizing soft error tolerant combinational circuits includes the step of inputting a combinational circuit to a combinational circuit analyzer for analysis. The analyzer then extracts smaller sub-circuits from said combinational circuit, computes probabilities of input vectors to occur for each of the smaller sub-circuits, produces new multi-level sub-circuits from the extracted sub-circuit, and maximizes logical fault masking against the occurrence of a single fault applied to the new multi-level sub-circuits, the maximizing being based on probabilities of sub-circuit input vectors to occur. Finally, the analyzer merges the new multi-level sub-circuits back to the original inputted combinational circuit.

Abstract: Processing a circuit design specified in a hardware description language (HDL) can include, for each of a plurality of nets of the circuit design, creating a trace memory structure, using a processor, during compilation of the HDL circuit design. Each trace memory structure can include trace properties indicating whether tracing is active for the net. A transaction function can be generated during compilation for each net. The transaction function can be configured to invoke tracing for each net during simulation of the circuit design according to an evaluation of the trace properties for the net.

Abstract: In one exemplary embodiment of the invention, a method includes: receiving a first description for a circuit whose operation over a plurality of inputs is to be verified; receiving a second description for expected behavior of the circuit, where the expected behavior in the second description is expressed as a set of algebraic systems of multivariable polynomials over at least one Galois field; applying at least one computational algebraic geometry technique to a combination of the first description and the second description to determine whether the circuit is verified, where verification of the circuit confirms that at least one output obtained based on the first description corresponds to at least one expected value based on the expected behavior expressed in the second description; and outputting an indication as to whether the circuit is verified.

Abstract: In one embodiment, a method of designing an integrated circuit is disclosed, including receiving a first partition block for a top level of a hierarchical design of an integrated circuit; analyzing each pin of the first partition block for an attribute associated with the pin indicating a timing exception; and if a timing exception other than false path is indicated then generating an internal timing pin in a first timing graph model of the first partition block for each timing exception, and adding a timing arc and a dummy arc coupled to the internal timing pin in the first timing graph model of the first partition block. The internal timing pin adds a timing exception constraint for each timing exception. Timing of the top level may then be analyzed with the first timing graph model to determine if timing constraints, including the added timing exception constraints, are met.

Abstract: A skew generator unit includes a delay chain. The delay chain is coupled to a clock line that transmits a clock signal. The delay chain generates a skewed clock signal having a unit of delay from the clock signal. The skew generator unit also includes a selector. The selector is coupled to the delay chain and the clock line and may select one of the clock signal and the skewed clock signal.

Abstract: Techniques generally disclosed herein relate to computation of a guard zone of a three-dimensional object. In some examples, guard zones may be computed by identifying intersection lines that couple adjacent planes of an object, and categorizing an external angle at an intersection line between adjacent planes as concave or convex. In some embodiments, for convex angles, a cylindrical surface can be determined that is located about an outside surface of the object and centered along the intersection line between the adjacent planes. In some embodiments, for concave angles, the external angle can be bisected with a bisection plane. A guard zone may be formed by one or more of (i) providing a guard zone plane parallel to the object that is a tangent to a given cylindrical surface, (ii) providing a guard zone plane parallel to the object that intersects a given bisection plane, and/or (iii) coupling adjacent guard zone planes.

Abstract: Provided is a noise analysis model and a noise analysis method that can analyze effects of substrate noise on each of elements included in a circuit to be analyzed. The noise analysis model includes first to third resistors. The first resistor serves as a substrate resistor in a semiconductor substrate between a first point set in the semiconductor substrate between a noise source and a transistor to which substrate noise from the noise source propagates through the semiconductor substrate and a second point set in the semiconductor substrate just below a back gate of the transistor. The second resistor serves as a substrate resistor in the semiconductor substrate between the second point and a fixed potential region near the transistor. The third resistor serves as a line resistor of a line connecting the fixed potential region and a power pad that supplies a ground potential.

Abstract: A plurality of target field programmable gate arrays are interconnected in accordance with a connection topology and map portions of a target system. A control module is coupled to the plurality of target field programmable gate arrays. A balanced clock distribution network is configured to distribute a reference clock signal, and a balanced reset distribution network is coupled to the control module and configured to distribute a reset signal to the plurality of target field programmable gate arrays. The control module and the balanced reset distribution network are cooperatively configured to initiate and control a simulation of the target system with the plurality of target field programmable gate arrays. A plurality of local clock control state machines reside in the target field programmable gate arrays. The local clock control state machines are coupled to the balanced clock distribution network and obtain the reference clock signal therefrom.

Abstract: A circuit design system 10 includes storage means 11 to store structure description information 11a of a reconfigurable circuit including an array of cells 1 including a plurality of switches 2, and application circuit netlist information 11b used to specify an application, circuit generation unit 12a to generate structure description information 11a based on the structure description information 11a and the application circuit netlist information 11b stored in the storage means 11, and circuit evaluation unit 12b to evaluate the structure description information 11a generated by the circuit generation unit 12a, wherein the circuit generation unit 12a generates the structure description information 11a by deleting at least one of the switches 2 from the structure description information 11a based on an evaluation result obtained by the circuit evaluation unit 12b.

Abstract: A method includes forming a connection between a first metal layer and a second metal layer. The second metal layer is over the first metal layer. A via location for a first via between the first metal layer and the second metal layer is identified. Additional locations for first additional vias are determined. The first additional vias are determined to be necessary for stress migration issues. Additional locations necessary for second additional vias are determined. The second additional vias are determined to be necessary for electromigration issues. The first via and the one of the group consisting of (i) the first additional vias and second additional vias (ii) the first additional vias plus a number of vias sufficient for electromigration issues taking into account that the first additional vias, after taking into account the stress migration issues, still have an effective via number greater than zero.

Abstract: For increasing user control and insight into preparing a mixed semiconductor design specification for simulation, there are provided methods responsive to commands that provide control over resolution of disciplines and partitioning of the design into analog and digital portions. In some aspects, the methods provide block-based assignments of disciplines, as well as design partitioning. In other aspects, the methods provide for resolving a discipline to apply in a block from among multiple possible disciplines. In some aspects, error flagging may be available for detecting disciplines different from what provided for assignment in a block. Assignments may be indicated based on instance, cell, terminal, or library names and may be specified with wild cards. In still other aspects, the methods may be embodied by instructions on computer readable media, and in systems comprising general and special purpose computer hardware that may communicate with various storage facilities and over various networks.

Abstract: A digital circuit block includes first to fourth conducting segments, a digital logic, first and second conducting layers, and a dielectric layer. The first and second conducting segments are coupled to first and second supply voltages, respectively. The digital logic and dielectric layer are between the first and second conducting segments. The third conducting segment includes a first end electrically connected to the first conducting segment, a second end not electrically connected to the second conducting segment, and a first portion located at the first conducting layer. The fourth conducting segment includes a first end electrically connected to the second conducting segment, a second end not electrically connected to the first conducting segment, and a second portion located at the second conducting layer. The first and second portions and dielectric layer are formed a first capacitive element to reduce the supply voltage drop between the first and second supply voltages.

Abstract: Some example embodiments include a computer-implemented method for designing an integrated circuit. The computer-implemented method includes receiving a hierarchical network design for the integrated circuit, wherein the hierarchical design comprises a number of components that are coupled together. The computer-implemented method includes detecting that a component of the number of components has at least one of failed timing and incomplete timing based on a problem that comprises at least one of a missing assertion, one or more missing latches, a source driver having an input source slew that is greater than a source slew limit threshold, and a sink having an input sink slew that is greater than a sink slew limit threshold. The computer-implemented method includes replacing the component with a different component that is independent of the problem and testing others components of the number of components based on the different component.

Abstract: A methodology is provided on developing metal fill as a library device and, in particular, a method of generating a model of the effects (e.g., capacitance) of metal fills in an integrated circuit and a design structure. The method is implemented on a computing device and includes generating a model for effects of metal fill in an integrated circuit. The metal fill model is generated prior to completion of a layout design for the integrated circuit.

Abstract: Systems and methods are provided for capturing mutual coupling effects between an integrated circuit chip and chip package using electronic design automation (EDA) tools. Specifically, a method is provided that is implemented in a computer infrastructure for designing an integrated circuit chip. The method includes compiling process technology parameters that describe electrical behavior for a chip-package coupling and a package of the integrated circuit chip. The method also includes generating a parasitic technology file to include the compiled process technology parameters.

Abstract: Searching for graphical objects of a design using a computer system. In one aspect of the inventions, a method includes defining a graphical search pattern based on input received from a user in a graphical interface displayed on a display device, where the search pattern is a graphical object and is defined with a plurality of types of characteristics. The graphical design is searched for all matching instances of graphical objects in the design that match the search pattern and match the characteristics specified by the search pattern. At least one of the matching instances is caused to be displayed on the display device as a result of the searching.

Abstract: Searching and/or replacing graphical objects of a design using a computer system. In one aspect of the inventions, a method includes searching a graphical design for all matching instances of graphical objects that match a search pattern. A graphical replacement pattern is received and caused to be displayed based on user input, and the matching instances in the graphical design are replaced with the graphical replacement pattern. At least one result of the replacement of the matching instances is caused to be displayed on a display device.

Abstract: Disclosed is a method and system for visualizing pin access locations on an integrated circuit design. Visual feedback is provided to a user that is attempting to connect a wire or a via to a pin structure polygon on the integrated circuit design. The visual feedback comprises any visual cue that provides an indication of a legal location to access the pin.

Abstract: Techniques for determining resistances of analog routes in electronic designs are described herein. In an example embodiment, a computer system receives first user input that indicates, in a user interface, a first component in an electronic design. The electronic design has been placed and routed for a programmable target device. The computer system receives second user input that selects, in the user interface, a particular component from one or more second components of the electronic design, where the one or more second components have analog connectivity to the first component. The computer system determines a resistance value of an analog route between the first component and the particular component, and displays the resistance value in association with the analog route in the user interface.

Abstract: A method and system for specifying a data occurrence in a service-oriented architecture based environment. After a service specification phase of a service, a service interface is received and a service implementation is created. During a service realization phase, a data element of the service is determined to be sourced or not sourced by the service implementation. If the data element is sourced, then the data element is determined to be optional. If the data element is not sourced, then the data element is determined to be mandatory. The data occurrence including an indication of whether the data element is optional or mandatory is displayed. The service specification phase is repeated and the service interface is modified based on the displayed data occurrence.

Abstract: Validating executable data for interactions among a plurality of process artifacts at design time. A data context is created to include the plurality of process artifacts. The data context carries interaction rules among the plurality of process artifacts. The executable data from a data source is associated with the plurality of process artifacts in the created data context. A subset of the interaction rules is selected corresponding to at least one of the plurality of process artifacts. The associated executable data is validated when the associated executable data is in accordance with the selected subset of the interaction rules.

Abstract: In one embodiment, a method includes accessing a modeling language representation of a system under test. The representation includes one or more Message Sequence Charts (MSCs). One or more of the MSCs includes one or more conditional constructs including at least one or more guards or one or more loops. The method includes generating one or more use scenarios based on the modeling language representation and generating one or more validation test suites based on the one or more use scenarios.

Abstract: A system and associated method for generating a Service Component Architecture (SCA) module with Service Oriented Architecture (SOA) model elements. A service model is created according to a process model that has activities and a process flow. Services of the service model are respectively associated with the activities. Each service is determined to employ only one service operation definition to render a message specification of a respective activity that is associated with each service. The activities, the process flow, and the message specification are utilized to produce the SCA module in executable implementations.

Abstract: A system and method for visualizing objects within an object network. For example, a computer-implemented method according to one embodiment comprises: receiving object graph data from a remote computing system, the object graph data representing characteristics of objects and relationships between objects in object-oriented program code executed on the remote computer system; interpreting the object graph data to determine one or more characteristics of each of the objects; and generating a graphical user interface (“GUI”) comprised of a plurality of graphical nodes arranged in a graph structure, each of the nodes representing one of the objects and the graph structure representing the relationships between the objects, wherein the graphical nodes are rendered with graphical characteristics representing characteristics of the objects which they represent, the graphical characteristics including at least a color and a shape.

Abstract: A method and a scripting paradigm for automatically integrating disparate information systems (e.g., web services and databases) within a given enterprise into a service-oriented architecture. A script writer generates a script using a scripting paradigm, and the resulting script automatically derives new data models, new ontological structures, new mappings, and a new web service that integrates disparate information systems. In addition to integrating disparate information systems, the scripts may be harvested to automate the metadata discovery and retrieval process. The scripting paradigm builds upon existing open-source scripting languages and is compatible with existing internet browsers, thus encouraging mass participation in the integration process.

Abstract: Software reuse utilizing naive group annotation of incomplete software descriptions. A software code is decimated whereby the software code's attributes, such as variable, class and method names are obfuscated into non-informative forms. The decimated software code is then presented to two or more participants that include at least one naive and one informed participant. The naive participant(s) poses a predetermined number of question(s) to and receive answer(s) from the informed participant(s). After receiving the answer(s) posed to the informed participant(s), the naive participant(s) proceeds to guess the function of the presented decimated software code. The annotations, i.e., questions and answers, to the decimated software code under review are collected and stored in a database.

Abstract: A system and method for constructing and deploying a business activity monitoring (BAM) dashboard associated with an event-based process are disclosed. A configuration module receives an event-based process identifier for an event-based process and data, such as inputs or outputs, for the event-based process. A generation module then generates a dashboard description that includes the identifier and an associated dashboard template having one or more dashboard components. This dashboard description is used by a dashboard server to automatically generate a BAM dashboard for monitoring the event-based process by using the association between the dashboard template and the event-based process to display data associated with the event-based process using one or more dashboard components.

Abstract: An application may obtain a data object based on a data type from a data dictionary. The obtained data object may be copied and modified. The modifications may include, for example, adding, removing, and/or changing a property, built-in type, simple type, and/or complex type of the data object.

Abstract: A method of operating a data processing system comprises running a source code editor, displaying source code in a graphical interface of the source code editor, and displaying a summary box, the summary box comprising a list of one or more aspects affecting the source code. The system is configured so that on receipt of a user input corresponding to an aspect listed in the summary box there is displayed one or more cross-reference markers of the selected aspect in the graphical interface of the source code editor.

Abstract: A compatibility evaluation apparatus for evaluating compatibility between a platform program and an application program that uses interfaces provided by the platform program, includes an application analyzing unit configured to analyze the application program and extract a list of the interfaces used by the application program; an incompatibility interface usage determination unit configured to extract, from the list of the interfaces used by the application program, an interface that corresponds to an incompatible interface that does not satisfy a specification, the interface being extracted with the use of a first storage unit storing information indicating contents of incompatibility for each of the incompatible interfaces among the interfaces provided by the platform; and a compatibility report creating unit configured to record, in a second storage unit, the information indicating contents of incompatibility for each interface that has been extracted by the incompatibility interface usage determination u

Abstract: Hosted applications are developed to be run in a hosted network environment and with access to host resources such as server databases and messaging systems. The host applications may include tag based requests for host resources. A platform-specific native host is used on a mobile device which interacts with a hosted application and identifies content-based request for host resources. The native host then determines and performs appropriate functionality in the context of a mobile platform to satisfy the host resource request. Hosted applications may thereby be run natively on mobile devices of various mobile platforms and accessed even when the mobile devices lack network connections.

Abstract: Embodiments relate to building a downloadable application. In response to a request to build a downloadable application, a build system determines a set of resources used by the downloadable application. The build system reads this initial set of resources to discover other resources used by the downloadable application. The build system determines resource dependencies for the set of resources and the discovered set of resources, and creates a dependency data structure according to the resource dependencies. Using the dependency data structure, the build system determines a subset of the set of resources and the discovered set of resources to include in a module associated with the downloadable application.

Abstract: Embodiments of the present invention provide a method, system and computer program product for melding mediation and adaptation modules of a service component architecture (SCA) system. A method for melding mediation and adaptation modules of an SCA system can include selecting each of a mediation module and an adaptation module in an integrated development tool executing in memory by a processor of a computer and loading respectively different descriptor files for each of the mediation module and the adaptation module. The method further can include combining descriptors from the different descriptor files into a single descriptor file for a melded module. Finally, the method can include modifying names and wiring descriptors in the single descriptor file for the melded module to account for a combination of the mediation component and the adaptation component in the melded component.

Abstract: Centrally managing configuration of software application involves creating configuration metadata for each component of the application; providing a specific configuration for a component; checking validity of the specific configuration using the metadata for said component; and monitoring the application component configuration for consistency with said specific configuration.

Abstract: A media interaction system is described herein that allows hosted applications to consume and/or produce rich media content independent of the format of the media content, while still maintaining the security of the host. The media interaction system accepts raw, uncompressed media data from a hosted application, and allows the hosted application to provide its own codec through a sandboxed API that restricts the actions the codec can perform to a set of trusted actions. Then, the application provides the uncompressed data to the system for playback. Thus, the media interaction system provides rich media content in any format that the application developer supports, and maintains the security of the user's computer system.

Abstract: A system for creating a station having a configuration and making the station active within a supervisor application without a need of actual site controller hardware. The configuration may be changed. The new station may be downloaded with the changed configuration to a site controller. Multiple steps for effecting the present configuration design and station download may automatically be accomplished by fewer steps.

Abstract: Disclosed are various embodiments of a method and system for detecting feature conflicts in a vendor account configuration. A request to modify an account configuration for an account holder is obtained. The configuration describes at least one feature provided to the account holder by a hosted service provider. A determination is made as to whether the requested modification complies with at least one vendor feature rule. If the modification complies with the at least one vendor feature rule, the configuration is modified as requested.

Abstract: System and method for configuring wires in and/or debugging a statechart. The statechart may be created or displayed on a display and may include a plurality of state icons connected by wires. The state icons may represent states and the wires may represent transitions between the states. One or more of the wires may be configured, e.g., according to user input. A graphical program may be created which specifies a debugging operation for the statechart. The statechart may be executed and may provide data to the graphical program. The graphical program may receive first data produced by the statechart, e.g., during execution. The graphical program may perform the debugging operation based on the first data.

Abstract: Embodiments of the present invention address deficiencies of the art in respect to source code analysis and provide a novel and non-obvious method, system and computer program product for source code pedigree management. In one embodiment of the invention, a method for source code pedigree management can be provided. The method can include parsing source code to identify copyright rights holders for corresponding copyright constructs, rejecting copyright constructs not associated with corresponding rights holders, compiling a list of the identified copyright rights holders, corresponding copyright statements, and lists of files corresponding to each of the copyright rights holders, and displaying the compiled list.

Abstract: An image forming apparatus includes a program storing unit, a function introducing unit to obtain a program licensed to an individual user and license information about the program from an external source and to store the program in the program storing unit, a user information storing unit to store user information that includes the license information about the program that is stored by the function introducing unit, the license information being associated with a user ID of the individual user in the user information, a removal timing receiving unit to receive a setting of removal timing at which the program stored by the function introducing unit is removed from the program storing unit, and a removal unit to remove the program stored by the function introducing unit from the program storing unit upon arrival of the removal timing received by the removal timing receiving unit.

Abstract: Embodiments are provided to utilize an orthogonal or independent programming component to rapidly develop new features for use in computer application programs through the testing of new application program concepts on a server. In one embodiment, the orthogonal programming component intercepts a request to access an application program stored on the server and, if the request meets certain predefined criteria, sends the request to a treatment component to implement the new application concepts without changes having to be made to the application program stored on the server.

Abstract: A computer based method and apparatus generate a class relationship diagram of dynamic language objects. In response to a user selecting a subject object implemented in the dynamic language, a diagramming member forms and displays a class relationship diagram of the subject object The class relationship diagram visually illustrates relationships between the subject object and objects it inherits from and objects it contains as extracted from the inheritance chain of the subject object. UML or graph notation may be employed in the generated class relationship diagram.

Abstract: A computer-implemented method for debugging a job running on a legacy system is provided. The job to be debugged is identified by programmatically reading a screen provided by the legacy system that displays a list of active jobs of the legacy system via screen scraping. Source code that corresponds to the identified job is programmatically retrieved. A breakpoint is programmatically created in the retrieved source code.

Abstract: A testing unit includes an input/output module and a processing module. The input/output module receives application requirements and parameters. The processing module generates a set of test cases based on the application requirements and the parameters; adjusts at least some of the set of test cases based on a code generation progression to produce targeted progression test cases; and tests a developing application code based on the targeted progression test cases, wherein the code generation progression indicates a level of development of the developing application code.

Abstract: A unified program analysis framework that facilitates the analysis of complex multi-language software systems, analysis reuse, and analysis comparison, by employing techniques such as program translation and automatic results mapping, is presented. The feasibility and effectiveness of such a framework are demonstrated using a sample application of the framework. The comparison yields new insights into the effectiveness of the techniques employed in both analysis tools. These encouraging results yield the observation that such a unified program analysis framework will prove to be valuable both as a testbed for examining different language analysis techniques, and as a unified toolset for broad program analysis.

Abstract: A technique for managing hardware resources and threads within a data processing system is disclosed. Compilation attributes of a function are collected during and after the compilation of the function. The pre-processing attributes of the function are also collected before the execution of the function. The collected attributes of the function are then analyzed, and a runtime configuration is assigned to the function based of the result of the attribute analysis. The runtime configuration may include, for example, the designation of the function to be executed under either a single-threaded mode or a simultaneous multi-threaded mode. During the execution of the function, real-time attributes of the function are being continuously collected. If necessary, the runtime configuration under which the function is being executed can be changed based on the real-time attributes collected during the execution of the function.