Abstract: An integrated circuit contains lower components in the substrate, a PMD layer, upper components over the PMD layer, lower contacts in the PMD layer connecting some upper components to some lower components, an ILD layer over the upper components, metal interconnect lines over the ILD layer, and upper contacts connecting some upper components to some metal interconnect lines, and also includes annular stacked contacts of lower annular contacts aligned with upper annular contacts. The lower contacts and upper contacts each have a metal liner and a contact metal on the liner. The lower annular contacts have at least one ring of liner metal and contact metal surrounding a pillar of PMD material, and the upper contacts have at least one ring of liner metal and contact metal surrounding a pillar of ILD material. The annular stacked contacts connect the metal interconnects to the lower components.

Abstract: Disclosed herein is a method of forming electronic device having thin-film components by using trenches. One or more of thin-film components is formed by depositing a thin-film in the trench followed by processing the deposited thin-film to have the desired thickness.

Abstract: Provided is a test apparatus for testing a device under test, including a dicing section that dices a wafer on which a plurality of devices under test are formed to separate each of the devices under test, a test packaging section that packages each of the devices under test resulting from the dicing by the dicing section in an individual test package, a testing section that tests the devices under test packaged in the test packages, a removing section that removes the devices under test that have been tested from the test packages, and a commercial packaging section that packages the devices under test removed from the test packages in commercial packages.

Abstract: A chip testing method includes cutting a wafer into chip packages, re-arranging the chip packages on a chip tray, and testing the re-arranged chip packages. The wafer includes a plurality of substrates vertically stacked thereon, and each of the plurality of substrates has a plurality of chips mounted thereon.

Abstract: An object is to provide a method for manufacturing a light-emitting device in which a defective portion is insulated. In addition, another object is to provide a manufacturing apparatus of a light-emitting device in which a defective portion is insulated. After a hemispherical lens is formed to overlap with a light-emitting element, the defective portion is detected. Then, the hemispherical lens overlapping with the light-emitting element including the detected defective portion may be irradiated with a laser beam having a low energy density, and the defective portion may be insulated by light condensed through the hemispherical lens.

Abstract: Standardized photon building blocks are packaged in molded interconnect structures to form a variety of LED array products. No electrical conductors pass between the top and bottom surfaces of the substrate upon which LED dies are mounted. Microdots of highly reflective material are jetted onto the top surface. Landing pads on the top surface of the substrate are attached to contact pads disposed on the underside of a lip of the interconnect structure. In a solder reflow process, the photon building blocks self-align within the interconnect structure. Conductors in the interconnect structure are electrically coupled to the LED dies in the photon building blocks through the contact pads and landing pads. Compression molding is used to form lenses over the LED dies and leaves a flash layer of silicone covering the landing pads. The flash layer laterally above the landing pads is removed by blasting particles at the flash layer.

Abstract: HPC techniques are applied to the screening and evaluating the materials, process parameters, process sequences, and post deposition treatment processes for the development of ohmic contact stacks for optoelectronic devices. Simple test structures are employed for initial screening of basic materials properties of candidate materials for each layer within the stack. The use of multiple site-isolated regions on a single substrate allows many material and/or process conditions to be evaluated in a timely and cost effective manner. Interactions between the layers as well as interactions with the substrate can be investigated in a straightforward manner.

Abstract: A method for etching an insulating film includes the steps of forming an insulating film; forming a first resin layer composed of a non-silicon-containing resin on the insulating film; forming a pattern including projections and recesses in the first resin layer; forming a second resin layer composed of a silicon-containing resin to cover the projections and the recesses of the pattern in the first resin layer; etching the second resin layer by reactive ion etching with etching gas containing CF4 gas and oxygen gas until the projections of the first resin layer are exposed, a Si component of the second resin layer being oxidized in etching the second resin layer; selectively etching the first resin layer until the insulating film is exposed using as a mask the second resin layer buried in the recesses of the first resin layer to form a resin layer mask; and etching the insulating film using the resin layer mask.

Abstract: According to the method of manufacturing an optical matrix device of this invention, semiconductor films and gate insulating films which influence the characteristics of thin-film transistors most are formed in a vacuum (S12, S13), whereby the interfaces between the semiconductor films and gate insulating films are not contaminated. The semiconductor films and gate insulating films are formed in a vacuum, but wires need not be formed in a vacuum (S03). Thus, the semiconductor films and gate insulating films formed in a vacuum are transferred onto the wires formed beforehand (S21). Even if a substrate has a large area, the wires, semiconductor films and gate insulating films of the thin-film transistors can be formed efficiently.

Abstract: A solid-state image pickup device includes an element isolation insulating film electrically isolating pixels on the surface of a well region; a first isolation diffusion layer electrically isolating the pixels under the element isolation insulating film; and a second isolation diffusion layer electrically isolating the pixels under the first isolation diffusion layer, wherein a charge accumulation region is disposed in the well region surrounded by the first and second isolation diffusion layers, the inner peripheral part of the first isolation diffusion layer forms a projecting region, an impurity having a conductivity type of the first isolation diffusion layer and an impurity having a conductivity type of the charge accumulation region are mixed in the projecting region, and a part of the charge accumulation region between the charge accumulation region and the second isolation diffusion layer is abutted or close to the second isolation diffusion layer under the projecting region.

Abstract: A MEMS is attached to a bonding wafer in part by forming a support layer over the MEMS. A first eutectic layer is formed over the support layer. The eutectic layer is patterned into segments to relieve stress. A second eutectic layer is formed over the bonding wafer. A eutectic bond is formed with the segments and the second eutectic layer to attach the bonding wafer to the MEMS.

Abstract: A sensor device and method. One embodiment provides a first semiconductor chip having a sensing region. A porous structure element is attached to the first semiconductor chip. A first region of the porous structure element faces the sensing region of the first semiconductor chip. An encapsulation material partially encapsulates the first semiconductor chip and the porous structure element.

Abstract: The present invention discloses a micrometer-scale grid structure based on single crystal silicon consists of periphery frame 1 and grid zone 2. The periphery frame 1 is rectangle, and grid zone 2 has a plurality of mesh-holes 3 distributing in the plane of grid zone 2. The present invention also provides a method for manufacturing a micrometer-scale grid structure based on single crystal silicon. According to the present invention thereof, the contradiction between demand of broad deformation space for sensor and actuator and the limit of the thickness of sacrifice layer is solved. Furthermore, the special requirement of double-side transparence for some optical sensor is met.

Abstract: An implanting method for forming a photodiode comprises providing a substrate with a first conductivity, growing an epitaxial layer on the substrate, implanting ions with a second conductivity in the epitaxial layer from a front side of the substrate and implanting ions with the first conductivity in the epitaxial layer from the front side of the substrate to form a photo active region adjacent to the front side and a photo inactive region underneath the photo active region. By employing the implanting method, an average doping density of the photo active region is approximately ten times more than an average doping density of the photo inactive region.

Abstract: A method of roughening a substrate surface includes forming an opening in a protection film formed on a surface of a semiconductor substrate, performing a first etching process using an acid solution by utilizing the protection film as a mask so as to form a first concave under the opening and its vicinity area, performing an etching process by using the protection film as a mask so as to remove an oxide film formed on a surface of the first concave, performing anisotropic etching by using the protection film as a mask so as to form a second concave under the opening and its vicinity area, and removing the protection film.

Abstract: A method for high temperature selenization of Cu—In—Ga metal precursor films comprises a partial selenization at a temperature between about 350 C and about 450 C in a Se-containing atmosphere followed by a more fully selenization step at a temperature between about 550 C and about 650 C in a Se-containing atmosphere. The Se-containing component of the atmosphere is removed through a rapid gas exchange process and the CIGS film is annealed to influence the Ga distribution throughout the depth of the film.

Abstract: A thin film photovoltaic device on a substrate is being realized by a method for manufacturing a p-i-n junction semiconductor layer stack with a p-type microcrystalline silicon layer, a p-type amorphous silicon layer, a buffer silicon layer comprising preferably intrinsic amorphous silicon, an intrinsic type amorphous silicon layer, and an n-type silicon layer over the intrinsic type amorphous silicon layer.

Abstract: A photovoltaic cell, the cell comprising: a silicon substrate of bulk silicon material having front and rear surfaces; an emitter layer on the rear surface of said substrate; elongate channels through the emitter layer; elongate contacts to the bulk of the silicon substrate within at least some of the elongate channels, wherein the contacts are narrower than the channels; and gaps in the emitter between at least some of the elongate contacts and the emitter layer on the sides of the contacts.

Abstract: The present invention provides a thick-film paste for printing the front side of a solar cell device having one or more insulating layers and a method for doing so. The thick-film paste comprises a source of an electrically conductive metal and a lead-vanadium-based oxide dispersed in an organic medium. The invention also provides a semiconductor device comprising an electrode formed from the thick-film paste.

Abstract: A method of making nanostructures using a self-assembled monolayer of organic spheres is disclosed. The nanostructures include bowl-shaped structures and patterned elongated nanostructures. A bowl-shaped nanostructure with a nanorod grown from a conductive substrate through the bowl-shaped nanostructure may be configured as a field emitter or a vertical field effect transistor. A method of separating nanoparticles of a desired size employs an array of bowl-shaped structures.

Abstract: A method of manufacturing a thin film transistor is provided. The method includes forming a lower organic semiconductor layer, forming an upper organic semiconductor layer on the lower organic semiconductor layer, the upper organic semiconductor layer having solubility and conductivity higher than those of the lower organic semiconductor layer, forming a source electrode and a drain electrode spaced apart from each other and respectively overlapping the upper organic semiconductor layer, and dissolving the upper organic semiconductor layer selectively by using the source electrode and the drain electrode as a mask.

Abstract: A method of manufacturing a phase-change random access memory includes: sequentially depositing an insulating layer, a first electrode layer, a phase change material layer, and a transfer material layer on a substrate; forming an array pattern in the transfer material layer using a laser interference lithography process; forming a metal layer on the transfer material layer having the array pattern formed; forming a second electrode layer by removing the transfer material layer; and forming a phase change layer by etching the phase change material layer using the second electrode layer as a mask. Accordingly, the manufacturing process of the phase-change random access memory may achieve an increase in speed and may be simplified.

Abstract: A layered chip package includes a main body, and wiring that includes a plurality of wires disposed on a side surface of the main body. The main body includes a plurality of stacked layer portions. A method of manufacturing the layered chip package includes the step of fabricating a layered substructure and the step of cutting the layered substructure. The layered substructure includes: a plurality of arrayed pre-separation main bodies; a plurality of accommodation parts disposed between two adjacent pre-separation main bodies; and a plurality of preliminary wires accommodated in the accommodation parts. The accommodation parts are formed in a photosensitive resin layer by photolithography. In the step of cutting the layered substructure, the plurality of pre-separation main bodies are separated from each other, and the wires are formed by the preliminary wires.

Abstract: A method includes providing a pad chip having contact pads, providing a spring chip having micro-springs, applying a chemical activator to one of either the pad chip or the spring chip, applying an adhesive responsive to the chemical activator on the other of the pad chip or the spring chip, aligning the pad chip to the spring chip such that the micro-springs will contact the contact pads, and pressing the pad chip and the spring chip together such that the chemical activator at least partially cures the adhesive.

Abstract: A package includes a first plated area, a second plated area, a die attached to the first plated area, and a bond coupling the die to the second plated area. The package further includes a molding encapsulating the die, the bond, and the top surfaces of the first and second plated areas, such that the bottom surfaces of the first and second plated areas are exposed exterior to the package. Additional embodiments include a method of making the package.

Abstract: To provide a technique that can improve the data retention characteristic of an MRAM device by improving the resistance against an external magnetic field in a semiconductor device including the MRAM device. A first magnetic shield material is disposed over a die pad via a first die attach film. Then, a semiconductor chip is mounted over the first magnetic shield material via a second die attach film. Furthermore, a second magnetic shield material is disposed over the semiconductor chip via a third die attach film. That is, the semiconductor chip is disposed so as to be sandwiched by the first magnetic shield material and the second magnetic shield material. At this time, while the planar area of the second magnetic shield material is smaller than that of the first magnetic shield material, the thickness of the second magnetic shield material is thicker than that of the first magnetic shield material.

Abstract: An integrated circuit package system includes: forming an anti-peel pad having both a concave ring and an external terminal with the concave ring, having a peripheral wall, surrounding the external terminal; connecting an integrated circuit with the anti-peel pad; and forming an encapsulation over the integrated circuit, the concave ring, and the external terminal with the encapsulation under the peripheral wall.

Abstract: A chip packaging method includes the steps of: attaching a first tape to a metal plate; patterning the metal plate to form a plurality of terminal pads and a plurality of leads, wherein the plurality of terminal pads and the plurality of leads are disposed on two opposite sides of a central void region, the plurality of terminal pads on each side are arranged in at least two rows spaced apart from each other in the direction away from the central void region, and each lead has a first end portion extending to the central void region and a second end portion connecting to a corresponding terminal pad; attaching a second tape having openings to the plurality of terminal pads, wherein each of the openings exposes the central void region and the first end portions of the leads; removing the first tape; attaching a chip to the plurality of terminal pads and the plurality of leads, wherein a plurality of bond pads on the chip are corresponding to the central void region; and connecting the bond pads to the first en

Abstract: The present invention relates to a surface mount package for a silicon condenser microphone and methods for manufacturing the surface mount package. The surface mount package uses a limited number of components which simplifies manufacturing and lowers costs, and features a substrate that performs functions for which multiple components were traditionally required, including providing an interior surface on which the silicon condenser die is mechanically attached, providing an interior surface for making electrical connections between the silicon condenser die and the package, and providing an exterior surface for surface mounting the package to a device's printed circuit board and for making electrical connections between package and the device's printed circuit board.

Abstract: The present invention proposes a semiconductor device structure and a method for manufacturing the same, and relates to the semiconductor manufacturing industry. The method comprises: providing a semiconductor substrate; forming gate electrode lines on the semiconductor substrate; forming sidewall spacers on both sides of the gate electrode lines; forming source/drain regions on the semiconductor substrates at both sides of the gate electrode lines; forming contact holes on the gate electrode lines or on the source/drain regions; and cutting off the gate electrode lines to form electrically isolated gate electrodes after formation of the sidewall spacers but before completion of FEOL process for a semiconductor device structure. The embodiments of the present invention are applicable for manufacturing integrated circuits.

Abstract: A method of fabricating a thin film transistor includes forming an active layer on an insulating substrate; forming a gate insulation film on the insulating substrate; forming source, drain, and body contact regions which are separated by a channel region in the active layer; forming a gate on the gate insulation film; forming an interlayer insulation film on the insulating substrate; and forming source and drain electrodes electrically connected with the source and drain regions, respectively, wherein a voltage is applied to the channel region of the active layer through the body contact region, and the body contact region is connected to the source or drain electrode.

Abstract: A method of manufacturing a thin film transistor array substrate includes forming a gate pattern on a substrate, forming a gate insulating film on the substrate, forming a source/drain pattern and a semiconductor pattern on the substrate, forming first, second, and third passivation films successively on the substrate. Over the above multi-layered passivation film forming a first photoresist pattern including a first portion formed on part of the drain electrode and on the pixel region, and a second portion. The second portion is thicker than the first portion. Then, patterning the third passivation film using the first photoresist pattern, forming a second photoresist pattern by removing the first portion of the first photoresist pattern, forming a transparent electrode film on the substrate, removing the second photoresist pattern and the transparent electrode film disposed on the second photoresist pattern, and forming a transparent electrode pattern on the second passivation layer.

Abstract: The present invention relates to a method for providing a Silicon-On-Insulator (SOI) stack that includes a substrate layer, a first oxide layer on the substrate layer and a silicon layer on the first oxide layer (BOX layer). The method includes providing at least one first region of the SOI stack wherein the silicon layer is thinned by thermally oxidizing a part of the silicon layer and providing at least one second region of the SOI stack wherein the first oxide layer (BOX layer) is thinned by annealing.

Abstract: A method of forming an SOI structure which includes providing a semiconductor on insulator (SOI) substrate having an SOI layer, an intermediate buried oxide (BOX) layer and a bottom substrate; patterning the SOI layer to form first and second openings in the SOI layer; extending the first openings into the bottom substrate; enlarging the first openings within the bottom substrate; filling the first and second openings with an insulator material to form deep trench isolations (DTIs) from the first openings and shallow trench isolations (STIs) from the second openings; implanting in the bottom substrate between the DTIs to form wells; and forming semiconductor devices in the SOI layer between the DTIs with each semiconductor device being separated from an adjacent semiconductor device by an STI.

Abstract: When forming sophisticated semiconductor devices, three-dimensional transistors in combination with planar transistors may be formed on the basis of a replacement gate approach and self-aligned contact elements by forming the semiconductor fins in an early manufacturing stage, i.e., upon forming shallow trench isolations, wherein the final electrically effective height of the semiconductor fins may be adjusted after the provision of self-aligned contact elements and during the replacement gate approach.

Abstract: Methods are provided for fabricating an integrated circuit that includes metal filled narrow openings. In accordance with one embodiment a method includes forming a dummy gate overlying a semiconductor substrate and subsequently removing the dummy gate to form a narrow opening. A layer of high dielectric constant insulator and a layer of work function-determining material are deposited overlying the semiconductor substrate. The layer of work function-determining material is exposed to a nitrogen ambient in a first chamber. A layer of titanium is deposited into the narrow opening in the first chamber in the presence of the nitrogen ambient to cause the first portion of the layer of titanium to be nitrided. The deposition of titanium continues, and the remaining portion of the layer of titanium is deposited as substantially pure titanium. Aluminum is deposited overlying the layer of titanium to fill the narrow opening and to form a gate electrode.

Abstract: The present invention discloses a semiconductor device, comprising a plurality of fins located on a substrate and extending along a first direction; a plurality of gate stack structures extending along a second direction and across each of the fins; a plurality of stress layers located in the fins on both sides of the gate stack structures and having a plurality of source and drain regions therein; a plurality of channel regions located between the plurality of source and drain regions along a first direction; characterized in that the plurality of gate stack structures enclose the plurality of channel regions. In accordance with the semiconductor device and the method of manufacturing the same of the present invention, an all-around nanowire metal multi-gate is formed in self-alignment by punching through and etching the fins at which the channel regions are located using a combination of the hard mask and the dummy gate, thus the device performance is enhanced.

Abstract: Some example embodiments of the invention comprise methods for and semiconductor structures comprised of: a MOS transistor comprised of source/drain regions, a gate dielectric, a gate electrode, channel region; a carbon doped SiGe region that applies a stress on the channel region whereby the carbon doped SiGe region retains stress/strain on the channel region after subsequent heat processing.

Abstract: A semiconductor device and its manufacturing method, wherein the NMOS device is covered by a layer of silicon nitride film having a high ultraviolet light absorption coefficient through PECVD, said silicon nitride film can well absorb ultraviolet light when being subject to the stimulated laser surface anneal so as to achieve a good dehydrogenization effect, and after dehydrogenization, the silicon nitride film will have a high tensile stress; since the silicon nitride film has a high ultraviolet light absorption coefficient, there is no need to heat the substrate, thus avoiding the adverse influences to the device caused by heating the substrate to dehydrogenize, and maintaining the heat budget brought about by the PECVD process.

Abstract: A FinFET device and method for fabricating a FinFET device is disclosed. An exemplary method includes forming a fin structure on a semiconductor substrate and forming a gate structure on the fin structure. A capping layer is then formed over the semiconductor substrate, fin structure, and gate structure. The capping layer is patterned to form an opening exposing a second portion of the fin structure. An epitaxial layer is grown in the opening and on the second portion of the fin structure. At least one of a source region and a drain region is provided in the epitaxial layer. The method may continue to remove the capping layer.

Abstract: A memory cell of an SRAM has two drive MISFETs and two vertical MISFETs. The p channel vertical MISFETs are formed above the n channel drive MISFETs. The vertical MISFETs respectively mainly include a laminate formed of a lower semiconductor layer, intermediate semiconductor layer and upper semiconductor layer laminated in this sequence, a gate insulating film of silicon oxide formed on the surface of the side wall of the laminate, and a gate electrode formed so as to cover the side wall of the laminate. The vertical MISFETs are perfect depletion type MISFETs.

Abstract: A SRAM includes a first CMOS inverter of first and second MOS transistors connected in series, a second CMOS inverter of third and fourth MOS transistors connected in series and forming a flip-flop circuit together with the first CMOS inverter, and a polysilicon resistance element formed on a device isolation region, each of the first and third MOS transistors is formed in a device region of a first conductivity type and includes a second conductivity type drain region at an outer side of a sidewall insulation film of the gate electrode with a larger depth than a drain extension region thereof, wherein a source region is formed deeper than a drain extension region, the polysilicon gate electrode has a film thickness identical to a film thickness of the polysilicon resistance element, the source region and the polysilicon resistance element are doped with the same dopant element.

Abstract: Provided are semiconductor memory devices and the methods of fabricating the same. The method may include forming a plurality of diode patterns in each of a plurality of first trenches, each of the plurality of first trenches including at least two active regions, the plurality of diode patterns occupying a plurality of spaces, treating the plurality of diode patterns to form a plurality of semiconductor patterns in each of the plurality of spaces, removing portions of the plurality of semiconductor patterns to form a recess in each of the plurality of spaces, treating the of the plurality of semiconductor patterns to form a plurality of diodes in each of the plurality of spaces, forming a bottom electrode on each of the plurality of diodes, forming a plurality of memory elements on each of the bottom electrodes, and forming a plurality of upper interconnection lines on the plurality of memory elements.

Abstract: A transistor region of a first semiconductor layer and a capacitor region in the first semiconductor layer are isolated. A dummy gate structure is formed on the first semiconductor layer in the transistor region. A second semiconductor layer is formed on the first semiconductor layer. First and second portions of the second semiconductor layer are located in the transistor region, and a third portion of the second semiconductor layer is located in the capacitor region. First, second, and third silicide regions are formed on the first, second, and third portions of the second semiconductor layer, respectively. After forming a dielectric layer, the dummy gate structure is removed forming a first cavity. At least a portion of the dielectric layer located above the third silicide region is removed forming a second cavity. A gate dielectric is formed in the first cavity and a capacitor dielectric in the second cavity.

Abstract: The present invention provides a pixel structure including a substrate, a patterned electrode disposed on the substrate, a first insulating layer disposed on the patterned electrode, a common electrode disposed on the first insulating layer, a second insulating layer disposed on the common electrode, and a drain disposed on the second insulating layer. The first insulating layer has a first through hole, and the second insulating layer has a second through hole. The drain includes a first portion electrically connected to the patterned electrode via the first through hole and the second through hole, and a second portion extending onto the common electrode. The common electrode is coupled with the patterned electrode to form a first storage capacitor and is coupled with the second portion to form a second storage capacitor.

Abstract: A trench MOSFET structure with ultra high cell density is disclosed, wherein the source regions and the body regions are located in different regions to save the mesa area between every two adjacent gate trenches in the active area. Furthermore, the inventive trench MOSFET is composed of stripe cells to further increase cell packing density and decrease on resistance Rds between the drain region and the source region.

Abstract: A method for fabricating vertical surround gate structures in semiconductor device arrays. The method includes forming pillars separated by vertical and horizontal trenches on a substrate. Forming a gate layer over the pillars and trenches such that the gate layer forms gate trenches in the horizontal trenches. The method includes forming fillers within the gate trenches, and planarizing the gate layer and fillers. The method also includes successively etching a first portion of the gate layer, removing the fillers, and etching a second portion of the gate layer.

Abstract: Disclosed are methods for manufacturing a floating gate memory device and the floating gate memory device thus obtained. In one embodiment, a method is disclosed that includes providing a semiconductor-on-insulator substrate, forming at least two trenches in the semiconductor-on-insulator substrate, and, as a result of forming the at least two trenches, forming at least one elevated structure. The method further includes forming isolation regions at a bottom of the at least two trenches by partially filling the at least two trenches, thermally oxidizing sidewall surfaces of at least a top portion of the at least one elevated structure, thereby providing a gate dielectric layer on at least the exposed sidewall surfaces; and forming a conductive layer over the at least one elevated structure, the gate dielectric layer, and the isolation regions to form at least one floating gate semiconductor memory device.

Abstract: An access transistor for a resistance variable memory element and methods of forming the same are provided. The access transistor has first and second source/drain regions and a channel region vertically stacked over the substrate. The access transistor is associated with at least one resistance variable memory element.

Abstract: A method of manufacturing a semiconductor device is presented. The device has: a gate terminal formed from polysilicon and covered by an insulation layer; and a plug extending through an insulation layer to provide an electrical connection to the gate trench. A metal layer is deposited to cover at least a portion of the insulation layer. The metal layer is then etched to remove the metal layer from above the plug.