Patents Issued in February 18, 2014
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Patent number: 8652906Abstract: A method for manufacturing a semiconductor device and semiconductor device. One embodiment provides a semiconductor substrate with an active region and a margin region bordering on the active region. The spacer layer in the margin region is broken through at a selected location and at least part of the spacer layer is removed in the active region using a common process. The location is selected such that at least part of the semiconductor mesa structure is exposed and the spacer layer in the margin region is broken through to the conductive layer and not to the semiconductor substrate.Type: GrantFiled: May 21, 2013Date of Patent: February 18, 2014Assignee: Infineon Technologies Austria AGInventors: Martin Poelzl, Walter Rieger, Markus Zundel
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Patent number: 8652907Abstract: A method of fabricating an integrated circuit including a first region and a second region each having different poly-silicon gate structures is provided. The method includes depositing a first poly-silicon layer over the first and the second region and depositing, within the second region, an oxide layer over the first poly-silicon layer. A second poly-silicon layer is deposited over the first poly-silicon layer and the oxide region. A portion of the second poly-silicon layer that lies over the oxide region is then stripped away.Type: GrantFiled: March 24, 2011Date of Patent: February 18, 2014Assignee: Spansion LLCInventors: Chuan Lin, Hidehiko Shiraiwa, Bradley Marc Davis, Lei Xue, Simon S. Chan, Kenichi Ohtsuka, Angela T. Hui, Scott Allan Bell
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Patent number: 8652908Abstract: A method of fabricating a semiconductor device includes providing a semiconductor substrate having a first region and a second region, forming a nitrogen-containing lower gate insulating layer on the semiconductor substrate, forming an upper gate insulating layer on the nitrogen containing lower gate insulating layer, forming a lower metal layer on the upper gate insulating layer; and selectively removing the lower metal layer in the first region such that a lower metal layer pattern remains in the second region, wherein the upper gate insulating layer in the first region prevents the lower gate insulating layer in the first region from being etched during removing of the lower metal layer in the first region. A semiconductor device fabricated by the method is also provided.Type: GrantFiled: September 22, 2011Date of Patent: February 18, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: WeonHong Kim, Dae-Kwon Joo
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Patent number: 8652909Abstract: A method of forming a nonvolatile memory cell includes forming a first electrode and a second electrode of the memory cell. Sacrificial material is provided between the first second electrodes. The sacrificial material is exchanged with programmable material. The sacrificial material may additionally be exchanged with select device material.Type: GrantFiled: June 25, 2012Date of Patent: February 18, 2014Assignee: Micron Technology, Inc.Inventors: Scott E. Sills, Gurtej S. Sandhu
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Patent number: 8652910Abstract: In a method for fabricating a semiconductor device, a substrate may be provided that includes: a base, an active fin that projects from an upper surface of the base and is integrally formed with the base, and a buffer oxide film pattern formed on the active fin in contact with the active fin. A first dummy gate film may be formed on the substrate to cover the buffer oxide film pattern and the first dummy gate film may be smoothed to expose the buffer oxide film pattern. A second dummy gate film may be formed on the exposed buffer oxide film pattern and the first dummy gate film.Type: GrantFiled: April 3, 2012Date of Patent: February 18, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Bo-Kyeong Kang, Jae-Seok Kim, Ho-Young Kim, Bo-Un Yoon, Il-Young Yoon
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Patent number: 8652911Abstract: A method of fabricating a semiconductor device includes forming a device isolation region on a semiconductor substrate to define an active region, forming a gate electrode on the active region and the device isolation region across the active region, and forming at least one gate electrode opening portion in the gate electrode so as to overlap an edge portion of the active region, wherein the gate electrode opening portion is simultaneously formed with the gate electrode.Type: GrantFiled: July 1, 2011Date of Patent: February 18, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Kee-In Bang, Tae-Jung Lee, Myoung-Kyu Park
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Patent number: 8652912Abstract: A method for fabricating a transistor gate with a conductive element that includes cobalt silicide includes use of a sacrificial material as a place-holder between sidewall spacers of the transistor gate until after high temperature processes, such as the fabrication of raised source and drain regions, have been completed. In addition, semiconductor devices (e.g., DRAM devices and NAND flash memory devices) with transistor gates that include cobalt silicide in their conductive elements are also disclosed, as are transistors with raised source and drain regions and cobalt silicide in the transistor gates thereof. Intermediate semiconductor device structures that include transistor gates with sacrificial material or a gap between upper portions of sidewall spacers are also disclosed.Type: GrantFiled: December 8, 2006Date of Patent: February 18, 2014Assignee: Micron Technology, Inc.Inventor: Yongjun Jeff Hu
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Patent number: 8652913Abstract: By providing a protection layer on a silicon/germanium material of high germanium concentration, a corresponding loss of strained semiconductor material may be significantly reduced or even completely avoided. The protection layer may be formed prior to critical cleaning processes and may be maintained until the formation of metal silicide regions. Hence, high performance gain of P-type transistors may be accomplished without requiring massive overfill during the selective epitaxial growth process.Type: GrantFiled: July 17, 2007Date of Patent: February 18, 2014Assignee: GLOBALFOUNDRIES Inc.Inventors: Andreas Gehring, Maciej Wiatr, Andy Wei, Thorsten Kammler, Roman Boschke, Casey Scott
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Patent number: 8652914Abstract: An aspect of the invention includes a method for forming a semiconductor device with a two-step silicide formation. First, a silicide intermix layer is formed over a source/drain region and a portion of an adjacent extension region. Any spacers removed to accomplish this may be replaced. Dielectric material covers the silicide intermix layer over the source/drain region. A contact opening for a via is etched into the dielectric material. A second silicide contact is formed on the silicide intermix layer, or may be formed within the source/drain region as long as the second silicide contact still contacts the silicide intermix layer.Type: GrantFiled: March 3, 2011Date of Patent: February 18, 2014Assignee: International Business Machines CorporationInventors: Emre Alptekin, Sameer Hemchand Jain, Reinaldo Ariel Vega
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Patent number: 8652915Abstract: A method of fabricating a semiconductor device can be provided by etching sidewalls of a preliminary trench in a substrate that are between immediately adjacent gate electrode structures, to recess the sidewalls further beneath the gate electrode structures to provide recessed sidewalls. Then, the recessed sidewalls and a bottom of the preliminary trench can be etched using crystallographic anisotropic etching to form a hexagonally shaped trench in the substrate.Type: GrantFiled: August 18, 2011Date of Patent: February 18, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Kevin Ahn, Sang-Jine Park, Jae-Jik Baek, Bo-Un Yoon, Jeong-Nam Han
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Patent number: 8652916Abstract: A method of forming a semiconductor structure, including forming a gate structure on a substrate; performing a first angled implantation on a first side of the gate structure to form a first doped region in the substrate, the first doped region partially extends within a channel of the gate structure and the gate structure blocks the first angled implantation from affecting the substrate on a second side of the gate structure; forming sidewall spacers on sidewalls of the gate; and forming a second doped region in the substrate on the second side of the gate, spaced apart from the channel.Type: GrantFiled: March 22, 2012Date of Patent: February 18, 2014Assignee: International Business Machines CorporationInventors: Roger A. Booth, Jr., Paul Chang, Kangguo Cheng, Chengwen Pei, William R. Tonti
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Patent number: 8652917Abstract: When forming sophisticated transistors on the basis of a high-k metal gate electrode structure and a strain-inducing semiconductor alloy, a superior wet cleaning process strategy is applied after forming cavities in order to reduce undue modification of sensitive gate materials, such as high-k dielectric materials, metal-containing electrode materials and the like, and modification of a threshold voltage adjusting semiconductor alloy. Thus, the pronounced dependence of the threshold voltage of transistors of different width may be significantly reduced compared to conventional strategies.Type: GrantFiled: May 23, 2012Date of Patent: February 18, 2014Assignee: GLOBALFOUNDRIES, Inc.Inventors: Markus Lenski, Stephan Kronholz, Nadja Zakowsky
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Patent number: 8652918Abstract: A structure method for producing same provides suppressed lattice defects when epitaxially forming nitride layers over non-c-plane oriented layers, such as a semi-polar oriented template layer or substrate. A patterned mask with “window” openings, or trenches formed in the substrate with appropriate vertical dimensions, such as the product of the window width times the cotangent of the angle between the surface normal and the c-axis direction, provides significant blocking of all diagonally running defects during growth. In addition, inclined posts of appropriate height and spacing provide a blocking barrier to vertically running defects is created. When used in conjunction with the aforementioned aspects of mask windows or trenches, the post structure provides significant blocking of both vertically and diagonally running defects during growth.Type: GrantFiled: May 17, 2012Date of Patent: February 18, 2014Assignee: Palo Alto Research Center IncorporatedInventor: Andre Strittmatter
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Patent number: 8652919Abstract: Embodiments of the present invention include a method for forming a tunable semiconductor device. In one embodiment, the method comprises: forming a semiconductor substrate; patterning a first mask over the semiconductor substrate; doping regions of the semiconductor substrate not protected by the first mask to form a first discontinuous subcollector; removing the first mask; patterning a second mask over the semiconductor substrate; doping regions of the semiconductor substrate not protected by the second mask and on top of the first discontinuous subcollector to form a second discontinuous subcollector; removing the second mask; and forming a single continuous collector above the second discontinuous subcollector.Type: GrantFiled: January 14, 2013Date of Patent: February 18, 2014Assignee: International Business Machines CorporationInventors: David L. Harame, Alvin J. Joseph, Qizhi Liu, Ramana M. Malladi
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Patent number: 8652920Abstract: A process for forming a laminate with capacitance and the laminate formed thereby. The process includes the steps of providing a substrate and laminating a conductive foil on the substrate wherein the foil has a dielectric. A conductive layer is formed on the dielectric. The conductive foil is treated to electrically isolate a region of conductive foil containing the conductive layer from additional conductive foil. A cathodic conductive couple is made between the conductive layer and a cathode trace and an anodic conductive couple is made between the conductive foil and an anode trace.Type: GrantFiled: March 1, 2012Date of Patent: February 18, 2014Assignee: Kamet Electronics CorporationInventors: John D. Prymak, Chris Stolarski, Alethla Melody, Antony P. Chacko, Gregory J. Dunn
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Patent number: 8652921Abstract: A semiconductor device has a substrate that includes a cell array region and a dummy pattern region surrounding the cell array region. The cell array region includes a cell structure having a plurality of cell active pillars extending in a vertical direction from the cell array region of the substrate and includes cell gate patterns and cell gate interlayer insulating patterns alternately stacked on the substrate. The cell gate patterns and cell gate interlayer insulating patterns have sides facing the cell active pillars. The dummy pattern region includes a damp-proof structure.Type: GrantFiled: February 5, 2013Date of Patent: February 18, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Seung-Jun Lee, Woonkyung Lee
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Patent number: 8652922Abstract: A method of forming a semiconductor structure includes forming a resistor on an insulator layer over a substrate and forming a trench in the resistor and into the substrate. The method also includes forming a liner on sidewalls of the trench and forming a core comprising a high thermal conductivity material in the trench and on the liner.Type: GrantFiled: January 18, 2011Date of Patent: February 18, 2014Assignee: International Business Machines CorporationInventors: Joseph M. Lukaitis, Jed H. Rankin, Robert R. Robison, Dustin K. Slisher, Timothy D. Sullivan
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Patent number: 8652923Abstract: Embodiments of the invention generally relate to a resistive switching nonvolatile memory device having an interface layer structure disposed between at least one of the electrodes and a variable resistance layer formed in the nonvolatile memory device, and a method of forming the same. Typically, resistive switching memory elements may be formed as part of a high-capacity nonvolatile memory integrated circuit, which can be used in various electronic devices, such as digital cameras, mobile telephones, handheld computers, and music players. In one configuration of the resistive switching nonvolatile memory device, the interface layer structure comprises a passivation region, an interface coupling region, and/or a variable resistance layer interface region that are configured to adjust the nonvolatile memory device's performance, such as lowering the formed device's switching currents and reducing the device's forming voltage, and reducing the performance variation from one formed device to another.Type: GrantFiled: March 14, 2013Date of Patent: February 18, 2014Assignees: Intermolecular, Inc., Kabushiki Kaisha Toshiba, SanDisk 3D LLCInventors: Yun Wang, Tony P. Chiang, Imran Hashim
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Patent number: 8652924Abstract: A storage node is formed in a semiconductor device by forming an interlayer insulation layer on a substrate, forming an etch stop layer and a first sacrificial layer on the interlayer insulation layer, patterning the first sacrificial layer and the etch stop layer to form a first sacrificial layer pattern and an etch stop layer pattern that define a storage node contact hole, forming a recessed first storage node conductive pattern that conformally covers a lower sidewall and a bottom surface of the storage node contact hole, forming a second storage node conductive pattern that includes a first portion surrounded by the recessed first storage node conductive pattern and a second portion conformally covering an upper sidewall of the storage node contact hole, and removing the first sacrificial layer pattern. The recessed first storage node conductive pattern and the second storage node conductive pattern constitute a storage node.Type: GrantFiled: February 14, 2012Date of Patent: February 18, 2014Assignee: SK Hynix Inc.Inventors: Han Sang Song, Jong Kook Park
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Patent number: 8652925Abstract: A structure and method is provided for fabricating isolated capacitors. The method includes simultaneously forming a plurality of deep trenches and one or more isolation trenches surrounding a group or array of the plurality of deep trenches through a SOI and doped poly layer, to an underlying insulator layer. The method further includes lining the plurality of deep trenches and one or more isolation trenches with an insulator material. The method further includes filling the plurality of deep trenches and one or more isolation trenches with a conductive material on the insulator material. The deep trenches form deep trench capacitors and the one or more isolation trenches form one or more isolation plates that isolate at least one group or array of the deep trench capacitors from another group or array of the deep trench capacitors.Type: GrantFiled: July 19, 2010Date of Patent: February 18, 2014Assignee: International Business Machines CorporationInventors: Oh-Jung Kwon, Junedong Lee, Paul C. Parries, Dominic J. Schepis
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Patent number: 8652926Abstract: A method of forming capacitors includes providing first capacitor electrodes within support material. The first capacitor electrodes contain TiN and the support material contains polysilicon. The polysilicon-containing support material is dry isotropically etched selectively relative to the TiN-containing first capacitor electrodes using a sulfur and fluorine-containing etching chemistry. A capacitor dielectric is formed over sidewalls of the first capacitor electrodes and a second capacitor electrode is formed over the capacitor dielectric. Additional methods are disclosed.Type: GrantFiled: July 26, 2012Date of Patent: February 18, 2014Assignee: Micron Technology, Inc.Inventors: Gurpreet Lugani, Kevin J. Torek
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Patent number: 8652927Abstract: A method for forming a capacitor stack is described. In some embodiments of the present invention, a first electrode structure is comprised of multiple materials. A first material is formed above the substrate. A portion of the first material is etched. A second material is formed above the first material. A portion of the second material is etched. Optionally, the first electrode structure receives an anneal treatment. A dielectric material is formed above the first electrode structure. Optionally, the dielectric material receives an anneal treatment. A second electrode material is formed above the dielectric material. Typically, the capacitor stack receives an anneal treatment.Type: GrantFiled: January 10, 2013Date of Patent: February 18, 2014Assignee: Intermolecular, Inc.Inventors: Sandra Malhotra, Hanhong Chen, Wim Y. Deweerd, Edward L. Haywood, Hiroyuki Ode, Gerald Richardson
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Patent number: 8652928Abstract: A semiconductor device includes a substrate having a first area and a second area, a first transistor in the first area, a second transistor in the second area, an isolation layer between the first area and the second area, and at least one buried shield structure on the isolation layer.Type: GrantFiled: September 22, 2011Date of Patent: February 18, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Young-Bae Yoon, Jeong-Dong Choe, Dong-Hoon Jang, Ki-Hyun Kim
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Patent number: 8652929Abstract: The present invention discloses a CMOS device of reducing charge sharing effect and a fabrication method thereof. The present invention has an additional isolation for trapping carriers disposed right below an isolation region. the material of the additional isolation region is porous silicon. Since porous silicon is a functional material of spongy structure by electrochemistry anodic oxidizing monocrystalline silicon wafer, there are a large number of microvoids and dangling bonds on the surface layer of the porous silicon. These defects may form defect states in a center of forbidden band of the porous silicon, the defect states may trap carriers so as to cause an increased resistance. And with an increase of density of corrosion current, porosity increases, and defects in the porous silicon increase.Type: GrantFiled: April 16, 2012Date of Patent: February 18, 2014Assignee: Peking UniversityInventors: Ru Huang, Fei Tan, Xia An, Qianqian Huang, Dong Yang, Xing Zhang
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Patent number: 8652930Abstract: A method of fabricating a reduced surface field (RESURF) transistor includes forming a first well in a substrate, the first well having a first conductivity type, doping a RESURF region of the first well to have a second conductivity type, doping a portion of the first well to form a drain region of the RESURF transistor, the drain region having the first conductivity type, and forming a second well in the substrate, the second well having the second conductivity type. A plug region is formed in the substrate, the plug region extending to the RESURF region.Type: GrantFiled: August 22, 2013Date of Patent: February 18, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Hongning Yang, Jiang-Kai Zuo
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Patent number: 8652931Abstract: The present invention is related to the trench manufacturing field in semiconductor, especially a manufacturing method of STI structure with difference depth which is apply to the imaging sensor including forming a dielectric layer with different thickness on the substrate which includes a first region and a second region, then forming a first type trench in the thick dielectric layer and a second type trench in the thin dielectric layer, and etching the substrate of the first region and the substrate of the second region, and thus form a first STI and a second STI with different depth which are located in the substrate of the first region and the second region respectively.Type: GrantFiled: December 27, 2012Date of Patent: February 18, 2014Assignee: Shanghai Huali Microelectronics CorporationInventor: Fei Luo
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Patent number: 8652932Abstract: A semiconductor device including at least two fin structures on a substrate surface and a functional gate structure present on the at least two fin structures. The functional gate structure includes at least one gate dielectric that is in direct contact with at least the sidewalls of the two fin structures, and at least one gate conductor on the at least one gate dielectric. The sidewall of the gate structure is substantially perpendicular to the upper surface of the substrate surface, wherein the plane defined by the sidewall of the gate structure and a plane defined by an upper surface of the substrate surface intersect at an angle of 90°+/?5°. An epitaxial semiconductor material is in direct contact with the at least two fin structures.Type: GrantFiled: April 17, 2012Date of Patent: February 18, 2014Assignee: International Business Machines CorporationInventors: Thomas N. Adam, Kangguo Cheng, Ali Khakifirooz, Alexander Reznicek
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Patent number: 8652933Abstract: Disclosed is a method of forming a semiconductor device structure in a semiconductor layer. The method includes forming a first trench of a first width and a second trench of a second width in the semiconductor layer; depositing a layer of first material which conforms to a wall of the first trench but does not fill it and which fills the second trench; removing the first material from the first trench, the first material remaining in the second trench; depositing a second material into and filling the first trench and over a top of the first material in the second trench; and uniformly removing the second material from the top of the first material in the second trench, wherein the first trench is filled with the second material and the second trench is filled with the first material and wherein the first material is different from the second material.Type: GrantFiled: November 11, 2010Date of Patent: February 18, 2014Assignee: International Business Machines CorporationInventors: Paul C. Parries, Yanli Zhang
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Patent number: 8652934Abstract: A method of forming a substrate with isolation areas suitable for integration of electronic and photonic devices is provided. A common reticle and photolithographic technique is used to fabricate a mask defining openings for etching first and second areas in a substrate, with the openings for the second trench isolation areas being wider than the openings for the first trench isolation areas. The first and second trench isolation areas are etched in the substrate through the mask and filled with an oxide material. The oxide material is removed from the bottom of the second trench isolation areas. The second trench isolation areas are further etched to the deeper than the first trench isolation areas, and are then filled with oxide material. Electrical devices can be formed on the substrate and electrically isolated by the first trench isolation areas and photonic devices can be formed over the second trench isolation areas and be optically isolated from the substrate.Type: GrantFiled: December 26, 2012Date of Patent: February 18, 2014Assignee: Micron Technology, Inc.Inventors: Roy Meade, Gurtej Sandhu
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Patent number: 8652935Abstract: A method of bonding first and second microelectronic elements includes pressing together a first substrate containing active circuit elements therein with a second substrate, with a flowable dielectric material between confronting surfaces of the respective substrates, each of the first and second substrates having a coefficient of thermal expansion less than 10 parts per million/° C., at least one of the confronting surfaces having a plurality of channels extending from an edge of such surface, such that the dielectric material between planes defined by the confronting surfaces is at least substantially free of voids and has a thickness over one micron, and at least some of the dielectric material flows into at least some of the channels.Type: GrantFiled: December 16, 2010Date of Patent: February 18, 2014Assignee: Tessera, Inc.Inventors: Ilyas Mohammed, Piyush Savalia, Craig Mitchell, Vage Oganesian, Belgacem Haba
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Patent number: 8652936Abstract: A method of forming an optoelectronic device comprising growing a first multi-layer 2 representing a reflector on a first substrate and a second multilayer 4 representing an active region on a second substrate, the first and second substrates being lattice mismatched, fusing the first multi-layer 2 to a third substrate 3, wherein the material of the third substrate 3 is lattice matched with respect to the material of the second multi-layer 4, removing the first substrate to expose the first multi-layer 2, and fusing the first multi-layer to the second multi-layer 4.Type: GrantFiled: July 1, 2010Date of Patent: February 18, 2014Assignee: Ecole Polytechnique Federale de LausanneInventors: Alexei Sirbu, Alexandru Mereuta, Andrei Caliman
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Patent number: 8652937Abstract: A back-illuminated semiconductor imaging device on a semiconductor-on-insulator substrate is disclosed. The device includes an insulator layer, a semiconductor substrate having an interface with the insulator layer, an epitaxial layer grown on the semiconductor substrate; and one or more imaging components in the epitaxial layer. The semiconductor substrate and the epitaxial layer exhibit a net doping concentration profile having a maximum value at a predetermined distance from the interface which decreases monotonically on both sides of the profile. The doping profile between the interface with the insulation layer and the peak of the doping profile functions as a “dead band” to prevent dark current carriers from penetrating to the front side of the device.Type: GrantFiled: March 13, 2012Date of Patent: February 18, 2014Assignee: SRI InternationalInventors: Levine Peter Alan, Pradyumna Swain, Mahalingam Bhaskaran
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Patent number: 8652938Abstract: The present invention relates to a thermally releasable sheet-integrated film for semiconductor back surface, which includes: a pressure-sensitive adhesive sheet including a base material layer and a pressure-sensitive adhesive layer, and a film for semiconductor back surface formed on the pressure-sensitive adhesive layer of the pressure-sensitive adhesive sheet, in which the pressure-sensitive adhesive sheet is a thermally releasable pressure-sensitive adhesive sheet whose peel force from the film for semiconductor back surface decreases upon heating.Type: GrantFiled: July 26, 2011Date of Patent: February 18, 2014Assignee: Nitto Denko CorporationInventors: Naohide Takamoto, Goji Shiga, Fumiteru Asai
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Patent number: 8652939Abstract: Methods and apparatus for die assembly. A method includes forming a trench extending from an active surface of a semiconductor substrate comprising a plurality of integrated circuit dies having connector terminals extending from the active surface, the trench extending into, but not through, the semiconductor substrate; forming a protective layer overlying the active surface of the semiconductor substrate and the trench, and covering the lower portion of the connector terminals; opening a pre-dicing opening in the protective layer and within the trench; applying a tape over the active surface of the semiconductor wafer, the protective layer and the connector terminals; and performing an operation on a backside of the semiconductor substrate to remove material until the pre-dicing opening is exposed on the backside of the semiconductor wafer. An apparatus includes a semiconductor substrate with integrated circuits and a protective layer surrounding connector terminals of integrated circuits.Type: GrantFiled: October 18, 2011Date of Patent: February 18, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming-Chung Sung, Yu-Chih Liu, Wei-Ting Lin, Chien-Hsiun Lee
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Patent number: 8652940Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer. The mask is composed of a layer covering and protecting the integrated circuits. The mask is patterned with a multi-step laser scribing process to provide a patterned mask with gaps. The patterning exposes regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then etched through the gaps in the patterned mask to singulate the integrated circuits.Type: GrantFiled: March 27, 2013Date of Patent: February 18, 2014Assignee: Applied Materials, Inc.Inventors: Wei-Sheng Lei, Brad Eaton, Madhava Rao Yalamanchili, Saravjeet Singh, Ajay Kumar
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Patent number: 8652941Abstract: In one embodiment, a dielectric material layer embedding metal structures is ablated from the chip-containing substrate by laser grooving, which is performed on dicing channels of the chip-containing substrate. Subsequently, an underfill layer is formed over the dielectric material layer in a pattern that excludes the peripheral areas of the chip-containing substrate. The physically exposed dicing channels at the periphery can be employed to align a blade to dice the chip-containing substrate. In another embodiment, an underfill layer is formed prior to any laser grooving. Mechanical cutting of the underfill layer from above dicing channels is followed by laser ablation of the dicing channels and subsequent mechanical cutting to dice a chip-containing substrate.Type: GrantFiled: May 17, 2012Date of Patent: February 18, 2014Assignees: International Business Machines Corporation, Disco Corporation, Sumitomo Bakelite Company Ltd.Inventors: Richard F. Indyk, Jae-Woong Nah, Satoru Katsurayama, Daisuke Oka, Shigefumi Okada
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Patent number: 8652942Abstract: A method for manufacturing electronic parts, which is characteristic in that it permits reduction of contamination to the semi-cured adhesive layer formed on semiconductor wafer and the cohesive sheet used therein is superior in adhesiveness for example to the lead frame, the method comprising a semi-cured adhesive layer-forming step of forming a semi-cured adhesive layer by coating a pasty adhesive entirely over the rear face of a wafer and curing the pasty adhesive partially by radiation-ray irradiation or heating into the sheet shape, a fixing step of fixing the semi-cured adhesive layer formed on a wafer and a ring frame by bonding them to the cohesive layer of a cohesive sheet, a dicing step of dicing the wafer together with the semi-cured adhesive layer with a dicing blade into semiconductor chips, and a pick-up step of picking up the chips carrying the semi-cured adhesive layer from the cohesive layer of the cohesive sheet after radiation-ray irradiation, wherein the photopolymerization initiator in thType: GrantFiled: September 14, 2011Date of Patent: February 18, 2014Assignee: Denki Kagaku Kogyo Kabushiki KaishaInventors: Takeshi Saito, Tomomichi Takatsu
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Patent number: 8652943Abstract: A method of processing a substrate is provided. The method includes providing a substrate, performing a device forming process on the substrate, and cleaning the substrate. The step of cleaning the substrate includes cleaning the substrate with an atomic spray and rinsing the substrate with deionized water.Type: GrantFiled: May 17, 2012Date of Patent: February 18, 2014Assignee: United Microelectronics Corp.Inventor: Tsung-Hsun Tsai
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Patent number: 8652944Abstract: Fabricating semiconductor nanowires (5) on a substrate (1) having a metallic oxide layer (2), includes: a) exposing the metallic oxide layer to a hydrogen plasma (11) of power P for a duration t suitable for reducing the layer and for forming metallic nanodrops (3) of radius (Rm) on the surface of the metallic oxide layer; b) low temperature plasma-assisted deposition of a thin layer (4) of a semiconductor material on the metallic oxide layer including the metallic nanodrops, the thin layer having a thickness (Ha) suitable for covering the metallic nanodrops; and c) thermal annealing at a temperature T sufficient to activate lateral growth of nanowires by catalysis of the material deposited as a thin layer from the metallic nanodrops. Nanowires are obtained by this method and nanometric transistors including a semiconductor nanowire.Type: GrantFiled: October 9, 2009Date of Patent: February 18, 2014Assignees: Ecole Polytechnique, Centre National de la Recherche ScientifiqueInventors: Pere Roca I Cabarrocas, Linwei Yu
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Patent number: 8652945Abstract: Embodiments of the present invention generally relate to methods for forming silicon epitaxial layers on semiconductor devices. The methods include forming a silicon epitaxial layer on a substrate at increased pressure and reduced temperature. The silicon epitaxial layer has a phosphorus concentration of about 1×1021 atoms per cubic centimeter or greater, and is formed without the addition of carbon. A phosphorus concentration of about 1×1021 atoms per cubic centimeter or greater increases the tensile strain of the deposited layer, and thus, improves channel mobility. Since the epitaxial layer is substantially free of carbon, the epitaxial layer does not suffer from film formation and quality issues commonly associated with carbon-containing epitaxial layers.Type: GrantFiled: July 28, 2011Date of Patent: February 18, 2014Assignee: Applied Materials, Inc.Inventors: Zhiyuan Ye, Xuebin Li, Saurabh Chopra, Yihwan Kim
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Patent number: 8652946Abstract: A system and method for forming graphene layers on a substrate. The system and methods include direct growth of graphene on diamond and low temperature growth of graphene using a solid carbon source.Type: GrantFiled: April 16, 2012Date of Patent: February 18, 2014Assignee: Uchicago Argonne, LLC.Inventors: Anirudha V. Sumant, Alexander Balandin
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Patent number: 8652947Abstract: A method for growing flat, low defect density, and strain-free thick non-polar III-V nitride materials and devices on any suitable foreign substrates using a fabricated nanocolumns compliant layer with an HVPE growth process is provided. The method uses a combination of dry and wet etching to create nanocolumns consisting of layers of non-polar III nitride material and other insulating materials or materials used to grow the non-polar III-V nitride materials.Type: GrantFiled: September 26, 2007Date of Patent: February 18, 2014Inventor: Wang Nang Wang
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Patent number: 8652948Abstract: During the growth of a nitride semiconductor crystal on a nonpolar face nitride substrate, such as an m-face, the gas that constitutes the main flow in the process of heating up to a relatively high temperature range, before growth of the nitride semiconductor layer, (the atmosphere to which the main nitride face of the substrate is exposed) and the gas that constitutes the main flow until growth of first and second nitride semiconductor layers is completed (the atmosphere to which the main nitride face of the substrate is exposed) are primarily those that will not have an etching effect on the nitride, while no Si source is supplied at the beginning of growth of the nitride semiconductor layer. Therefore, nitrogen atoms are not desorbed from near the nitride surface of the epitaxial substrate, thus suppressing the introduction of defects into the epitaxial film. This also makes epitaxial growth possible with a surface morphology of excellent flatness.Type: GrantFiled: November 20, 2008Date of Patent: February 18, 2014Assignee: Mitsubishi Chemical CorporationInventors: Hideyoshi Horie, Kaori Kurihara
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Patent number: 8652949Abstract: A method of manufacturing a semiconductor wafer, which includes: a semiconductor substrate made of silicon and having both a central area and an outer periphery area; and a compound semiconductor layer made of a nitride-based semiconductor and formed on the semiconductor substrate, the method comprising: forming a growth inhibition layer to inhibit the compound semiconductor layer from growing on a tapered part provided in the outer periphery area of the semiconductor substrate; and growing the compound semiconductor layer on at least the central area of the semiconductor substrate, after the growth inhibition layer has been formed.Type: GrantFiled: August 5, 2011Date of Patent: February 18, 2014Assignee: Sanken Electric Co., Ltd.Inventor: Ken Sato
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Patent number: 8652950Abstract: A carbon-rich carbon boron nitride dielectric film having a dielectric constant of equal to, or less than 3.6 is provided that can be used as a component in various electronic devices. The carbon-rich carbon boron nitride dielectric film has a formula of CxByNz wherein x is 35 atomic percent or greater, y is from 6 atomic percent to 32 atomic percent and z is from 8 atomic percent to 33 atomic percent.Type: GrantFiled: February 25, 2013Date of Patent: February 18, 2014Assignee: International Business Machines CorporationInventors: Son Van Nguyen, Alfred Grill, Thomas J. Haigh, Jr., Sanjay Mehta
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Patent number: 8652951Abstract: Methods and apparatus for forming a germanium containing film on a patterned substrate are described. The patterned substrate is a silicon, or silicon containing material, and may have a mask material formed on a surface thereof. The germanium containing material is formed selectively on exposed silicon in the recesses of the substrate, and an overburden of at least 50% is formed on the substrate. The germanium containing layer is thermally treated using pulsed laser radiation, which melts a portion of the overburden, but does not melt the germanium containing material in the recesses. The germanium containing material in the recesses is typically annealed, at least in part, by the thermal treatment. The overburden is then removed.Type: GrantFiled: February 13, 2013Date of Patent: February 18, 2014Assignee: Applied Materials, Inc.Inventors: Yi-Chiau Huang, Jiping Li, Miao Jin, Bingxi Sun Wood, Errol Antonio C. Sanchez, Yihwan Kim
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Patent number: 8652952Abstract: Methods and apparatus provide for: a first source of plasma, wherein the plasma includes a first species of ions; a second source of plasma, wherein the plasma includes a second species of ions; selection of the plasma from the first and second sources; and acceleration the first species of ions or the second species of ions toward a semiconductor wafer.Type: GrantFiled: May 15, 2012Date of Patent: February 18, 2014Assignee: Corning IncorporatedInventor: Sarko Cherekdjian
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Patent number: 8652953Abstract: In a plasma doping device according to the invention, a vacuum chamber is evacuated with a turbo-molecular pump as an exhaust device via a exhaust port while a predetermined gas is being introduced from a gas supply device in order to maintain the inside of the vacuum chamber to a predetermined pressure with a pressure regulating valve. A high-frequency power of 13.56 MHz is supplied by a high-frequency power source to a coil provided in the vicinity of a dielectric window opposed to a sample electrode to generate inductive-coupling plasma in the vacuum chamber. A high-frequency power source for supplying a high-frequency power to the sample electrode is provided. Uniformity of processing is enhanced by driving a gate shutter and covering a through gate.Type: GrantFiled: July 27, 2012Date of Patent: February 18, 2014Assignee: Panasonic CorporationInventors: Tomohiro Okumura, Yuichiro Sasaki, Katsumi Okashita, Bunji Mizuno, Hiroyuki Ito, Ichiro Nakayama, Cheng-Guo Jin
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Patent number: 8652954Abstract: A method for manufacturing a silicon carbide semiconductor device includes the step of forming a mask pattern of a silicon oxide film by removing a portion of the silicon oxide film by means of etching employing a gas containing oxygen gas and at least one fluorine compound gas selected from a group consisting of CF4, C2F6, C3F8, and SF6.Type: GrantFiled: January 17, 2012Date of Patent: February 18, 2014Assignee: Sumitomo Electric Industries, Ltd.Inventors: Naoki Ooi, Hiromu Shiomi
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Patent number: 8652955Abstract: Provided is a manufacturing method of semiconductor integrated circuit, which is effective when applied to a processing technique for a gate electrode or the like. In the patterning of a gate stack film having a high-k gate insulating film and a metal electrode film in a memory region, etching for a cut region between adjacent gate electrodes is performed first using a first resist film and, after the first resist film that is no longer needed is removed, etching for a line and space pattern is performed using a second resist film.Type: GrantFiled: February 14, 2012Date of Patent: February 18, 2014Assignee: Renesas Electronics CorporationInventor: Masaaki Shinohara