Abstract: A field effect transistor (FET) includes source and drain electrodes, a channel layer, a barrier layer over the channel layer, a passivation layer covering the barrier layer for passivating the barrier layer, a gate electrode extending through the barrier layer and the passivation layer, and a gate dielectric surrounding a portion of the gate electrode that extends through the barrier layer and the passivation layer, wherein the passivation layer is a first material and the gate dielectric is a second material, and the first material is different than the second material.

Abstract: According to one embodiment, a fabrication method of a semiconductor device comprising forming a dummy gate with a gate length direction set to a [111] direction perpendicular to a [110] direction on a surface of a supporting substrate having Si1-xGex (0?x<0.5) with a crystal orientation perpendicular to the surface set to the [110] direction on the surface, forming source/drain regions and forming insulating films on side portions of the dummy gate. Next, the dummy gate is etched with using the insulating films as a mask, and a surface portion of the substrate between the source/drain regions is further etched. Next, a channel region formed of a III-V group semiconductor or Ge is grown between the source/drain regions by using the edge portions of the source/drain regions as seeds. Then, a gate electrode is formed above the channel region via a gate insulating film.

Abstract: A III-nitride semiconductor electronic device comprises a semiconductor laminate provided on a primary surface of a substrate, a first electrode in contact with the semiconductor laminate, and a second electrode. The semiconductor laminate includes a channel layer and a barrier layer making a junction with the channel layer. The channel layer comprises first III-nitride semiconductor containing aluminum as a Group III constituent element, and the barrier layer comprises second III-nitride semiconductor containing aluminum as a Group III constituent element. The semiconductor laminate including first, second and third regions arranged along the primary surface, and the third region is located between the first region and the second region. The barrier layer includes first to third portions included in the first to third regions, respectively.

Abstract: An improved structure of the high electron mobility transistor (HEMT) and a fabrication method thereof are disclosed. The improved HEMT structure comprises a substrate, a channel layer, a spacing layer, a carrier supply layer, a Schottky layer, a first etch stop layer, a first n type doped layer formed by AlxGa1-xAs, and a second n type doped layer. The fabrication method comprises steps of: etching a gate, a drain, and a source recess by using a multiple selective etching process. Below the gate, the drain, and the source recess is the Schottky layer. A gate electrode is deposited in the gate recess to form Schottky contact. A drain electrode and a source electrode are deposited to form ohmic contacts in the drain recess and the source recess respectively, and on the second n type doped layer surrounding the drain recess and the source recess respectively.

Abstract: A semiconductor device includes: a substrate comprised of gallium nitride; an active layer provided on the substrate; a first buffer layer that is provided between the substrate and the active layer and is comprised of indium aluminum nitride (InxAl1?xN, 0.15?x?0.2); and a spacer layer that is provided between the first buffer layer and the active layer and is comprised of aluminum nitride having a thickness of 1 nm or more to 10 nm or less.

Abstract: A millimeter-wave transistor device includes a plurality of sub-cells arranged in matrix array, each of the sub-cells having a longitudinal gate finger elongating along a reference y-axis, a source doping region disposed at one side of the longitudinal gate finger and a drain doping region at the other side of the longitudinal gate finger opposite to the source doping region; and at least three parallel connecting bars extending along a reference x-axis, electrically connecting with respective distal ends of the longitudinal gate finger of each of the sub-cells.

Abstract: Various aspects of the technology includes a quad semiconductor power and/or switching FET comprising a pair of control/sync FET devices. Current may be distributed in parallel along source and drain fingers. Gate fingers and pads may be arranged in a serpentine configuration for applying gate signals to both ends of gate fingers. A single continuous ohmic metal finger includes both source and drain regions and functions as a source-drain node. A set of electrodes for distributing the current may be arrayed along the width of the source and/or drain fingers and oriented to cross the fingers along the length of the source and drain fingers. Current may be conducted from the electrodes to the source and drain fingers through vias disposed along the surface of the fingers. Heat developed in the source, drain, and gate fingers may be conducted through the vias to the electrodes and out of the device.

Abstract: The present invention provides a solid-state imaging device in which high S/N is achieved. A solid-state imaging device includes a photodiode, a transfer transistor, a floating diffusion, a floating diffusion wiring, an amplifying transistor, a power line, and first output signal lines, in which the first output signal lines are formed one on each side of the floating diffusion wiring in a layer having the floating diffusion wiring formed on a semiconductor substrate, and the power line is formed above the floating diffusion wiring.

Abstract: A chemically sensitive sensor with a lightly doped region that affects an overlap capacitance between a gate and an electrode of the chemical sensitive sensor. The lightly doped region extends beneath and adjacent to a gate region of the chemical sensitive sensor. Modifying the gain of the chemically sensitive sensor is achieved by manipulating the lightly doped region under the electrodes.

Abstract: Manufacturing a semiconductor device with higher operating characteristics and achieve low power consumption of a semiconductor integrated circuit. A single crystal semiconductor layer is formed so that crystal plane directions of single crystal semiconductor layers which are used for channel regions of an n-channel and a p-channel TFT and which are formed over the same plane of the substrate are the most appropriate crystal plane directions for each TFT. In accordance with such a structure, mobility of carrier flowing through a channel is increased and the semiconductor device with higher operating characteristics can be provided. Low voltage driving can be performed, and low power consumption can be achieved.

Abstract: An electric-field blocking film is provided between a BL insulation film and BL insulation film of a transistor, and a blocking film includes those three layers. The electric-field blocking film blocks an electric field produced by a drain electrode, a source electrode, and an n+-Si film. Even if misalignment of the drain electrode, the source electrode, and the n+-Si film in each drive transistor varies to make a portion overlying an i-Si film larger, therefore, the electric field at this portion is blocked by the electric-field blocking film, thereby making a variation in characteristic smaller.

Abstract: A solid-state image capturing element includes, disposed in a surface portion from an upper part of the photodiode region to the electric charge detecting section: a second conductivity type first region; a second conductivity type second region; and a second conductivity type third region, one end of which is adjacent to the second conductivity type second region and the other end of which is adjacent to the electric charge detecting section, where each impurity concentration of the first, second and third regions is set in a manner to form an electric field being directed from the second conductivity type first region through the second conductivity type second region to the second conductivity type third region.

Abstract: A semiconductor device according to an embodiment includes: a semiconductor region on a semiconductor substrate, an upper face and side faces of the semiconductor region forming a saddle-like shape, convex portions being formed at both ends of a region including a saddle point in the upper face; a gate insulating film on the upper face of the semiconductor region except upper faces of the convex portions, and on side faces of the convex portions on a side of the region including the saddle point in the upper face; a gate electrode on the gate insulating film and including: a main body part located immediately above the region including the saddle point in the upper face; and leg portions leading to the main body portion and covering the side faces of the semiconductor region, a length of the leg portions being greater than a length of the main body portion.

Abstract: A method of forming (and an apparatus for forming) a metal-doped aluminum oxide layer on a substrate, particularly a semiconductor substrate or substrate assembly, using a vapor deposition process.

Abstract: A flash memory and a method for fabricating the same are provided. The flash memory comprises: a semiconductor substrate; a storage medium layer formed on the semiconductor substrate and comprising from bottom to top: a tunneling oxide layer, a silicon nitride layer and a blocking oxide layer; a semiconductor layer formed on the storage medium layer and comprising a channel region and a source region and a drain region located on both sides of the channel region respectively; and a gate stack formed on the channel region and comprising a gate dielectric and a gate formed on the gate dielectric.

Abstract: A method for fabricating a semiconductor device includes forming buried bit lines separated from each other by a trench in a substrate, forming a plurality of first pillar holes that expose a top surface of the substrate, forming first active pillars buried in the first pillar holes, forming a gate conductive layer over entire surface of a resultant structure including the first active pillars, forming a gate electrode by etching the gate conducting layer to cover the first active pillars, forming a plurality of second pillar holes that expose the first active pillars by partially etching the gate electrode, and forming second active pillars buried in the second pillar holes and connected to the first active pillars.

Abstract: A method of forming a SONOS gate structure. The method includes forming a gate pattern with sidewalls on a substrate, wherein the gate pattern includes a gate dielectric layer patterned on the substrate and a gate electrode patterned on the gate dielectric layer, forming a first oxide layer on the gate pattern and the substrate; etching back the first oxide layer to expose the substrate and the top of the gate electrode, leaving oxide spacers along the sidewalls of the gate pattern respectively; forming a second oxide layer on the substrate and the oxide spacers; and forming trapping dielectric spacers on the second oxide layer adjacent to the sidewalls of the gate pattern respectively.

Abstract: A nonvolatile semiconductor memory device includes: a stacked body in which insulating films and electrode films are alternately stacked; selection gate electrodes provided on the stacked body; bit lines provided on the selection gate electrodes; semiconductor pillars; connective members separated from one another; and a charge storage layer provided between the electrode film and the semiconductor pillar. One of the connective members is connected between a lower part of one of the semiconductor pillars and a lower part of another of the semiconductor pillars. The one of the semiconductor pillars passes through one of the selection gate electrodes and is connected to one of the bit lines, and the another of the semiconductor pillars passes through another of the selection gate electrodes and is connected to another of the bit lines.

Abstract: A semiconductor device having a string gate structure and a method of manufacturing the same suppress leakage current. The semiconductor device includes a selection gate and a memory gate. The channel region of the selection gate has a higher impurity concentration than that of the memory gate. Impurities may be implanted at different angles to form the channel regions having different impurity concentrations.

Abstract: According to one embodiment, a semiconductor storage device includes a charge storage layer, a control gate. The charge storage layer is formed above a semiconductor substrate with first insulating film disposed therebetween. The control gate is formed above the charge storage layer with second insulating film disposed therebetween. The control gate includes a nickel silicide region. The side surface expands outwardly in at least a partial region thereof, and height of the control gate from a portion at which the side surface thereof starts to expand outwardly to a top of the control gate is greater than maximum width of the control gate in a region above the portion at which the side surface starts to expand outwardly.

Abstract: Semiconductor devices and a methods of fabricating the semiconductor devices are provided. The semiconductor devices may include a pattern on a substrate. The semiconductor devices may also include a capping dielectric layer on the pattern. The semiconductor devices may further include a first nitride layer on the capping dielectric layer. Moreover, the semiconductor devices may include a second nitride layer on the first nitride layer. A concentration of nitrogen in the first nitride layer may be greater than that in the second nitride layer.

Abstract: Memory devices having an increased effective channel length and/or improved TPD characteristics, and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line dielectrics between the memory cells. The memory cell contains a charge trapping dielectric stack, a poly gate, a pair of pocket implant regions, and a pair of bit lines. The bit line can be formed by an implant process at a higher energy level and/or a higher concentration of dopants without suffering device short channel roll off issues because spacers at bit line sidewalls constrain the implant in narrower implant regions.

Abstract: A nonvolatile semiconductor memory device, includes: a stacked structural unit including a plurality of insulating films alternately stacked with a plurality of electrode films in a first direction; a selection gate electrode stacked on the stacked structural unit in the first direction; an insulating layer stacked on the selection gate electrode in the first direction; a first semiconductor pillar piercing the stacked structural unit, the selection gate electrode, and the insulating layer in the first direction, a first cross section of the first semiconductor pillar having an annular configuration, the first cross section being cut in a plane orthogonal to the first direction; a first core unit buried in an inner side of the first semiconductor pillar, the first core unit being recessed from an upper face of the insulating layer; and a first conducting layer of the first semiconductor pillar provided on the first core unit to contact the first core unit.

Abstract: In one embodiment, a semiconductor device includes a main vertical field-effect transistor (FET) and a sensing FET. The main vertical FET and the sense FET are both formed on a pillar of semiconductor material. Both share an extended drain region formed in the pillar above the substrate, and first and second gate members formed in a dielectric on opposite sides of the pillar. The source regions of the main vertical FET and the sensing FET are separated and electrically isolated in a first lateral direction. In operation, the sensing FET samples a small portion of a current that flows in the main vertical FET. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure.

Abstract: A dual vertical channel transistor includes a tuning fork-shaped substrate body; a buried bit line embedded at a bottom of a recess between two prong portions of the tuning fork-shaped substrate body; an out-diffused drain region adjacent to the buried bit line in the tuning fork-shaped substrate body; a source region situated at a top portion of each of the two prong portions of the tuning fork-shaped substrate body; an epitaxial portion connecting the two prong portions of the tuning fork-shaped substrate body between the out-diffused drain region and the source region; a front gate situated on a first side surface of the tuning fork-shaped substrate body; and a back gate situated on a second side surface opposite to the first side surface of the tuning fork-shaped substrate body.

Abstract: A nonvolatile memory device having a vertical structure and a method of manufacturing the same, the nonvolatile memory device including a channel region that vertically extends from a substrate; gate electrodes on the substrate, the gate electrodes being disposed along an outer side wall of the channel region and spaced apart from one another; and a channel pad that extends from one side of the channel region to an outside of the channel region, the channel pad covering a top surface of the channel region.

Abstract: A superjunction device is disclosed, wherein P-type regions in an active region are not in contact with the N+ substrate, and the distance between the surface of the N+ substrate and the bottom of the P-type regions in the active region is greater than the thickness of a transition region in the N-type epitaxial layer. Methods for manufacturing the superjunction device are also disclosed. The present invention is capable of improving the uniformity of reverse breakdown voltage and overshoot current handling capability in a superjunction device.

Abstract: This invention discloses a trench MOSFET comprising a top side drain region in a wide trench in a termination area besides a BV sustaining area, wherein said top side drain comprises a top drain metal connected to an epitaxial layer and a substrate through a plurality of trenched drain contacts, wherein the wide trench is formed simultaneously when a plurality of gate trenches are formed in an active area, and the trenched drain contacts are formed simultaneously when a trenched source-body contact is formed in the active area.

Abstract: A semiconductor device includes: a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type on the first semiconductor layer; trenches in the first semiconductor layer; a semiconductor protruding part on the first semiconductor layer; a third semiconductor layer on the semiconductor protruding part; a fourth semiconductor layer on the third semiconductor layer; a gate insulating layer disposed along the trench; a first interlayer insulating layer disposed along the trench; a first conductive layer facing to the fourth semiconductor layer; a second conductive layer on the first interlayer insulating layer; a second interlayer insulating layer covering the second conductive layer; a third conductive layer on the third semiconductor layer and fourth semiconductor layer; a contacting part connecting the third conductive layer and third semiconductor layer; and a fourth conductive layer formed on the second semiconductor layer.

Abstract: An integrated circuit includes a plurality of trench MOSFET and a plurality of trench Schottky rectifier. The integrated circuit further comprises: tilt-angle implanted body dopant regions surrounding a lower portion of all trenched gates sidewalls for reducing Qgd; a source dopant region disposed below trench bottoms of all trenched gates for functioning as a current path for preventing a resistance increased caused by the tilt-angle implanted body dopant regions.

Abstract: An embodiment of a vertical-conduction integrated electronic device formed in a body of semiconductor material which includes: a substrate made of a first semiconductor material and with a first type of conductivity, the first semiconductor material having a first bandgap; an epitaxial region made of the first semiconductor material and with the first type of conductivity, which overlies the substrate and defines a first surface; and a first epitaxial layer made of a second semiconductor material, which overlies the first surface and is in direct contact with the epitaxial region, the second semiconductor material having a second bandgap narrower than the first bandgap. The body moreover includes a deep region of a second type of conductivity, extending underneath the first surface and within the epitaxial region.

Abstract: A semiconductor component arrangement and method for producing thereof is disclosed. One embodiment provides at least one power semiconductor component integrated in a semiconductor body and at least one logic component integrated in the semiconductor body. The logic component includes a trench extending into the semiconductor body proceeding from a first side, at least one gate electrode arranged in the trench and insulated from the semiconductor body by a gate dielectric, and at least one source zone and at least one drain zone of a first conduction type, which are formed in the semiconductor body in a manner adjacent to the gate dielectric and in a manner spaced apart from one another in a peripheral direction of the trench and between which at least one body zone of a second conduction type is arranged.

Abstract: A method of forming an isolation structure, comprising: (a) providing a base having a recess; (b) forming a stop layer on the base and in the recess; (c) forming a dielectric material on the stop layer so as to allow the rest of the recess to be filled with the dielectric material; (d) removing the dielectric material over the base by performing a chemical mechanical polishing (CMP) process until a part of the stop layer is exposed so as to form a dielectric layer in the recess; and (e) removing a part of the stop layer, wherein the another part of the stop layer and the dielectric layer filled in the recess constitute the isolation structure.

Abstract: A semiconductor device includes a semiconductor layer provided with a gate trench, a first conductivity type source region exposed on a surface side of the semiconductor layer, a second conductivity type channel region formed on a side of the source region closer to aback surface of the semiconductor layer to be in contact with the source region, a first conductivity type drain region formed on a side of the channel region to be in contact with the channel region, a gate insulating film formed on an inner surface of the gate trench, and agate electrode embedded inside the gate insulating film in the gate trench, while the channel region includes a channel portion formed along the side surface of the gate trench and a projection projecting from an end portion of the channel portion closer to the back surface of the semiconductor layer toward the back surface.

Abstract: The present invention discloses a double diffused metal oxide semiconductor (DMOS) device and a manufacturing method thereof. The DMOS device includes: an isolation structure for defining device regions; a gate with a ring-shaped structure; a drain located outside the ring; and a lightly doped drain, a source, and a body electrode located inside the ring. To increase the sub-threshold voltage at the corners of the gate, the corners are located completely on the isolation structure, or the lightly doped drain is apart from the corners by a predetermined distance.

Abstract: The present invention relates to a semiconductor device including a circuit composed of thin film transistors having a novel GOLD (Gate-Overlapped LDD (Lightly Doped Drain)) structure. The thin film transistor comprises a first gate electrode and a second electrode being in contact with the first gate electrode and a gate insulating film. Further, the LDD is formed by using the first gate electrode as a mask, and source and drain regions are formed by using the second gate electrode as the mask. Then, the LDD overlapping with the second gate electrode is formed. This structure provides the thin film transistor with high reliability.

Abstract: An integrated circuit includes an SOI substrate with a unitary N+ layer below the BOX, a P region in the N+ layer, an eDRAM with an N+ plate, and logic/SRAM devices above the P region. The P region functions as a back gate of the logic/SRAM devices. An optional intrinsic (undoped) layer can be formed between the P back gate layer and the N+ layer to reduce the junction field and lower the junction leakage between the P back gate and the N+ layer. In another embodiment an N or N+ back gate can be formed in the P region. The N+ back gate functions as a second back gate of the logic/SRAM devices. The N+ plate of the SOI eDRAM, the P back gate, and the N+ back gate can be electrically biased at the same or different voltage potentials. Methods to fabricate the integrated circuits are also disclosed.

Abstract: Solutions for optimizing a bulk bias across a substrate of an ETSOI device are disclosed. In one embodiment, an apparatus for optimizing a bulk bias across a substrate of an ETSOI device is disclosed, including: a sensing circuit for sensing at least one predetermined circuit parameter; a charging circuit for applying a bias voltage to the substrate of the ETSOI device; and a processing circuit connected to the sensing circuit and the charging circuit, the processing circuit configured to receive an output of the sensing circuit, and adjust the bias voltage applied to substrate of the ETSOI device in response to determining whether the bias voltage deviates from a target amount.

Abstract: An electrical switch using a gated resistor structure includes an isolation layer, a doped silicon layer arranged on the isolation layer and having a recessed portion with reduced thickness, the doped silicon layer having a predetermined doping type and a predetermined doping profile; a gate layer arranged corresponding to the recessed portion. The recessed portion in the doped silicon layer has such thickness that a channel defined under the gate can be fully depleted to form a high resistivity region. The recessed channel gated resistor structure can be advantageously used to achieve high interconnect density with low thermal budget for 3D integration.

Abstract: A CMOS nanowire FinFET device structure and method of manufacturing the same are provided. The CMOS nanowire FinFET device structure includes a first plurality of fins and a second plurality of fins. The first and the second plurality of fins are formed in a semiconductor-on-insulator (SOI) layer over a buried insulator (BOX) layer. The first plurality of fins is formed in the first region and the second plurality of fins is formed in the second region. The CMOS nanowire FinFET device structure further includes a first plurality of nanowires formed over a top surface of each of the first plurality of fins and containing a first epitaxial layer. The first plurality of nanowires has a pair of facet surfaces. The pair of facet surfaces has (111) crystal orientation.

Abstract: A semiconductor device includes a pillar formed on a substrate of the same conductivity type. The pillar has a vertical thickness that extends from a top surface down to the substrate. The pillar extends in first and second lateral directions in a loop shape. First and second dielectric regions are disposed on opposite lateral sides of the pillar, respectively. First and second conductive field plates are respectively disposed in the first and second dielectric regions. A metal layer is disposed on the top surface of the pillar, the metal layer forming a Schottky diode with respect to the pillar. When the substrate is raised to a high-voltage potential with respect to both the metal layer and the first and second field plates, the first and second field plates functioning capacitively to deplete the pillar of charge, thereby supporting the high-voltage potential along the vertical thickness of the pillar.

Abstract: This invention provides a current control semiconductor element in which dependence of a sense ratio on a temperature distribution is eliminated and the accuracy of current detection using a sense MOSFET can be improved, and to provide a control device using the current control semiconductor element. The current control semiconductor element 1 includes a main MOSFET 7 that drives a current and a sense MOSFET 8 that is connected to the main MOSFET in parallel and detects a current shunted from a current of the main MOSFET. The main MOSFET is formed using a multi-finger MOSFET that has a plurality of channels and is arranged in a row. When a distance between the center of the multi-finger MOSFET 7 and a channel located farthest from the center of the multi-finger MOSFET 7 is indicated by L, a channel that is located closest to a position distant by a distance of (L/(?3)) from the center of the multi-finger MOSFET is used as a channel for the sense MOSFET 8.

Abstract: A transistor is fabricated by removing a polysilicon gate over a doped region of a substrate and forming a mask layer over the substrate such that the doped region is exposed through a hole within the mask layer. An interfacial layer is deposited on top and side surfaces of the mask layer and on a top surface of the doped region. A layer adapted to reduce a threshold voltage of the transistor and/or reduce a thickness of an inversion layer of the transistor is deposited on the interfacial layer. The layer includes metal, such as aluminum or lanthanum, which diffuses into the interfacial layer, and also includes oxide, such as hafnium oxide. A conductive plug, such as a metal plug, is formed within the hole of the mask layer. The interfacial layer, the layer on the interfacial layer, and the conductive plug are a replacement gate of the transistor.

Abstract: A semiconductor device includes a substrate including a memory cell region and a peripheral region and a field pattern including an insulating region disposed on a nitride liner in a trench in the substrate adjacent an active region. The field pattern and the active region extend in parallel through the cell and peripheral regions. The device also includes a transistor in the peripheral region including a source/drain region in the active region. The device further includes an insertion pattern including an elongate conductive region disposed in the substrate and extending along a boundary between the field pattern and the active region in the peripheral region. Fabrication methods are also described.

Abstract: Multiple transistor types are formed in a common epitaxial layer by differential out-diffusion from a doped underlayer. Differential out-diffusion affects the thickness of a FET channel, the doping concentration in the FET channel, and distance between the gate dielectric layer and the doped underlayer. Differential out-diffusion may be achieved by differentially applying a dopant migration suppressor such as carbon; differentially doping the underlayer with two or more dopants having the same conductivity type but different diffusivities; and/or differentially applying thermal energy.

Abstract: The work function of a high-k gate electrode structure may be adjusted in a late manufacturing stage on the basis of a lanthanum species in an N-channel transistor, thereby obtaining the desired high work function in combination with a typical conductive barrier material, such as titanium nitride. For this purpose, in some illustrative embodiments, the lanthanum species may be formed directly on the previously provided metal-containing electrode material, while an efficient barrier material may be provided in the P-channel transistor, thereby avoiding undue interaction of the lanthanum species in the P-channel transistor.

Abstract: It is intended to provide a semiconductor device capable to improve a controllability of dv/dt by a gate drive circuit during a turn-on switching period, while maintaining a low loss and a high breakdown voltage. Trench gates are disposed so as to have narrow distance regions and wide distance regions, wherein each of the narrow distance regions is provided with a channel region, and each of the wide distance regions is provided with trenches, each trench having an electrode electrically connected to the emitter electrode. In this manner, even if a floating-p layer is removed, it is possible to reduce a feedback capacity and maintain a breakdown voltage.

Abstract: An integrated circuit, in which a minimum gate length of low-noise NMOS transistors is less than twice a minimum gate length of logic NMOS transistors, is formed by: forming gates of the low-noise NMOS transistors concurrently with gates of the logic NMOS transistors, forming a low-noise NMDD implant mask which exposes the low-noise NMOS transistors and covers the logic NMOS transistors and logic PMOS transistors, ion implanting n-type NMDD dopants and fluorine into the low-noise NMOS transistors and limiting p-type halo dopants to less than 20 percent of a corresponding logic NMOS halo dose, removing the low-noise NMDD implant mask, forming a logic NMDD implant mask which exposes the logic NMOS transistors and covers the low-noise NMOS transistors and logic PMOS transistors, ion implanting n-type NMDD dopants and p-type halo dopants, but not implanting fluorine, into the logic NMOS transistors, and removing the logic NMDD implant mask.

Abstract: An integrated circuit structure includes a substrate and a fin field-effect transistor (FinFET). The FinFET includes a fin over the substrate and having a first fin portion and a second fin portion. A gate stack is formed on a top surface and sidewalls of the first fin portion. An epitaxial semiconductor layer has a first portion formed directly over the second fin portion, and a second portion formed on sidewalls of the second fin portion. A silicide layer is formed on the epitaxial semiconductor layer. A peripheral ratio of a total length of an effective silicide peripheral of the FinFET to a total length of a fin peripheral of the FinFET is greater than 1.

Abstract: An integrated circuit structure includes an integrated circuit structure includes a substrate, insulation regions over the substrate, and a fin field-effect transistor (FinFET). The FinFET includes a plurality of fins over the substrate, wherein each of the plurality of fins comprises a first fin portion and a second fin portion, a gate stack on a top surface and sidewalls of the first fin portion of each of the plurality of fins, an epitaxial semiconductor layer comprising a portion directly over the second fin portion of each of the plurality of fins, and sidewall portions directly over the insulation regions, and a silicide layer on, and having an interface with, the epitaxial layer, wherein a peripheral ratio of a total length of an effective silicide peripheral of the FinFET to a total length of peripherals of the plurality of fins is greater than 1.