Abstract: An optoelectronic component with short circuit protection is provided, comprising a first electrode layer (1) with a plurality of segments (11, 12), which are arranged separately from one another, a functional layer (2) on the first electrode layer (1), which emits electromagnetic radiation when in operation, a second electrode layer (3) on the functional layer (2), a power supply (4) and a plurality of electrical connections (51, 52). In each case at least one of the plurality of electrical connections (51, 52) is arranged between the first power supply (4) and at least one of the plurality of segments (11, 12) of the first electrode layer (1) for electrical contacting of the first electrode layer (1). The power supply (4) has a first cross-section and each of the plurality of electrical connections (51, 52) has a second cross-section. The second cross-section is smaller than the first cross-section, and the electrical connections (51, 52) take the form of fuses.

Abstract: In certain embodiments, a field effect transistor (FET) can include a substrate, a source electrode, a drain electrode, a ferroelectric material layer, a first gate electrode, and a second gate electrode to maintain an optimal polarization state of the ferroelectric material layer. In other embodiments, a FET can include a film, first and second gates on the film, a ferroelectric material layer covering the film and gates, an insulating layer substantially covering the ferroelectric material layer, a source and a drain on the insulating layer, and a pentacene layer.

Abstract: An organic light emitting diode (OLED) display may be constructed with a substrate; a first electrode formed on the substrate; a barrier rib formed on the substrate and having an opening exposing the first electrode; an organic emission layer formed on the first electrode; and a second electrode formed on the organic emission layer. The barrier rib includes an isolating groove formed between organic emission layers of neighboring pixels. Accordingly, in the organic light emitting diode (OLED) display, the isolating groove is formed at the barrier rib such that ink is prevented from crossing over the barrier rib and flowing into a neighboring pixel without a hydrophobic surface treatment of the barrier rib.

Abstract: The present disclosure is directed to a thin film transistor composition. The thin film transistor composition has a semiconductor material and a substrate. The substrate is composed of a polyimide and a sub-micron filler. The polyimide is derived from at least one aromatic dianhydride component selected from rigid rod dianhydride, non-rigid rod dianhydride and combinations thereof, and at least one aromatic diamine component selected from rigid rod diamine, non-rigid rod diamine and combinations thereof. The mole ratio of dianhydride to diamine is 48-52:52-48 and the ratio of X:Y is 20-80:80-20 where X is the mole percent of rigid rod dianhydride and rigid rod diamine, and Y is the mole percent of non-rigid rod dianhydride and non-rigid rod diamine. The sub-micron filler is less than 550 nanometers in at least one dimension; has an aspect ratio greater than 3:1; is less than the thickness of the film in all dimensions.

Abstract: A semiconductor device includes an oxide semiconductor layer, a source electrode and a drain electrode in contact with the oxide semiconductor layer, a gate electrode overlapping with the oxide semiconductor layer, and a gate insulating layer between the oxide semiconductor layer and the gate electrode, in which the source electrode or the drain electrode comprises a first conductive layer and a second conductive layer having a region which extends beyond an end portion of the first conductive layer in a channel length direction and which overlaps with part of the gate electrode, in which a sidewall insulating layer is provided over the extended region of the second conductive layer, and in which the sidewall insulating layer comprises a stack of a plurality of different material layers.

Abstract: An object is to manufacture a semiconductor device with high reliability by providing the semiconductor device including an oxide semiconductor with stable electric characteristics. In a transistor including an oxide semiconductor layer, a gallium oxide film is used for a gate insulating layer and made in contact with an oxide semiconductor layer. Further, gallium oxide films are provided so as to sandwich the oxide semiconductor layer, whereby reliability is increased. Furthermore, the gate insulating layer may have a stacked structure of a gallium oxide film and a hafnium oxide film.

Abstract: Provided is a thin film transistor and thin film transistor panel array. The thin film transistor includes: a substrate; a gate electrode disposed on the substrate; a semiconductor layer disposed on the substrate and partially overlapping with the gate electrode; a source electrode and a drain electrode spaced apart from each other with respect to a channel region of the semiconductor layer; an insulating layer disposed between the gate electrode and the semiconductor layer; and a barrier layer disposed between the semiconductor layer and the source electrode and between the semiconductor layer and the drain electrode, in which the barrier layer comprises graphene. An ohmic contact is provided based on the type of material used for the semiconductor layer.

Abstract: A transistor includes a substrate; a gate including a first electrically conductive layer stack on the substrate; and a first inorganic thin film dielectric layer on the substrate with the first inorganic thin film dielectric layer having a first pattern. A second inorganic thin film dielectric layer, having a second pattern, is in contact with the first inorganic thin film dielectric layer. The first inorganic thin film dielectric layer and the second thin film dielectric layer have the same material composition. A third inorganic thin film dielectric layer has a third pattern. A semiconductor layer is in contact with and has the same pattern as the third inorganic thin film dielectric material layer. A source/drain includes a second electrically conductive layer stack.

Abstract: In a TFT that adopts an oxide semiconductor as an active layer and has a resistance layer interposed between the active layer and one of a source and drain electrode, while Vth close to 0 V and a small off current are sustained, an on-current is increased. In a thin-film transistor including a gate electrode, a gate insulating film, a semiconductor layer, a source electrode, and a drain electrode, the semiconductor layer that links the source electrode and drain electrode is made of a metal oxide. The semiconductor layer includes three regions of first, second, and third regions. The first region is connected with the source electrode, the third region is connected with the drain electrode, and the second region is connected between the first region and third region. The resistivities of the three regions have the relationship of the first region>the second region>the third region.

Abstract: A semiconductor device has a floating gate structure in which charge storage layers are stacked on a SiO2 layer formed on a substrate made of n-type Si. The charge storage layer has quantum dots made of undoped Si and an oxide layer that covers the quantum dots. The charge storage layer has quantum dots made of n+-Si and an oxide layer that covers the quantum dots. Electrons originally existing in the quantum dots migrate between the quantum dots and the quantum dots via tunnel junction and are distributed in the quantum dots and/or the quantum dots according to the voltage applied to a gate electrode via pads. The distribution is detected in the form of a current (ISD).

Abstract: The electronic device includes a substrate, a first electrode formed over a surface of the substrate, a second electrode located on an opposite side of the first electrode from the substrate so as to face the first electrode, and a functional layer interposed between the first electrode and second electrode and formed by means of anodizing a first polycrystalline semiconductor layer in an electrolysis solution so as to contain a plurality of semiconductor nanocrystals. The electronic device further includes a second polycrystalline semiconductor layer interposed between the first electrode and the functional layer so as to be in close contact with the functional layer. The second polycrystalline semiconductor layer has an anodic oxidization rate in the electrolysis solution lower than that of the first polycrystalline semiconductor layer so as to function as a stop layer for exclusively anodizing the first polycrystalline semiconductor layer.

Abstract: An object is to provide a semiconductor device having a novel structure in which a transistor including an oxide semiconductor and a transistor including a semiconductor material other than an oxide semiconductor are stacked. The semiconductor device includes a first transistor, an insulating layer over the first transistor, and a second transistor over the insulating layer. In the semiconductor device, the first transistor includes a first channel formation region, the second transistor includes a second channel formation region, the first channel formation region includes a semiconductor material different from a semiconductor material of the second channel formation region, and the insulating layer includes a surface whose root-mean-square surface roughness is less than or equal to 1 nm.

Abstract: A liquid crystal display array substrate and a method for manufacturing the same are discussed. The liquid crystal display array substrate includes a gate line arranged on a substrate in one direction, a data line which crosses the gate line and defines a plurality of pixel areas, a thin film transistor formed at a crossing of the gate line and the data line, a pixel electrode connected to the thin film transistor, and a common electrode which is positioned opposite the pixel electrode and forms an electric field. The common electrode includes a shield line overlapping the data line, and the shield line includes at least two cutting portions having a width less than other portion of the shield line.

Abstract: There is provided an electric device which can prevent a deterioration in a frequency characteristic due to a large electric power external switch connected to an opposite electrode and can prevent a decrease in the number of gradations. The electric device includes a plurality of source signal lines, a plurality of gate signal lines, a plurality of power source supply lines, a plurality of power source control lines, and a plurality of pixels. Each of the plurality of pixels includes a switching TFT, an EL driving TFT, a power source controlling TFT, and an EL element, and the power source controlling TFT controls a potential difference between a cathode and an anode of the EL element.

Abstract: There is provided a thin-film transistor forming substrate in which at least one of a source electrode, a drain electrode, and a gate electrode, which are constituent elements of a thin film transistor, or a first electrode is included on a face of a substrate main body that is located on any one side in a thickness direction. An embedded wiring that is connected to one of the source electrode, the drain electrode, the gate electrode, and the first electrode is buried inside the substrate main body.

Abstract: A touch panel display and method for manufacturing the same are disclosed. The touch panel display includes a first substrate, a second substrate, a touch-sensing member, and a liquid crystal layer. The first substrate has a first surface and a second surface thereon. The second substrate has an element array and is disposed on the second surface of the first substrate. The touch-sensing member locates on the first surface of the first substrate. Furthermore, the touch-sensing member includes a conductive layer, a patterned electrode layer, and a protective layer. The patterned electrode layer is correspondingly located on the periphery of the first substrate. The protective layer covers the conductive layer, and the patterned electrode layer. The conductive layer locates between the protective layer and the first substrate. In addition, the liquid crystal layer is disposed between the first and the second substrate.

Abstract: A thin-film transistor according to the present disclosure includes: a substrate; a gate electrode above the substrate; a gate insulating layer on the gate electrode; a channel layer on the gate insulating layer which is located on the gate electrode; a source electrode above the channel layer; a drain electrode above the channel layer; and a barrier layer between the channel layer and the source electrode and between the channel layer and the drain electrode. Each of the source electrode and the drain electrode is made of a metal including copper, and the barrier layer contains nitrogen and molybdenum and has a density greater than 7.5 g/cm3 and less than 10.5 g/cm3.

Abstract: A display panel having a display area and a gate driving area includes a gate line and plural pixel units in the display area, and a gate driver circuit in the gate driving area. The gate line connects to the pixel units. The gate driver circuit connects to the gate line. The gate driver includes a driving transistor and a driving storage capacitor stacked to each other to form a stack structure, which includes a first electrode, a first dielectric layer, a second electrode, a second dielectric layer, a first semiconductor layer, a drain electrode, and a source electrode, which is connected to the gate line. The driving storage capacitor is formed by the first electrode, the first dielectric layer, and the second electrode. The driving transistor is formed by the second electrode, the second dielectric layer, the first semiconductor layer, the source electrode, and the drain electrode.

Abstract: Disclosed is a method for manufacturing a thin film transistor in which a semiconductor film in a channel portion is provided between a source electrode and a drain electrode, wherein a partition layer (a bank) can be appropriately formed. The method comprises the steps of: forming two underlying electrodes on an underlying layer; forming a partition layer on the surface of the underlying layer containing the two underlying electrodes so as to surround an area where the source electrode and the drain electrode are to be formed; forming the source electrode and the drain electrode by a plating method on the surfaces of the two underlying electrodes, which are surrounded by the partition layer; and applying semiconductor solution, in which a semiconductor material is dissolved or dispersed, to the area surrounded by the partition layer so that a semiconductor film is formed in the area.

Abstract: A thin film transistor including: an active layer formed on a substrate; a gate insulating layer pattern formed on a predetermined region of the active layer; a gate electrode formed on a predetermined region of the gate insulating layer pattern; an etching preventing layer pattern covering the gate insulating layer pattern and the gate electrode; and a source member and a drain member formed on the active layer and the etching preventing layer pattern.

Abstract: In a semiconductor device in which a glass substrate is attached to a surface of a semiconductor die with an adhesive layer being interposed therebetween, it is an object to fill a recess portion of an insulation film formed on a photodiode with the adhesive layer without bubbles therein. In a semiconductor die in which an optical semiconductor integrated circuit including a photodiode having a recess portion of an interlayer insulation film in the upper portion, an NPN bipolar transistor, and so on are formed, generally, a light shield film covers a portion except the recess portion region on the photodiode and except a dicing region. In the invention, an opening slit is further formed in the light shield film, extending from the recess portion to the outside of the recess portion, so as to attain the object.

Abstract: The present invention relates to a thin film transistor array panel and a manufacturing method thereof that prevent disconnection of wiring due to misalignment of a mask, and simplify a process and reduce cost by reducing the number of masks. The thin film transistor array panel according to the disclosure includes a source electrode enclosing an outer part of the first contact hole and formed on the second insulating layer; a drain electrode enclosing an outer part of the second contact hole and formed on the second insulating layer; a first connection electrode connecting the source region of the semiconductor layer and the source electrode through the first contact hole; and a second connection electrode connecting the drain region of the semiconductor layer and the drain electrode through the second contact hole.

Abstract: Disclosed is a thin film transistor wherein an ON current is increased and a leak current is reduced. The channel layer 60 of the TFT 10 is formed of a crystalline silicon, and the lower surface of one end of the channel layer 60 is electrically connected to the surface of an n+ silicon layer 40a, and the lower surface of the other end is electrically connected to the surface of an n+ silicon layer 40b. Furthermore, the side surface of said end of the channel layer 60 is electrically connected to a source electrode 50a, and the side surface of the other end is electrically connected to a drain electrode 50b. Thus, a barrier that makes electrons, which act as carriers, not easily transferred is formed on the boundary between the source electrode 50a and the channel layer 60. As a result, the ON current that flows when the TFT 10 is in the ON state can be increased, and the leak current that flows when the TFT is in the OFF state can be reduced.

Abstract: Disclosed herein is a display device, including: a substrate; a circuit part configured to include a drive element; a planarization insulating layer; an electrically-conductive layer including a plurality of first electrodes and an auxiliary interconnect; an aperture-defining insulating layer configured to insulate the plurality of first electrodes from each other and have an aperture through which part of the first electrode is exposed; a plurality of light emitting elements; and a separator configured to be formed by removing the planarization insulating layer at a position between a display area, in which the plurality of light emitting elements connected to the drive element are disposed, and a peripheral area which is surrounding the display area. A method of manufacturing a display device is also provided.

Abstract: A method of manufacturing a semiconductor device includes the steps of forming a silicon oxide film on a silicon carbide substrate, annealing the silicon carbide substrate and the silicon oxide film in gas containing hydrogen, and forming an aluminum oxynitride film on the silicon oxide film after the annealing of the silicon carbide substrate and the silicon oxide film.

Abstract: An electronic device includes a silicon carbide drift region having a first conductivity type, a Schottky contact on the drift region, and a plurality of junction barrier Schottky (JBS) regions at a surface of the drift region adjacent the Schottky contact. The JBS regions have a second conductivity type opposite the first conductivity type and have a first spacing between adjacent ones of the JBS regions. The device further includes a plurality of surge protection subregions having the second conductivity type. Each of the surge protection subregions has a second spacing between adjacent ones of the surge protection subregions that is less than the first spacing.

Abstract: A semiconductor device according to the present invention includes a contact region 201 of a second conductivity type which is provided in a body region 104. The contact region 201 includes a first region 201a in contact with a first ohmic electrode 122 and a second region 201b located at a position deeper than that of the first region 201a and in contact with the body region 104. The first region 201a and the second region 201b each have at least one peak of impurity concentration. The peak of impurity concentration in the first region 201a has a higher value than that of the peak of impurity concentration in the second region 201b.

Abstract: An object is to provide a novel manufacturing method of a semiconductor substrate containing silicon carbide, and another object is to provide a semiconductor device using silicon carbide. A semiconductor substrate is manufactured through the steps of: adding ions to a silicon carbide substrate to form an embrittlement region in the silicon carbide substrate; bonding the silicon carbide substrate to a base substrate with insulating layers interposed therebetween; heating the silicon carbide substrate and separating the silicon carbide substrate at the embrittlement region to form a silicon carbide layer over the base substrate with the insulating layers interposed between therebetween; and performing heat treatment on the silicon carbide layer at a temperature of 1000° C. to 1300° C. to reduce defects of the silicon carbide layer. A semiconductor device is manufactured using the semiconductor substrate formed as described above.

Abstract: The invention relates to a layer assembly for a light-emitting component, in particular a phosphorescent organic light-emitting diode, having a hole-injecting contact and an electron-injecting contact which are each connected to a light-emitting region, wherein, in the light-emitting region, one light-emitting layer is made up of a material (M1) and another light-emitting layer is made up of another material (M2), where the material (M1) is ambipolar and preferentially transports holes and the other material (M2) is ambipolar and preferentially transports electrons; a heterotransition is formed by the material (M1) and the other material (M2) in the light-emitting region; an interface between the material (M1) and the other material (M2) is of the staggered type II; the material (M1) and the other material (M2) each contain an appropriate addition of one or more triplet emitter dopants; and an energy barrier for transfer of holes from the material (M1) into the other material (M2) and an energy barrier for tr

Abstract: Disclosed herein is a rod type light emitting device and method for fabricating the same, wherein a plurality of rod structures is sequentially formed with a semiconductor layer doped with a first polarity dopant, an active layer, and a semiconductor layer doped with a second polarity dopant.

Abstract: In accordance with certain embodiments, an illumination system comprising a plurality of power strings features elements facilitating compensation for failure of one or more light-emitting elements connected along each power string.

Abstract: An optoelectronic semiconductor body includes a semiconductor layer sequence which has an active layer suitable for generating electromagnetic radiation, and a first and a second electrical connecting layer. The semiconductor body is provided for emitting electromagnetic radiation from a front side. The first and the second electrical connecting layer are arranged at a rear side opposite the front side and are electrically insulated from one another by means of a separating layer. The first electrical connecting layer, the second electrical connecting layer and the separating layer laterally overlap and a partial region of the second electrical connecting layer extends from the rear side through a breakthrough in the active layer in the direction of the front side. Furthermore, a method for producing such an optoelectronic semiconductor body is specified.

Abstract: A semiconductor device including a plurality of circuits that includes a transistor, where a semiconductor layer forming the transistor includes a first contact pad, a first part that is connected to the first contact pad and that extends in a direction intersecting a short direction of a pitch with which the circuits are arranged, a second part that extends from the first part in the short direction, and a second contact pad including the first part and the second part that are provided between the first contact pad and the second contact pad, where the second part overlaps an electrode layer across an insulating layer.

Abstract: The present disclosure provides a method of fabricating a light emitting diode (LED) package. The method includes bonding a plurality of separated light emitting diode (LED) dies to a substrate, wherein each of the plurality of separated LED dies includes an n-doped layer, a quantum well active layer, and a p-doped layer; depositing an isolation layer over the plurality of separated LED dies and the substrate; etching the isolation layer to form a plurality of via openings to expose portions of each LED die and portions of the substrate; forming electrical interconnects over the isolation layer and inside the plurality of via openings to electrically connect between one of the doped layers of each LED die and the substrate; and dicing the plurality of separated LED dies and the substrate into a plurality of LED packages.

Abstract: The deposition substrate of the present invention includes a light-transmitting substrate having a first region and a second region. In the first region, a first heat-insulating layer transmitting light is provided over the light-transmitting substrate, a light absorption layer is provided over the first heat-insulating layer, and a first organic compound-containing layer is provided over the light absorption layer. In the second region, a reflective layer is provided over the light-transmitting substrate, a second heat-insulating layer is provided over the reflective layer, and a second organic compound-containing layer is provided over the second heat-insulating layer. The edge of the second heat-insulating layer is placed inside the edge of the reflective layer, and there is a space between the first heat-insulating layer and the second heat-insulating layer.

Abstract: OLED device (1) comprising a substrate (4) with multiple light emitting OLED segments (5, 6, 7) on top of the substrate (4) each comprising an electroluminescent layer stack (6) of at least an organic light-emitting layer sandwiched between a substrate electrode (5) facing towards the substrate (4) and a counter electrode (7), which are connected in series and are separated from the adjacent OLED segment (5, 6, 7) by an interconnect region (3) located between the adjacent OLED segments comprising a first isolating layer (10) of an electrically non-conducting material between the substrate electrodes (5) of adjacent OLED segments to electrically isolate the adjacent substrate electrodes (5) from each other and a conductive layer (9) of an electrically conducting material to connect the counter electrode (7) of the OLED segment to the substrate electrode (5) of the adjacent OLED segment, wherein the electrically non-conducting material and/or the conducting material is suitable to redirect the light emitted by

Abstract: A semiconductor light emitting device that includes a first conductive type semiconductor layer, a first electrode, a insulating layer, and an electrode layer. The first electrode has at least one branch on the first conductive type semiconductor layer. The insulating layer is disposed on the first electrode. The electrode layer is disposed on the insulating layer.

Abstract: A light-emitting device includes a light-emitting stacked layer having an active layer, and a composite substrate located under the light-emitting stacked layer. The composite substrate includes a supportive substrate having a top surface and a bottom surface non-parallel to the active layer; a metal substrate located under the supportive substrate; and a reflective layer located between the supportive substrate and the metal substrate.

Abstract: Provided are a light emitting device and a light emitting device package. The light emitting device includes a first electrode, a light emitting structure including a first semiconductor layer, an active layer, and a second semiconductor layer on the first electrode, a second electrode on the light emitting structure, and a reflective member on at least lateral surface of the second electrode.

Abstract: A light-emitting device comprising a light-emitting layer and a light exit layer. In this case, the light exit layer has a multiplicity of mutually parallel first areas, arranged in an inclined fashion with respect to the light-emitting layer. The light exit layer furthermore has a multiplicity of mutually parallel second areas arranged in an inclined fashion with respect to the light-emitting layer and in an inclined fashion with respect to the first areas. The first areas are transparent and the second areas are reflective to light emitted by the light-emitting layer.

Abstract: Provided are a phosphor, a phosphor manufacturing method, and a white light emitting device. The phosphor is represented as a chemical formula of aMO-bAlN-cSi3N4, which uses light having a peak wavelength in a wavelength band of about 350 nm to about 480 nm as an excitation source to emit visible light having a peak wavelength in a wavelength band of about 480 nm to about 680 nm. (where M is one selected from alkaline earth metals (0.2?a/(a+b)?0.9, 0.05?b(b+c)?0.85, 0.4?c/(c+a)?0.9)).

Abstract: An LED device having plasmonically enhanced emission is provided. The device includes an inverted LED structure with a coating of metal nanoparticles on the surface chosen to match the plasmonic response to the peak emission from the active quantum well (QW) emission region of the LED. The active QW emission region is separated from the metal nanoparticles on the surface by a thin n-type contact layer disposed on a top side of the active QW emission. A p-type layer is disposed immediately beneath the active QW emission region and injects holes into the active QW emission region. The n-type contact layer is sufficiently thin to permit a coupling of the surface plasmons (SPs) from the metal nanoparticles and the excitons in the active QW emission region. The SP-exciton coupling provides an alternative decay route for the excitons and thus enhances the photon emission from the LED device.

Abstract: A light-emitting element, a light-emitting element unit and a light-emitting element package are provided, which are each reduced in reflection loss and intra-film light absorption by suppressing multiple light reflection in a transparent electrode layer and hence have higher luminance. The light-emitting element 1 includes a substrate 2, an n-type nitride semiconductor layer 3, a light-emitting layer 4, a p-type nitride semiconductor layer 5, a transparent electrode layer 6 and a reflective electrode layer 7, and the transparent electrode layer 6 has a thickness T satisfying the following expression (1): 3 ? ? 4 ? ? n + 0.30 × ( ? 4 ? ? n ) ? T ? 3 ? ? 4 ? ? n + 0.45 × ( ? 4 ? ? n ) ( 1 ) wherein ? is the light-emitting wavelength of the light-emitting element 4, and n is the refractive index of the transparent electrode layer 6.

Abstract: The light-emitting device includes a groove passing through a second semiconductor layer and a light-emitting layer to reach a first semiconductor layer; a first ohmic electrode in contact with the first semiconductor layer within the groove; a connection electrode passing through the first semiconductor layer from the surface thereof and electrically connected to the first ohmic electrode; an insulating layer for covering the second semiconductor layer on a surface thereof opposing the first semiconductor layer, the insulating layer having an opening; a second ohmic electrode in contact with the second semiconductor layer in the opening; a metal layer formed over the insulating layer, and connected to the second ohmic electrode; and a support bonded to the metal layer.

Abstract: An object is to provide a light-emitting element which uses a plurality of kinds of light-emitting dopants and has high emission efficiency. In one embodiment of the present invention, a light-emitting device, a light-emitting module, a light-emitting display device, an electronic device, and a lighting device each having reduced power consumption by using the above light-emitting element are provided. Attention is paid to Förster mechanism, which is one of mechanisms of intermolecular energy transfer. Efficient energy transfer by Förster mechanism is achieved by making an emission wavelength of a molecule which donates energy overlap with a local maximum peak on the longest wavelength side of a graph obtained by multiplying an absorption spectrum of a molecule which receives energy by a wavelength raised to the fourth power.

Abstract: A white LED assembly includes a blue LED die attached to a substrate. A first volume of a first luminescent material surrounds the blue LED die in a lateral dimension such that none of the first luminescent material is disposed directly over the blue LED die. The first luminescent material includes a relatively inefficient phosphor having a peak emission wavelength longer than 620 nm and includes substantially no phosphor having a peak emission wavelength shorter than 620 nm. A second volume of a second luminescent material is disposed over the first volume and the blue LED die. The second luminescent material includes a relatively efficient phosphor having a peak emission wavelength shorter than 620 nm and includes substantially no phosphor having a peak emission wavelength longer than 620 nm. Placement of the first and second luminescent materials in this way promotes removal of heat from the inefficient phosphor and reduces the likelihood of interabsorption.

Abstract: A vertical light-emitting diode with a short circuit protection function includes a heat dissipation substrate, a second electrode, a welding metal layer and a third electrode; a semiconductor light-emitting layer formed on the third electrode; a barrier for the semiconductor light-emitting layer with an isolation trench, so that the barrier for the semiconductor light-emitting layer surrounds the semiconductor light-emitting layer on a central region of the third electrode, with the isolation trench therebetween. The barrier for the semiconductor light-emitting layer has a structure the same as the semiconductor light-emitting layer, and the isolation trench exposes the third electrode. A fourth electrode is formed on the semiconductor light-emitting layer.

Abstract: A vertical semiconductor device includes a semiconductor body, and first and second contacts on opposite sides of the semiconductor body. A plurality of regions are formed in the semiconductor body including, in a direction from the first contact to the second contact, a first region of a first conductivity type, a second region of a second conductivity type; and a third region of the first conductivity type. The third region is electrically connected to the second contact. A semiconductor zone of the second conductivity type and increased doping density is arranged in the second region. The semiconductor zone separates a first part of the second region from a second part of the second region. The semiconductor zone has a maximum doping density exceeding about 1016 cm?3 and a thickness along the direction from the first contact to the second contact of less than about 3 ?m.

Abstract: A high holding voltage (HV) electrostatic discharge (ESD) protection circuit comprises a silicon controlled rectifier (SCR) device and compensation regions located within the length between the anode and cathode (LAC) of the SCR device which increase the holding voltage of the SCR device. The compensation regions may introduce negative feedback mechanisms into the SCR device which may influence the loop gain of the SCR and cause it to reach regenerative feedback at a higher holding voltage.

Abstract: In some embodiments, a metal insulator semiconductor heterostructure field effect transistor (MISHFET) is disclosed that has a source, a drain, an insulation layer, a gate dielectric, and a gate. The source and drain are on opposing sides of a channel region of a channel layer. The channel region is an upper portion of the channel layer. The channel layer comprises gallium nitride. The insulation layer is over the channel layer and has a first portion and a second portion. The first portion is nearer the drain than the source and has a first thickness. The second portion is nearer the source than drain and has the first thickness. The insulation layer has an opening through the insulation layer. The opening is between the first portion and the second portion.