Patents Issued in April 1, 2014
  • Patent number: 8686406
    Abstract: A pyrene-based compound, an organic light-emitting diode including the compound and an organic light-emitting apparatus including the compound are disclosed.
    Type: Grant
    Filed: June 29, 2012
    Date of Patent: April 1, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: Dong-Woo Shin, O-Hyun Kwon, Kyul Han, Seul-Ong Kim, Byoung-Ki Choi
  • Patent number: 8686407
    Abstract: A display apparatus includes a driving substrate and an organic light emitting diode device. The driving substrate includes a display area, a non-display area, a substrate and a transparent driving element. The transparent driving element is disposed in the non-display area to form a transparent region. The organic light emitting diode device is disposed over the driving substrate and located in the display area to form a non-transparent region.
    Type: Grant
    Filed: August 8, 2012
    Date of Patent: April 1, 2014
    Assignee: E Ink Holdings Inc.
    Inventors: Fang-An Shu, Yao-Chou Tsai, Wen-Chung Tang, Ted-Hong Shinn
  • Patent number: 8686408
    Abstract: A photoelectric conversion device is provided and includes: a first electrode, a second electrode, and a photoelectric conversion layer between the first and second electrodes, the photoelectric conversion layer containing a mixture of an organic photoelectric conversion dye, a fullerene or a fullerene derivative, and a fullerene polymer; various embodiments of the device, a photosensor, an imaging device, and production methods for these devices.
    Type: Grant
    Filed: February 24, 2011
    Date of Patent: April 1, 2014
    Assignee: FUJIFILM Corporation
    Inventors: Katsuyuki Yofu, Daigo Sawaki
  • Patent number: 8686409
    Abstract: A method of repairing a defective pixel in a display apparatus that includes forming an insulating layer to cover the plurality of second signal wires, cutting both sides of a region of the corresponding second signal wire of the defective pixel and the insulating layer to form both sides of a cut region, forming contact holes adjacent to the both sides of the cut region, respectively, such that an upper portion of the corresponding second signal wire is exposed, forming a repair metal layer on the insulating layer to contact the contact holes and the second signal wire, and forming a repair insulating layer to cover the repair metal layer.
    Type: Grant
    Filed: October 31, 2012
    Date of Patent: April 1, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: Yul-Kyu Lee, Sun Park, Kyu-Sik Cho
  • Patent number: 8686410
    Abstract: An electroluminescence generating device comprising a channel of organic semiconductor material, said channel being able to carry both types of charge carriers, said charge carriers being electrons and holes; an electron electrode, said electron electrode being in contact with said channel and positioned on top of a first side of said channel layer or within said channel layer, said electron electrode being able to inject electrons in said channel layer; a hole electrode, said hole electrode being spaced apart from said electron electrode, said hole channel and positioned on top of within said channel layer, said hole electrode being able to inject holes into said channel; a control electrode positioned on said first side or on a second side of said channel; whereby light emission of said electroluminescence generating device can be acquired by applying an electrical potential difference between said electron electrode and said hole electrode.
    Type: Grant
    Filed: June 26, 2013
    Date of Patent: April 1, 2014
    Inventor: Michele Muccini
  • Patent number: 8686411
    Abstract: Self-aligning fabrication methods for forming memory access devices comprising a doped chalcogenide material. The methods may be used for forming three-dimensionally stacked cross point memory arrays. The method includes forming an insulating material over a first conductive electrode, patterning the insulating material to form vias that expose portions of the first conductive electrode, forming a memory access device within the vias of the insulating material and forming a memory element over the memory access device, wherein data stored in the memory element is accessible via the memory access device. The memory access device is formed of a doped chalcogenide material and formed using a self-aligned fabrication method.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: April 1, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Neil Greeley, Bhaskar Srinivasan, Gurtej Sandhu, John Smythe
  • Patent number: 8686412
    Abstract: A microelectronic device includes a thin film transistor having an oxide semiconductor channel and an organic polymer passivation layer formed on the oxide semiconductor channel.
    Type: Grant
    Filed: July 31, 2007
    Date of Patent: April 1, 2014
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Gregory Herman, Benjamin Clark, Zhizhang Chen
  • Patent number: 8686413
    Abstract: It is an object to provide a semiconductor device having a new productive semiconductor material and a new structure. The semiconductor device includes a first conductive layer over a substrate, a first insulating layer which covers the first conductive layer, an oxide semiconductor layer over the first insulating layer that overlaps with part of the first conductive layer and has a crystal region in a surface part, second and third conductive layers formed in contact with the oxide semiconductor layer, an insulating layer which covers the oxide semiconductor layer and the second and third conductive layers, and a fourth conductive layer over the insulating layer that overlaps with part of the oxide semiconductor layer.
    Type: Grant
    Filed: September 30, 2010
    Date of Patent: April 1, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Kei Takahashi, Yoshiaki Ito
  • Patent number: 8686415
    Abstract: An object is to provide a semiconductor memory device capable of shortening writing operation by concurrently determining potentials of memory cells on one word line. A plurality of transistors having switching characteristics are connected to one potential control circuit, whereby writing potentials are determined concurrently. A potential continues to be changed (raised or decreased) stepwise, a desired potential is determined while changing the potential, and whether data resulted from reading with respect to written data is correct or not is continuously checked, so that high-precision writing operation and high-precision reading operation can be achieved. In addition, favorable switching characteristics and holding characteristics of a transistor including an oxide semiconductor are utilized.
    Type: Grant
    Filed: December 12, 2011
    Date of Patent: April 1, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Koichiro Kamata
  • Patent number: 8686416
    Abstract: Provided is an oxide semiconductor film which has more stable electric characteristics and essentially consists of indium zinc oxide. In addition, provided is a highly reliable semiconductor device which has stable electric characteristics by using the oxide semiconductor film. The oxide semiconductor film essentially consisting of indium zinc oxide has a hexagonal crystal structure in which the a-b plane is substantially parallel to a surface of the oxide semiconductor film and a rhombohedral crystal structure in which the a-b plane is substantially parallel to the surface of the oxide semiconductor film.
    Type: Grant
    Filed: March 15, 2012
    Date of Patent: April 1, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tatsuya Honda, Hiroshi Kanemura, Kengo Akimoto, Suzunosuke Hiraishi
  • Patent number: 8686417
    Abstract: An object is to manufacture a semiconductor device including an oxide semiconductor at low cost with high productivity in such a manner that a photolithography process is simplified by reducing the number of light-exposure masks. In a method for manufacturing a semiconductor device including a channel-etched inverted-staggered thin film transistor, an oxide semiconductor film and a conductive film are etched using a mask layer formed with the use of a multi-tone mask which is a light-exposure mask through which light is transmitted so as to have a plurality of intensities. In etching steps, a first etching step is performed by wet etching in which an etchant is used, and a second etching step is performed by dry etching in which an etching gas is used.
    Type: Grant
    Filed: July 23, 2012
    Date of Patent: April 1, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hideomi Suzawa, Shinya Sasagawa, Taiga Muraoka, Shunichi Ito, Miyuki Hosoba
  • Patent number: 8686419
    Abstract: A memory device in a 3-D read and write memory includes a resistance-changing layer, and a local contact resistance in series with, and local to, the resistance-changing layer. The local contact resistance is established by a junction between a semiconductor layer and a metal layer. Further, the local contact resistance has a specified level of resistance according to a doping concentration of the semiconductor and a barrier height of the junction. A method for fabricating such a memory device is also presented.
    Type: Grant
    Filed: February 17, 2011
    Date of Patent: April 1, 2014
    Assignee: SanDisk 3D LLC
    Inventors: Franz Kreupl, Deepak C Sekar
  • Patent number: 8686420
    Abstract: An organic light emitting diode (OLED) display includes a substrate including a plurality of pixels defined thereon, a thin film transistor (TFT) positioned at each pixel, a negative electrode electrically connected to the TFT, an organic emission layer positioned on the negative electrode, and a positive electrode positioned on the organic emission layer, the positive electrode including an auxiliary layer positioned on the organic emission layer, a conductive layer positioned on the auxiliary layer, and an insulation layer positioned on the conductive layer.
    Type: Grant
    Filed: March 18, 2011
    Date of Patent: April 1, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: Il-Soo Oh, Chang-Ho Lee, Hee-Joo Ko, Se-Jin Cho, Hyung-Jun Song, Jin-Young Yun, Jong-Hyuk Lee
  • Patent number: 8686422
    Abstract: A stem wiring (13a) having a broad line width is formed above branch wirings (13b) having a narrow line width. In a region where the stem wiring (13a) is connected to the branch wiring (13b), the stem wiring (13a) overlaps with the branch wiring (13b) via a gate insulating film when seen in a plan view, a contact hole is provided in the gate insulating film so as to uncover the branch wiring (13b), and the stem wiring (13a) is electrically connected to the branch wiring (13b) via a connecting conductor formed in the contact hole. Consequently, a TFT array substrate can be achieved, in which a disconnection failure or an abnormal line width is reduced without enlarging the dimension of a driving circuit region.
    Type: Grant
    Filed: April 2, 2010
    Date of Patent: April 1, 2014
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Masahiro Yoshida, Isao Ogasawara, Shinya Tanaka
  • Patent number: 8686423
    Abstract: A thin film transistor array panel according to an exemplary embodiment of the present invention comprises a substrate, a gate line formed on the substrate, a gate insulating layer formed on the gate line, a semiconductor layer formed on the gate insulating layer, and a data line formed on the semiconductor layer, wherein the data line comprises a lower data layer, an upper data layer, a data oxide layer, and a buffer layer, wherein the upper data layer and the buffer layer comprise a same material.
    Type: Grant
    Filed: September 5, 2012
    Date of Patent: April 1, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: Sung-Ryul Kim, Jean-Ho Song, Jae-Hyoung Youn, O-Sung Seo, Byeong-Beom Kim, Je-Hyeong Park, Jong-In Kim, Jae-Jin Song
  • Patent number: 8686424
    Abstract: Disclosed is a method of manufacturing a bipolar transistor, comprising providing a substrate (10) comprising a first isolation region (12) separated from a second isolation region by an active region (11) comprising a collector impurity; forming a layer stack over said substrate, said layer stack comprising a base layer (14, 14?), a silicon capping layer (15) over said base layer and a silicon-germanium (SiGe) base contact layer (40) over said silicon capping layer; etching the SiGe base contact layer to form an emitter window (50) over the collector impurity, wherein the silicon emitter cap layer is used as etch stop layer; forming sidewall spacers (22) in the emitter window; and filling the emitter window with an emitter material (24). A bipolar transistor manufactured in accordance with this method and an IC comprising one or more of such bipolar transistors are also disclosed.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: April 1, 2014
    Assignee: NXP, B.V.
    Inventors: Evelyne Gridelet, Johannes Josephus Theodorus Marinus Donkers, Tony Vanhoucke, Petrus Hubertus Cornelis Magnee, Hans Mertens, Blandine Duriez
  • Patent number: 8686425
    Abstract: A larger substrate can be used, and a transistor having a desirably high field-effect mobility can be manufactured through formation of an oxide semiconductor layer having a high degree of crystallinity, whereby a large-sized display device, a high-performance semiconductor device, or the like can be put into practical use. A first multi-component oxide semiconductor layer is formed over a substrate and a single-component oxide semiconductor layer is formed thereover; then, crystal growth is carried out from a surface to an inside by performing heat treatment at 500° C. to 1000° C. inclusive, preferably 550° C. to 750° C. inclusive so that a first multi-component oxide semiconductor layer including single crystal regions and a single-component oxide semiconductor layer including single crystal regions are formed; and a second multi-component oxide semiconductor layer including single crystal regions is stacked over the single-component oxide semiconductor layer including single crystal regions.
    Type: Grant
    Filed: August 14, 2012
    Date of Patent: April 1, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Takuya Hirohashi, Masahiro Takahashi, Takashi Shimazu
  • Patent number: 8686426
    Abstract: A plural semiconductive oxides TFT (sos-TFT) provides improved electrical functionality in terms of charge-carrier mobility and/or threshold voltage variability. The sos-TFT may be used to form a thin film transistor array panel for display devices. An example sos-TFT includes: an insulated gate electrode; a first semiconductive oxide layer having a composition including a first semiconductive oxide; and a second semiconductive oxide layer having a different composition that also includes a semiconductive oxide. The first and second semiconductive oxide layers have respective channel regions that are capacitively influenced by a control voltage applied to the gate electrode. In one embodiment, the second semiconductive oxide layer includes at least one additional element that is not included in the first semiconductive oxide layer where the additional element is one of gallium (Ga), silicon (Si), niobium (Nb), hafnium (Hf), and germanium (Ge).
    Type: Grant
    Filed: July 23, 2012
    Date of Patent: April 1, 2014
    Assignees: Samsung Display Co., Ltd., Kobe Steel, Ltd.
    Inventors: Byung Du Ahn, Ji Hun Lim, Gun Hee Kim, Kyoung Won Lee, Je Hun Lee
  • Patent number: 8686427
    Abstract: A display apparatus includes a first substrate including pixels, a second substrate facing the first substrate, and a liquid crystal layer interposed between the first substrate and the second substrate. Each of the pixels includes a thin film transistor disposed on a first insulating substrate, a first protective layer that covers the thin film transistor and includes a SiOC layer, a first electrode disposed on the first protective layer, a second protective layer that covers the first electrode, and a second electrode disposed on the second protective layer.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: April 1, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: Chang Ok Kim, Hyeongsuk Yoo, Jieun Nam, Kiseong Seo, Jae Sul An, Taeyoung Ahn, Jungyun Jo
  • Patent number: 8686428
    Abstract: A device with an external surface, the device including: a substrate including first mono-crystal transistors; a second layer including second mono-crystal transistors, the second mono-crystal transistors overlaying the first mono-crystal transistors; and a plurality of thermal conduction paths from a plurality of the second layer locations to the external surface, wherein at least one of the thermal conduction paths includes an electrically nonconductive contact.
    Type: Grant
    Filed: November 16, 2012
    Date of Patent: April 1, 2014
    Assignee: Monolithic 3D Inc.
    Inventors: Deepak Sekar, Zvi Or-Bach, Brian Cronquist
  • Patent number: 8686429
    Abstract: Embodiments of the present invention are generally related to LED chips having improved overall emission by reducing the light-absorbing effects of barrier layers adjacent mirror contacts. In one embodiment, a LED chip comprises one or more LEDs, with each LED having an active region, a first contact under the active region having a highly reflective mirror, and a barrier layer adjacent the mirror. The barrier layer is smaller than the mirror such that it does not extend beyond the periphery of the mirror. In another possible embodiment, an insulator is further provided, with the insulator adjacent the barrier layer and adjacent portions of the mirror not contacted by the active region or by the barrier layer. In yet another embodiment, a second contact is provided on the active region.
    Type: Grant
    Filed: June 24, 2011
    Date of Patent: April 1, 2014
    Assignee: Cree, Inc.
    Inventors: Michael Bergmann, Matthew Donofrio, Sten Heikman, Kevin S. Schneider, Kevin W. Haberern, John A. Edmond
  • Patent number: 8686430
    Abstract: A buffer layer of zinc telluride (ZnTe) or titanium dioxide (TiO2) is formed directly on a silicon substrate. Optionally, a layer of AlN is then formed as a second layer of the buffer layer. A template layer of GaN is then formed over the buffer layer. An epitaxial LED structure for a GaN-based blue LED is formed over the template layer, thereby forming a first multilayer structure. A conductive carrier is then bonded to the first multilayer structure. The silicon substrate and the buffer layer are then removed, thereby forming a second multilayer structure. Electrodes are formed on the second multilayer structure, and the structure is singulated to form blue LED devices.
    Type: Grant
    Filed: September 7, 2011
    Date of Patent: April 1, 2014
    Assignee: Toshiba Techno Center Inc.
    Inventor: Zhen Chen
  • Patent number: 8686431
    Abstract: Techniques for manufacturing optical devices, such as light emitting diodes (LEDs) using a separation process of thick gallium and nitrogen containing substrate members, are described.
    Type: Grant
    Filed: October 25, 2011
    Date of Patent: April 1, 2014
    Assignee: Soraa, Inc.
    Inventors: Max Batres, Aurelien David
  • Patent number: 8686432
    Abstract: A semiconductor device composed of a Group III nitride semiconductor has the following structure. A substrate has on it an n-type first semiconductor layer, an active layer, and a p-type second semiconductor layer in this order. Two first end faces are formed by cleavage and oppose each other in planar view. Two trenches extend to the two first end faces in the direction orthogonal to the first end faces in planar view. Bottoms of the trenches are positioned at least below the lower surface of the active layer. Second end faces are formed by laser scribing in the direction orthogonal to the first end faces and outside the trenches.
    Type: Grant
    Filed: June 29, 2012
    Date of Patent: April 1, 2014
    Assignee: Renesas Electronics Corporation
    Inventor: Kazuhisa Fukuda
  • Patent number: 8686433
    Abstract: A light emitting device includes a light emitting layer, a substrate that is transparent to an emission wavelength of the light emitting layer and positioned to receive an emission wavelength from the light emitting layer, a convex pattern including a collection of a plurality of convex portions discretely arranged on a front surface of the substrate with a first pitch, an n type nitride semiconductor layer located on the front surface of the substrate to cover the convex pattern and a p type nitride semiconductor layer located on the light emitting layer. The light emitting layer is located on the n type semiconductor layer. Each of the convex portions includes a sub convex pattern comprising a plurality of fine convex portions discretely formed at the top of the convex portion with a second pitch smaller than the first pitch, and a base supporting the sub convex pattern.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: April 1, 2014
    Assignee: Rohm Co., Ltd.
    Inventors: Nobuaki Matsui, Hirotaka Obuchi, Yasuo Nakanishi, Kazuaki Tsutsumi, Takao Fujimori
  • Patent number: 8686434
    Abstract: There is provided a silicon carbide semiconductor device having excellent electrical characteristics such as channel mobility, and a method for manufacturing the same. A semiconductor device includes a substrate made of silicon carbide and having an off-angle of greater than or equal to 50° and less than or equal to 65° with respect to a surface orientation of {0001}, a p-type layer serving as a semiconductor layer, and an oxide film serving as an insulating film. The p-type layer is formed on the substrate and is made of silicon carbide. The oxide film is formed to contact with a surface of the p-type layer. A maximum value of the concentration of nitrogen atoms in a region within 10 nm of an interface between the semiconductor layer and the insulating film (interface between a channel region and the oxide film) is greater than or equal to 1×1021 cm?3.
    Type: Grant
    Filed: February 3, 2009
    Date of Patent: April 1, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Shin Harada, Takeyoshi Masuda, Keiji Wada, Masato Tsumori
  • Patent number: 8686435
    Abstract: A silicon carbide layer is epitaxially formed on a main surface of a substrate. The silicon carbide layer is provided with a trench having a side wall inclined relative to the main surface. The side wall has an off angle of not less than 50° and not more than 65° relative to a {0001} plane. A gate insulating film is provided on the side wall of the silicon carbide layer. The silicon carbide layer includes: a body region having a first conductivity type and facing a gate electrode with the gate insulating film being interposed therebetween; and a pair of regions separated from each other by the body region and having a second conductivity type. The body region has an impurity density of 5×1016 cm?3 or greater. This allows for an increased degree of freedom in setting a threshold voltage while suppressing decrease of channel mobility.
    Type: Grant
    Filed: March 29, 2012
    Date of Patent: April 1, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Takeyoshi Masuda, Toru Hiyoshi, Keiji Wada
  • Patent number: 8686436
    Abstract: According to one embodiment, a semiconductor device includes a first semiconductor region, a second semiconductor region, a third semiconductor region, a fourth semiconductor region, an insulating film, a control electrode, a first electrode, and a second electrode. The first semiconductor region includes silicon carbide, and has a first portion. The second semiconductor region is provided on the first semiconductor region, and includes silicon carbide. The third semiconductor region and the fourth semiconductor region are provided on the second semiconductor region, and includes silicon carbide. The electrode is provided on the film. The second semiconductor region has a first region and a second region. The first region contacts with the third semiconductor region and the fourth semiconductor region. The second region contacts with the first portion. The impurity concentration of the first region is higher than an impurity concentration of the second region.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: April 1, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Kono, Takashi Shinohe, Takuma Suzuki, Johji Nishio
  • Patent number: 8686437
    Abstract: According to one embodiment, a semiconductor device includes a first, a second, a third, a fourth, and a fifth semiconductor region, an insulating film, a control electrode, and a first and a second electrode. The first, the second, the third, the fourth and the fifth semiconductor region include silicon carbide. The first semiconductor region has a first impurity concentration, and has a first portion. The second semiconductor region is provided on the first semiconductor region. The third semiconductor region is provided on the second semiconductor region. The fourth semiconductor region is provided between the first portion and the second semiconductor region. The fourth semiconductor region is provided between the first portion and the third semiconductor region. The fifth semiconductor region includes a first region provided between the first portion and the second semiconductor region, and has a second impurity concentration higher than the first impurity concentration.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: April 1, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Kono, Takashi Shinohe, Takuma Suzuki, Johji Nishio
  • Patent number: 8686438
    Abstract: When viewed in a plan view, a termination region (TM) surrounds an element region (CL). A first side of a silicon carbide substrate (SB) is thermally etched to form a side wall (ST) and a bottom surface (BT) in the silicon carbide substrate (SB) at the termination region (TM). The side wall (ST) has a plane orientation of one of {0-33-8} and {0-11-4}. The bottom surface (BT) has a plane orientation of {000-1}. On the side wall (ST) and the bottom surface (BT), an insulating film (8T) is formed. A first electrode (12) is formed on the first side of the silicon carbide substrate (SB) at the element region (CL). A second electrode (14) is formed on a second side of the silicon carbide substrate (SB).
    Type: Grant
    Filed: October 17, 2012
    Date of Patent: April 1, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Toru Hiyoshi, Takeyoshi Masuda, Keiji Wada
  • Patent number: 8686439
    Abstract: This silicon carbide semiconductor element includes: a body region of a second conductivity type which is located on a drift layer of a first conductivity type; an impurity region of the first conductivity type which is located on the body region; a trench which runs through the body region and the impurity region to reach the drift layer; a gate insulating film which is arranged on surfaces of the trench; and a gate electrode which is arranged on the gate insulating film. The surfaces of the trench include a first side surface and a second side surface which is opposed to the first side surface. The concentration of a dopant of the second conductivity type is higher at least locally in a portion of the body region which is located beside the first side surface than in another portion of the body region which is located beside the second side surface.
    Type: Grant
    Filed: June 25, 2012
    Date of Patent: April 1, 2014
    Assignee: Panasonic Corporation
    Inventors: Kunimasa Takahashi, Masahiko Niwayama, Masao Uchida, Chiaki Kudou
  • Patent number: 8686440
    Abstract: In at least one embodiment of the organic light-emitting component (10), the latter comprises a unipolar charge carrier balder layer (3), a first layer (1) and a second layer (2) which are applied to opposing sides of the charge carrier barrier layer (3) and are in each case formed of at least one organic material, and two ambipolar injection layers (4), which are applied to the sides of the first (1) and second layers (2) remote from the charge carrier barrier layer (3). Such an organic, light-emitting component (10) may be operated efficiently with alternating current.
    Type: Grant
    Filed: May 7, 2009
    Date of Patent: April 1, 2014
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Thomas Dobbertin, Nina Riegel
  • Patent number: 8686441
    Abstract: A semiconductor light emitting device includes first and second semiconductor layers, an active region, a transparent electrically-conducting layer 13, a reflecting structure 20, and a first electrode. The second semiconductor layer has a conductivity different from the first semiconductor layer. The active region is arranged between the first and second semiconductor layers. The transparent electrically-conducting layer 13 is arranged on or above the first semiconductor layer. The reflecting structure 20 is arranged on or above the transparent electrically-conducting layer 13. The first electrode is arranged on or above the reflecting structure 20, and electrically connected to the first semiconductor layer. The reflecting structure 20 includes at least a reflective layer 16. An intermediate layer 17 is interposed between the transparent electrically-conducting layer 13 and the reflecting structure 20.
    Type: Grant
    Filed: April 6, 2012
    Date of Patent: April 1, 2014
    Assignee: Nichia Corporation
    Inventors: Toshiaki Ogawa, Hisashi Kasai, Masahiko Sano
  • Patent number: 8686442
    Abstract: The present invention provides a nitride semiconductor light emitting device having an n-electrode that has an Au face excellent in ohmic contacts to an n-type nitride semiconductor and excellent in mounting properties, and a method of manufacturing the same. The nitride semiconductor light emitting device uses an n-electrode having a three-layer laminate structure that is composed of a first layer containing aluminum nitride and having a thickness not less than 1 nm or less than 5 nm, a second layer containing one or more metals selected from Ti, Zr, Hf, Mo, and Pt, and a third layer made of Au, from the near side of the n-type nitride semiconductor in order of mention. The n-electrode thus formed is then annealed to obtain ohmic contacts to the n-type nitride semiconductor.
    Type: Grant
    Filed: May 22, 2012
    Date of Patent: April 1, 2014
    Assignee: Oclaro Japan, Inc.
    Inventors: Akihisa Terano, Aki Takei
  • Patent number: 8686443
    Abstract: An organic light-emitting display device comprises a substrate including a plurality of light-emitting regions separated by a non-light-emitting region, an organic light-emitting element disposed on each of the light-emitting regions, and a photoactive element disposed on the non-light-emitting region.
    Type: Grant
    Filed: August 31, 2011
    Date of Patent: April 1, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventor: Byung-Uk Han
  • Patent number: 8686444
    Abstract: An organic light emitting device including a substrate on which an organic light emitting unit is formed, wherein the organic light emitting unit sequentially includes a first electrode, an organic layer, and a second electrode; and a passivation layer covering the substrate and the second electrode, and a method of manufacturing the organic light emitting device.
    Type: Grant
    Filed: June 14, 2010
    Date of Patent: April 1, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: Yong-Tak Kim, Jong-Hyuk Lee, Won-Jong Kim, Joon-Gu Lee, Jin-Baek Choi
  • Patent number: 8686445
    Abstract: A light emission package includes at least one solid state emitter, a leadframe including at least one electrical lead and a body structure encasing a portion of the leadframe. A thermal transfer material can be isolated from the at least one electrical lead. The body structure can include a plastic body structure wherein a rim portion can be disposed along a portion of the upper surface of the body structure. The light emission package can also include the at least one solid state emitter mounted over thermal transfer material using a direct metal-to-metal bond such as by eutectic die attachment. The light emission package is operable to emit light with an output of approximately 70% or greater of an initial light output for an extrapolated time of at least approximately 150,000 hours or more.
    Type: Grant
    Filed: December 15, 2010
    Date of Patent: April 1, 2014
    Assignee: Cree, Inc.
    Inventors: Christopher P. Hussell, Amber C. Abare, Jesse Colin Reiherzer
  • Patent number: 8686446
    Abstract: A capacitor device prevents capacitor failure and pixel failure by preventing the capacitor from experiencing a short circuit caused by disconnection of a bridge formed between electrodes of the capacitor and a display apparatus having the capacitor device. A display device comprises a thin film transistor, a light emitting device, and the capacitor device described above.
    Type: Grant
    Filed: August 30, 2011
    Date of Patent: April 1, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventor: Sang-Min Hong
  • Patent number: 8686447
    Abstract: A light emitting unit including plural kinds of light emitting elements with different light emitting wavelengths, wherein, among the light emitting elements, at least one kind of light emitting element includes a semiconductor layer configured by laminating a first conductive layer, an active layer and a second conductive layer and having a side surface exposed by the first conductive layer, the active layer and the second conductive layer; a first electrode electrically connected to the first conductive layer; a second electrode electrically connected to the second conductive layer; a first insulation layer contacting at least an exposed surface of the active layer in the surface of the semiconductor layer; and a metal layer contacting at least a surface, which is opposite to the exposed surface of the active layer, in the surface of the first insulation layer, and electrically separated from the first electrode and the second electrode.
    Type: Grant
    Filed: February 22, 2012
    Date of Patent: April 1, 2014
    Assignee: Sony Corporation
    Inventors: Katsuhiro Tomoda, Naoki Hirao, Goshi Biwa
  • Patent number: 8686448
    Abstract: D={(2?m+?L+?U)/4?}? is satisfied when an optical path length between a reflecting layer and pixel electrode and a counter electrode is D, a phase shift in reflection in the reflecting layer and pixel electrode is ?L, a phase shift in reflection in the counter electrode is ?U, a peak wavelength of a standing wave generated between the reflecting layer and pixel electrode, and the counter electrode is ?, and an integer of 2 or less is m. Here, among red, green, and blue pixel reflecting layer and pixel electrode, at least one reflecting layer and pixel electrode may be made of a different metal material from that of the other reflecting layer and pixel electrodes.
    Type: Grant
    Filed: May 23, 2012
    Date of Patent: April 1, 2014
    Assignee: Seiko Epson Corporation
    Inventor: Koya Shiratori
  • Patent number: 8686449
    Abstract: A light emitting device comprises a substantially planar light transmissive substrate having a light emitting surface and an opposite surface. The substrate is configured as a light guiding medium. The light emitting device also comprises at least one phosphor material disposed as a layer on the light emitting surface with a plurality of window areas and at least one source of excitation radiation of a first wavelength positioned adjacent to at least one peripheral edge of the substrate. The source is configured to couple excitation radiation into the substrate such that it is waveguided within the substrate by total internal reflection. Additionally, the light emitted by the device from the light emitting surface comprises first wavelength radiation and second, longer wavelength photoluminescent light emitted by the phosphor layer as a result of excitation by the source.
    Type: Grant
    Filed: May 25, 2012
    Date of Patent: April 1, 2014
    Assignee: Intematix Corporation
    Inventor: Yi-Qun Li
  • Patent number: 8686450
    Abstract: The present invention relates to a method of manufacturing a vertically-structured GaN-based light emitting diode. The method of manufacturing a vertically-structured GaN-based light emitting diode includes forming a GaN layer on a substrate; patterning the compound layer in a predetermined shape; forming an n-type GaN layer on the patterned compound layer through the epitaxial lateral over-growth process and sequentially forming an active layer and a p-type GaN layer on the n-type GaN layer; forming a structure supporting layer on the p-type GaN layer; sequentially removing the substrate and the GaN layer formed on the substrate after forming the structure supporting layer; removing the patterned compound layer exposed after removing the GaN layer so as to form an n-type GaN layer patterned in a concave shape; and forming an n-type electrode on the n-type GaN layer patterned in a concave shape.
    Type: Grant
    Filed: August 23, 2007
    Date of Patent: April 1, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae Hoon Lee, Hee Seok Choi, Jeong Tak Oh, Su Yeol Lee
  • Patent number: 8686451
    Abstract: An optoelectronic component (100) comprises a first semiconductor layer stack (101), which has an active layer (110) designed for the emission of radiation and a main area (111). A separating layer (103) is arranged on said main area, said separating layer forming a semitransparent mirror. The optoelectronic component comprises a second semiconductor layer stack (102), which is arranged at the separating layer and which has a further active layer (120) designed for the emission of radiation.
    Type: Grant
    Filed: January 19, 2009
    Date of Patent: April 1, 2014
    Assignee: OSRAM Opto Semiconductor GmbH
    Inventors: Nikolaus Gmeinwieser, Berthold Hahn
  • Patent number: 8686452
    Abstract: An optoelectronic apparatus includes an optical device with an optical structure including a plurality of optical elements, and a radiation-emitting or radiation-receiving semiconductor chip with a contact structure which includes a plurality of contact elements that make electrical contact with the semiconductor chip and are spaced apart vertically from the optical structure, wherein the contact elements are arranged in interspaces between the optical elements upon a projection of the contact structure into the plane of the optical structure.
    Type: Grant
    Filed: June 25, 2009
    Date of Patent: April 1, 2014
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Peter Brick, Julius Muschaweck, Joachim Frank
  • Patent number: 8686453
    Abstract: Provided is a light emitting device. The light emitting device comprises: In one embodiment, a light emitting device includes: a light emitting structure comprising a first conductive type semiconductor layer, a second conductive type semiconductor layer, and an active layer between the first conductive type semiconductor layer and the second conductive type semiconductor layer; and a conductive support member under the light emitting structure. The conductive support member comprises a first conductive support member and a second conductive support member. The second conductive support member has a thermal conductivity higher than that of the first conductive support member.
    Type: Grant
    Filed: January 14, 2011
    Date of Patent: April 1, 2014
    Assignee: LG Innotek Co.,, Ltd.
    Inventors: Jung Hyeok Bae, Young Kyu Jeong, Kyung Wook Park, Duk Hyun Park
  • Patent number: 8686454
    Abstract: There is provided a semiconductor light emitting device including a conductive substrate, a first electrode layer, an insulating layer, a second electrode layer, a second semiconductor layer, an active layer, and a first semiconductor layer that are sequentially stacked. The contact area between the first electrode layer and the first semiconductor layer is 3% to 13% of the total area of the semiconductor light emitting device, and thus high luminous efficiency is achieved.
    Type: Grant
    Filed: October 22, 2009
    Date of Patent: April 1, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Pun Jae Choi, Yu Seung Kim, Jin Bock Lee
  • Patent number: 8686455
    Abstract: A composite substrate for the formation of a light-emitting device, ensuring that a high-quality nitride-based light-emitting diode can be easily formed on its top surface and the obtained substrate-attached light-emitting diode functions as a light-emitting device capable of emitting light for an arbitrary color such as white, is provided.
    Type: Grant
    Filed: March 2, 2010
    Date of Patent: April 1, 2014
    Assignees: Ube Industries, Ltd., Riken
    Inventors: Yasuyuki Ichizono, Hideki Hirayama
  • Patent number: 8686456
    Abstract: Provided are a light emitting device, a light emitting device package, and a light unit. The light emitting device includes a support substrate, a light emitting structure layer disposed on the support substrate, the light emitting structure layer including a first conductive type semiconductor layer, a second conductive type semiconductor layer, and an active layer disposed between the first conductive type semiconductor layer and the second conductive type semiconductor layer, an electrode electrically connected to the first conductive type semiconductor layer, and a volume layer disposed on the light emitting structure layer, the volume layer having a thickness greater than a thickness of the electrode.
    Type: Grant
    Filed: August 25, 2011
    Date of Patent: April 1, 2014
    Assignee: LG Innotek Co., Ltd.
    Inventor: Hwan Hee Jeong
  • Patent number: 8686457
    Abstract: A light emitting element having a recess-protrusion structure on a substrate is provided. A semiconductor light emitting element 100 has a light emitting structure of a semiconductor 20 on a first main surface of a substrate 10. The first main surface of the substrate 10 has substrate protrusion portion 11, the bottom surface 14 of each protrusion is wider than the top surface 13 thereof in a cross-section, or the top surface 13 is included in the bottom surface 14 in a top view of the substrate. The bottom surface 14 has an approximately polygonal shape, and the top surface 13 has an approximately circular or polygonal shape with more sides than that of the bottom surface 14.
    Type: Grant
    Filed: February 5, 2013
    Date of Patent: April 1, 2014
    Assignee: Nichia Corporation
    Inventors: Shunsuke Minato, Junya Narita, Yohei Wakai, Yukio Narukawa, Motokazu Yamada
  • Patent number: 8686458
    Abstract: A light emitting diode device emitting at a wavelength of 390-415 nm has a bulk gallium and nitrogen containing substrate with an active region. The device has a current density of greater than about 175 Amps/cm2 and an external quantum efficiency with a roll off of less than about 5% absolute efficiency.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: April 1, 2014
    Assignee: Soraa, Inc.
    Inventors: Michael R. Krames, Mark P. D'Evelyn, James W. Raring, Thomas M. Katona