Abstract: The present invention provides a light-transmitting metal electrode including a substrate and a metal electrode layer having plural openings. The metal electrode layer also has such a continuous metal part that any pair of point-positions in the part is continuously connected without breaks. The openings in the metal electrode layer are periodically arranged to form plural microdomains. The plural microdomains are so placed that the in-plane arranging directions thereof are oriented independently of each other. The thickness of the metal electrode layer is in the range of 10 to 200 nm.

Abstract: A flip-chip semiconductor based Light Emitting Device (LED) can include an n-type semiconductor substrate and an n-type GaN epi-layer on the substrate. A p-type GaN epi-layer can be on the n-type GaN epi-layer and a metal ohmic contact p-electrode can be on the p-type GaN epi-layer, where the metal ohmic contact p-electrode can have an average thickness less than about 25 ?. A reflector can be on the metal ohmic contact p-electrode and a metal stack can be on the reflector. An n-electrode can be on the substrate opposite the n-type GaN epi-layer and a bonding pad can be on the n-electrode.

Abstract: A light emitting diode (LED) die includes a first substrate having a first surface and an opposing second surface; a second substrate on the second surface of the first substrate; a p-type semiconductor layer on the first surface of the first substrate; a multiple quantum well (MQW) layer on the p-type semiconductor layer configured to emit light; and an n-type semiconductor layer on the multiple quantum well (MQW) layer.

Abstract: The application provides an optoelectronic device structure, comprising a semiconductor stack, comprising a first conductivity type semiconductor layer, an active layer, and a second conductivity type semiconductor layer; a first electrode electrically connecting with the first conductivity type semiconductor layer, and further comprising a first extension electrode; a second electrode electrically connecting with the second conductivity type semiconductor layer; and a plurality of electrical restraint contact areas between the semiconductor stack and the first extension electrode, wherein the plurality of electrical restraint contact areas is distributed in a variable interval.

Abstract: A capping system includes: a moving portion moving a stem, on which an optical semiconductor element is mounted, horizontally; a fixer fixing a cap having a window, on the stem; a camera taking an image of the cap and the stem from above the cap and the stem; a detector detecting whether the optical semiconductor element is present within a visual field of the camera; and a searching action controller controlling the moving portion to move the stem so the detector searches the optical semiconductor element. The searching action controller causes searching radially and outwardly from a search starting point.

Abstract: According to one embodiment, an LED module includes a substrate, an interconnect layer, a light emitting diode (LED) package, and a reflection member. The interconnect layer is provided on the substrate. The LED package is mounted on the interconnect layer. The reflection member is provided on a region in the substrate where the LED package is not mounted and has a property of reflecting light emitted from the LED package. The LED package includes a first lead frame, a second lead frame, an LED chip, and a resin body. The first lead frame and the second lead frame are arranged apart from each other on the same plane. The LED chip is provided above the first lead frame and the second lead frame, with one terminal connected to the first lead frame and one other terminal connected to the second lead frame.

Abstract: Glass is provided which is capable of covering at a covering treatment temperature of at most 400° C. and which has a low thermal expansion coefficient and excellent weather resistance. Glass comprising, as represented by mol % based on oxides, from 29% to 33% of P2O5, from 43% to 58% of SnO, from 11% to 25% of ZnO, from 0.1% to 2% of Ga2O3, from 0.5% to 5% of CaO, and from 0% to 1% of SrO, provided that the sum X of ZnO, Ga2O3 and CaO is within a range of from 13% to 27%, as represented by mol % based on oxides.

Abstract: A method for growth and fabrication of semipolar (Ga, Al, In, B)N thin films, heterostructures, and devices, comprising identifying desired material properties for a particular device application, selecting a semipolar growth orientation based on the desired material properties, selecting a suitable substrate for growth of the selected semipolar growth orientation, growing a planar semipolar (Ga, Al, In, B)N template or nucleation layer on the substrate, and growing the semipolar (Ga, Al, In, B)N thin films, heterostructures or devices on the planar semipolar (Ga, Al, In, B)N template or nucleation layer. The method results in a large area of the semipolar (Ga, Al, In, B)N thin films, heterostructures, and devices being parallel to the substrate surface.

Abstract: A semiconductor device includes a semiconductor substrate in which a diode region and an IGBT region are formed, wherein a lower surface side of the semiconductor substrate comprises a low impurity region provided between a second conductivity type cathode region of the diode region and a first conductivity type collector region of the IGBT region. The low impurity region includes at least one of a first conductivity type first low impurity region which has a lower density of first conductivity type impurities than that in the collector region and a second conductivity type second low impurity region which has a lower density of second conductivity type impurities than that in the cathode region.

Abstract: A trench semiconductor power device with a termination area structure is disclosed. The termination area structure comprises a wide trench and a trenched field plate formed not only along trench sidewall but also on trench bottom of the wide trench by doing poly-silicon CMP so that the body ion implantation is blocked by the trenched field plate on the trench bottom to prevent the termination area underneath the wide trench from being implanted. Moreover, a contact mask is used to define both trenched contacts and source regions of the device for saving a source mask.

Abstract: A semiconductor device includes a semiconductor substrate having a diode active region and an edge termination region adjacent to each other, a first region of a first conductivity type in the diode active region, a second region of a second conductivity type, a third region of the first conductivity type in the edge termination region, and a fourth region of the second conductivity type. The first region and the third region share a drift region of the first conductivity type. The first region and the third region share a fifth region of the first conductivity type. The drift region in the third region is greater in number of crystal defects per unit volume than the drift region in the first region in order that the drift region in the third region is shorter in carrier lifetime than the drift region in the first region.

Abstract: An integrated circuit device provides electrostatic discharge (ESD) protection. In connection with various example embodiments, an ESD protection circuit includes a diode-type circuit having a p-n junction that exhibits a low breakdown voltage. Connected in series with the diode between an internal node susceptible to an ESD pulse and ground, are regions of opposite polarity having junctions therebetween for mitigating the passage of leakage current via voltage sharing with the diode's junction. Upon reaching the breakdown voltage, the diode shunts current to ground via another substrate region, bypassing one or more junctions of the regions of opposite polarity and facilitating a low clamping voltage.

Abstract: Disclosed are minority carrier based mercury-cadmium telluride (HgCdTe) infrared detectors and arrays, and methods of making, are disclosed. The constructions provided by the invention enable the detectors to be used at higher temperatures, and/or be implemented on less expensive semiconductor substrates to lower manufacturing costs. An exemplary embodiment a substrate, a bottom contact layer disposed on the substrate, a first mercury-cadmium telluride layer having a first bandgap energy value disposed on the bottom contact layer, a second mercury-cadmium telluride layer having a second bandgap energy value that is greater than the first bandgap energy value disposed on the first mercury-cadmium telluride layer, and a collector layer disposed on the second mercury-cadmium telluride layer, wherein the first and second mercury-cadmium telluride layers are each doped with an n-type dopant.

Abstract: There is provided a semiconductor wafer including a base wafer, an insulating layer, and a Si crystal layer in the stated order. The semiconductor wafer further includes an inhibition layer that is provided on the Si crystal layer and has an opening penetrating therethrough to reach the Si crystal layer. The inhibition layer inhibiting crystal growth of a compound semiconductor. Furthermore, a seed crystal is provided within the opening, and a compound semiconductor has a lattice match or a pseudo lattice match with the seed crystal.

Abstract: The interface resistance between the source/drain and gate of an HFET may be significantly reduced by engineering the bandgap of the 2DEG outside a gate region such that the charge density is substantially increased. The resistance may be further reduced by using an n+GaN Cap layer over the channel layer and barrier layer such that a horizontal surface of the barrier layer beyond the gate region is covered by the n+GaN Cap layer. This technique is applicable to depletion and enhancement mode HFETs.

Abstract: A structure comprises a substrate, a mask, a buffer/nucleation layer, and a group III-V compound semiconductor material. The substrate has a top surface and has a recess from the top surface. The recess includes a sidewall. The first mask is the top surface of the substrate. The buffer/nucleation layer is along the sidewall, and has a different material composition than a material composition of the sidewall. The III-V compound semiconductor material continuously extends from inside the recess on the buffer/nucleation layer to over the first mask.

Abstract: A cell element field for data processing having function cells for execution of algebraic and/or logic functions and memory cells for receiving, storing and/or outputting information is described. A control connection may lead from the function cells to the memory cells.

Abstract: A memory cell is provided that includes a diode and a resistance-switching material layer coupled in series with the diode. The resistance-switching material layer: (a) includes a material from the family consisting of XvOw, wherein X represents an element from the family consisting of Hf and Zr, and wherein the subscripts v and w have non-zero values that form a stable compound, and (b) has a thickness between 20 and 65 angstroms. Other aspects are also provided.

Abstract: Pixel array structures to provide a ground contact for a CMOS pixel cell. In an embodiment, an active area of a pixel cell includes a photodiode disposed in a first portion of an active area, where a second portion of the active area extends from a side of the first portion. The second portion includes a doped region to provide a ground contact for the active area. In another embodiment, the pixel cell includes a transistor to transfer the charge from the photodiode, where a gate of the transistor is adjacent to the second portion and overlaps the side of the first portion.

Abstract: Methods of electrically programming a diffusion resistor by using trapped charge in a trapped charge region adjacent to the resistor to vary the resistance of the resistor, and the resistor, are disclosed. In one embodiment, a method includes forming a diffusion resistor in a substrate; forming a trapped charge region adjacent to the diffusion resistor; and adjusting a resistance of the diffusion resistor by controlling the trapped charge in the trapped charge region.

Abstract: Provided is a solid-state CMOS image sensor, specifically a CMOS image sensor pixel that has stacked photo-sites, high sensitivity, and low dark current. In an image sensor including an array of pixels, each pixel includes: a standard photo-sensing and charge storage region formed in a first region under a surface portion of a substrate and collecting photo-generated carriers; a second charge storage region formed adjacent to the surface portion of the substrate and separated from the standard photo-sensing and charge storage region; and a potential barrier formed between the first region and a second region underneath the first region and diverting the photo-generated carriers from the second region to the second charge storage region.

Abstract: Disclosed is a method for manufacturing a semiconductor device that can improve the performance of a photodiode that is formed on a same substrate as a thin film transistor without greatly deteriorating the productivity of the semiconductor device. On a glass substrate 30, a base layer 31 having a recess 33b on the surface is formed, and on the base layer 31, an amorphous silicon thin film 42 is formed. The amorphous silicon thin film 42 is melted to form a crystalline silicon thin film 43, while moving the molten silicon into the recess 33b. Of the silicon thin film 43, a silicon film 11 that constitutes a portion of a thin film transistor 10 is formed of the silicon thin film 43 in a part other than the recess 33b, while a silicon film 21 that constitutes a portion of a photodiode 20 is formed of the silicon thin film 43 in the recess 33b.

Abstract: Disclosed are embodiments of a semiconductor device comprising a semiconductor body with a semiconductor image sensor comprising a two-dimensional matrix of picture elements, each picture element comprising a radiation-sensitive element coupled to MOS field effect transistors for reading the radiation-sensitive elements, wherein a semiconductor region is sunken in the surface of the body having the same conductivity type as the body and having an increased doping concentration, the semiconductor region being disposed between the radiation-sensitive elements of neighboring picture elements.

Abstract: A CIS and a method of manufacturing the same, the CIS including a substrate having a first surface and second surface opposite thereto, the substrate including an APS array region including a photoelectric transformation element and a peripheral circuit region; an insulating interlayer on the first surface of the substrate and including metal wirings electrically connected to the photoelectric transformation element; a light blocking layer on the peripheral circuit region of the second surface of the substrate, exposing the APS array region, and including a plurality of metal wiring patterns spaced apart from one another to form at least one drainage path along a boundary region between the APS array region and the peripheral circuit region; a color filter layer on the second surface of the substrate covering the APS array region and the light blocking layer; and a microlens on the color filter layer on the APS array region.

Abstract: A photosite may include, in a semi-conductor substrate, a photodiode pinched in the direction of the depth of the substrate including a charge storage zone, and a charge transfer transistor to transfer the stored charge. The charge storage zone may include a pinching in a first direction passing through the charge transfer transistor defining a constriction zone adjacent to the charge transfer transistor.

Abstract: A spin-torque magnetoresistive memory element has a high magnetoresistance and low current density. A free magnetic layer is positioned between first and second spin polarizers. A first tunnel barrier is positioned between the first spin polarizer and the free magnetic layer and a second tunnel barrier is positioned between the second spin polarizer and the free magnetic layer. The magnetoresistance ratio of the second tunnel barrier has a value greater than double the magnetoresistance ratio of the first tunnel barrier.

Abstract: A semiconductor device may include active patterns of pillar-shapes disposed on a substrate and spaced apart from each other in one direction; a gate electrode extending in the one direction and overlapped with sidewalls of the active patterns; a gate insulating layer disposed between the gate electrode and the active patterns; bit lines connected to bottom surfaces of respective active patterns; and/or capacitors connected to top surfaces of the respective active patterns. Each of the active patterns may have no p-type/n-type (PN) junctions. A semiconductor device may include a substrate; active patterns on the substrate that are spaced apart from each other; a gate electrode configured to overlap sidewalls of the active patterns; and/or gate insulating layers between the gate electrode and respective active patterns. The active patterns may be doped with dopants of a same conductivity type.

Abstract: It is an object to provide a memory device where an area occupied by a memory cell is small, and moreover, a memory device where an area occupied by a memory cell is small and a data holding period is long. A memory device includes a bit line, a capacitor, a first insulating layer provided over the bit line and including a groove portion, a semiconductor layer, a second insulating layer in contact with the semiconductor layer, and a word line in contact with the second insulating layer. Part of the semiconductor layer is electrically connected to the bit line in a bottom portion of the groove portion, and another part of the semiconductor layer is electrically connected to one electrode of the capacitor in a top surface of the first insulating layer.

Abstract: Semiconductor devices include one or more transistors having a floating gate and a control gate. In at least one embodiment, the floating gate comprises an intermediate portion extending between two end portions. The intermediate portion has an average cross-sectional area less than one or both of the end portions. In some embodiments, the intermediate portion may comprise a single nanowire. In additional embodiments, semiconductor devices have one or more transistors having a control gate and a floating gate in which a surface of the control gate opposes a lateral side surface of a floating gate that defines a recess in the floating gate. Electronic systems include such semiconductor devices. Methods of forming semiconductor devices include, for example, forming a floating gate having an intermediate portion extending between two end portions, and configuring the intermediate portion to have an average cross-sectional area less than one or both of the end portions.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a semiconductor substrate, a gate insulating film formed on the semiconductor substrate, a floating gate electrode formed on the gate insulating film, made of polysilicon containing a p-type impurity as a group XIII element, and having a lower film and an upper film stacked on the lower film, an inter-electrode insulating film formed on the floating gate electrode, and a control gate electrode formed on the inter-electrode insulating film. One of a concentration and an activation concentration of the p-type impurity in the upper film is higher than one of a concentration and an activation concentration of the p-type impurity in the lower film.

Abstract: The flash memory cell comprises a sense transistor that has a pair of source/drain lines and a control gate. A coupling metal-insulator-metal capacitor is created between the floating gate and a read wordline. A tunneling metal-insulator-metal capacitor is created between the floating gate and a write/erase bit line. In one embodiment, the insulator is a metal oxide.

Abstract: Methods and apparatuses for electronic devices such as non-volatile memory devices are described. The memory devices include a multi-layer control dielectric, such as a double or triple layer. The multi-layer control dielectric includes a combination of high-k dielectric materials such as aluminum oxide, hafnium oxide, and/or hybrid films of hafnium aluminum oxide. The multi-layer control dielectric provides enhanced characteristics, including increased charge retention, enhanced memory program/erase window, improved reliability and stability, with feasibility for single or multi state (e.g., two, three or four bit) operation.

Abstract: The memory devices include a tunneling insulating layer disposed on a substrate, a charge storage layer disposed on the tunneling insulating layer, a blocking insulating layer disposed on the charge storage layer and a control gate electrode disposed on the blocking insulating layer. The control gate electrode may have an edge portion spaced farther apart from the blocking insulating layer than a central portion of the control gate electrode to concentrate charge density distribution on a central portion of a memory cell.

Abstract: Methods for fabricating an electronic device and electronic devices therefrom are provided. A method includes forming one or more masking layers on a semiconducting surface of a substrate and forming a plurality of dielectric isolation features and a plurality of fin-type projections using the masking layer. The method also includes processing the masking layers and the plurality of fin-type projections to provide an inverted T-shaped cross-section for the plurality of fin-type projections that includes a distal extension portion and a proximal base portion. The method further includes forming a plurality of bottom gate layers on the distal extension portion and forming a plurality of control gate layers on the plurality of dielectric isolation features and the plurality of bottom gate layers.

Abstract: A semiconductor structure includes a monolithically integrated trench FET and Schottky diode. The semiconductor structure further includes a plurality of trenches extending into a semiconductor region. A stack of gate and shield electrodes are disposed in each trench. Body regions extend over the semiconductor region between adjacent trenches, with a source region extending over each body region. A recess having tapered edges extends between every two adjacent trenches from upper corners of the two adjacent trenches through the body region and terminating in the semiconductor region below the body region. An interconnect layer extends into each recess to electrically contact tapered sidewalls of the source regions and the body regions, and to contact the semiconductor region along a bottom of each recess to form a Schottky contact therebetween.

Abstract: The disclosed recessed thyristor-based memory cell comprises in one embodiment a conductive plug recessed into the bulk of the substrate, which is coupled to or comprises the enable gate of the cell. Vertically disposed around this recessed gate is a thyristor, whose anode is connected to the bit line and cathode is connected to the word line. The disclosed cell comprises no other gate, such as an access transistor, and hence is essentially a one-transistor device. As facilitated by the vertical disposition of the thyristor, the disclosed cell takes up a small amount of area on an integrated circuit when compared to a traditional DRAM cell. The disclosed cell is simple to manufacture in its various embodiments, and is easy to configure into an array of cells. Isolation underneath the cell assists in improving the data retention of the cell and extends the time needed between cell refresh.

Abstract: According to one or more embodiments of the present invention, a power semiconductor device comprise a plurality of gate electrodes, first to third electrodes, and first to fifth semiconductor layers The second semiconductor layer is formed on the first semiconductor layer. A plurality of the third semiconductor layers are formed in the second semiconductor layer and arranged in a direction perpendicular to the stacking direction. The fourth semiconductor layer is formed on the second semiconductor layer. The fifth semiconductor layer is formed on the fourth semiconductor layer. The gate electrodes are formed above the second semiconductor layer and each gate electrode is arranged between the adjacent third semiconductor layers. The first electrodes are formed below the gate electrodes. One of the first electrodes is connected to the gate electrode. One of the first electrodes is connected to the third electrode.

Abstract: A semiconductor device includes a semiconductor substrate having a first gate groove having first and second side walls facing to each other. A first gate insulating film covers the first and second side walls. A first gate electrode is disposed on the first gate insulating film and in a lower portion of the first gate groove. A first burying insulating film buries the first gate groove and covers the first gate electrode. A first diffusion region is adjacent to a first upper portion of the first gate insulating film. The first upper portion is positioned on an upper portion of the first side wall of the first gate groove. A second diffusion region is in contact with an upper portion of the second side wall of the first gate groove.

Abstract: A double-gate vertical channel transistor (DGVC) structure is described which is particularly well suited for Dynamic RAM (DRAM) memory (e.g., capacitorless DRAM) wherein the memory cell occupies a small cell area of 4F2, and provides beneficial retention properties including immunity to disturbances. The vertical transistors are arranged in an alternating gate-facing orientation, with a common source formed on a first end and separate drains on their second ends. Word lines comprise alternating front gates and back gates shared by columns of gate-facing transistors on each side of it. The DGVC cell provides enhanced scalability allowing the continued scaling of DRAM technology and can be fabricated using low-cost semiconductor materials and existing fabrication techniques. Fabrication techniques and array biasing are also described for the DGVC cell arrays.

Abstract: A semiconductor device is provided. The semiconductor device includes a gate on a substrate, a source region at a first side of the gate, a first conductive type body region under the source region, a second conductive type drain region at a second side of the gate, a device isolation region in the substrate between the source region and the drain region and overlapping part of the gate, and a first buried layer extending in a direction from the source region to the drain region, the first buried layer under the body region, overlapping part of the device isolation region, and not overlapping the drain region.

Abstract: A semiconductor device includes a p-type semiconductor substrate, an n-type drift region formed in the p-type semiconductor substrate, and a p-type body region formed in the n-type drift region. A circular gate electrode is formed over a pn junction between sides of the p-type body region and the n-type drift region along the pn junction. An n-type drain region and an n-type source region are formed in the n-type drift region and the p-type body region, respectively, with a part of the gate electrode between.

Abstract: The present invention discloses a double diffused metal oxide semiconductor (DMOS) device and a manufacturing method thereof. The DMOS device is formed in a first conductive type substrate, and includes a second conductive type high voltage well, a field oxide region, a gate, a second conductive type source, a second conductive type drain, a first conductive type body region, and a first conductive type deep well. The deep well is formed beneath and adjacent to the high voltage well in a vertical direction. The deep well and the high voltage well are defined by a same lithography process step.

Abstract: A semiconductor device includes: a p-type active region; a gate electrode traversing the active region; an n-type LDD region having a first impurity concentration and formed from a drain side region to a region under the gate electrode; a p-type channel region having a second impurity concentration and formed from a source side region to a region under the gate electrode to form an overlap region with the LDD region under the gate electrode, the channel region being shallower than the LDD region; an n-type source region formed outside the gate electrode; and an n+-type drain region having a third impurity concentration higher than the first impurity concentration formed outside and spaced from the gate electrode, wherein an n-type effective impurity concentration of an intermediate region between the gate electrode and the n+-type drain region is higher than an n-type effective impurity concentration of the overlap region.

Abstract: In an LDMOS device leakage and forward conduction parameters are adjusted by integrating an Schottky diode into the LDMOS by substituting one or more n+ source regions with Schottky diodes.

Abstract: The present disclosure discloses a lateral high-voltage transistor and associated method for making the same.

Abstract: The present invention discloses a double diffused drain metal oxide semiconductor (DDDMOS) device and a manufacturing method thereof. The DDDMOS device is formed in a substrate, and includes a first well, a gate, a diffusion region, a source, and a drain. A low voltage device is also formed in the substrate, which includes a second well and a lightly doped drain (LDD) region, wherein the first well and the diffusion region are formed by process steps which also form the second well and the LDD region in the low voltage device, respectively.

Abstract: A method produces a semiconductor device including a semiconductor body, an electrode thereon, and an insulating structure insulating the electrode from the semiconductor body. The semiconductor body includes a first contact region of a first conductivity type, a body region of a second conductivity type, a drift region of the first conductivity type, and a second contact region having a higher maximum doping concentration than the drift region. The insulating structure includes a gate dielectric portion forming a first horizontal interface. with the drift region and has a first maximum vertical extension A field dielectric portion forms with the drift region second and third horizontal interfaces arranged below the main surface. A second maximum vertical extension of the field dielectric portion is larger than the first maximum vertical extension. A third maximum vertical extension of the field dielectric portion is larger than the second maximum vertical extension.

Abstract: A CMOS chip comprising a high performance device region and a high density device region includes a plurality of high performance devices comprising n-type field effect transistors (NFETs) and p-type field effect transistors (PFETs) in the high performance device region, wherein the high performance devices have a high performance pitch; and a plurality of high density devices comprising NFETs and PFETs in the high density device region, wherein the high density devices have a high density pitch, and wherein the high performance pitch is about 2 to 3 times the high density pitch; wherein the high performance device region comprises doped source and drain regions, NFET gate regions having an elevated stress induced using stress memorization technique (SMT), gate silicide and source/drain silicide regions, and a dual stressed liner, and wherein the high density device region comprises doped source and drain regions, gate silicide regions, and a neutral stressed liner.

Abstract: A system and method for electrostatic discharge protection. The system includes a plurality of transistors. The plurality of transistors includes a plurality of gate regions, a plurality of source regions, and a plurality of drain regions. The plurality of source regions and the plurality of drain regions are located within an active area in a substrate, and the active area is adjacent to at least an isolation region in the substrate. Additionally, the system includes a polysilicon region. The polysilicon region is separated from the substrate by a dielectric layer, and the polysilicon region intersects each of the plurality of gate regions. At least a part of the polysilicon region is on the active area.

Abstract: Structures and methods are provided for nanosecond electrical pulse anneal processes. The method of forming an electrostatic discharge (ESD) N+/P+ structure includes forming an N+ diffusion on a substrate and a P+ diffusion on the substrate. The P+ diffusion is in electrical contact with the N+ diffusion. The method further includes forming a device between the N+ diffusion and the P+ diffusion. A method of annealing a structure or material includes applying an electrical pulse across an electrostatic discharge (ESD) N+/P+ structure for a plurality of nanoseconds.