Abstract: Several embodiments of light emitting diode packaging configurations including a substrate with a cavity are disclosed herein. In one embodiment, a cavity is formed on a substrate to contain an LED and phosphor layer. The substrate has a channel separating the substrate into a first portion containing the cavity and a second portion. A filler of encapsulant material or other electrically insulating material is molded in the channel. The first portion can serve as a cathode for the LED and the second portion can serve as the anode.

Abstract: An optical emitter includes a Light-Emitting Diode (LED) on a package wafer, transparent insulators, and one or more transparent electrical connectors between the LED die and one or more contact pads on the packaging wafer. The transparent insulators are deposited on the package wafer with LED dies attached using a lithography or a screen printing method. The transparent electrical connectors are deposited using physical vapor deposition, chemical vapor deposition, spin coating, spray coating, or screen printing and may be patterned using a lithography process and etching.

Abstract: A method of manufacturing a light-emitting device comprising the steps of cutting a substrate by a laser beam to form a cavity in the substrate and generate a by-product directly on the substrate by the cutting, and removing the by-product by a chemical solution containing an acid under a predetermined cleaning temperature.

Abstract: It is an object to provide a gas sensor which is formed by a simple manufacturing process. Another object is to provide a gas sensor whose manufacturing cost is reduced. A transistor which includes an oxide semiconductor layer in contact with a gas and which serves as a detector element of a gas sensor, and a transistor which includes an oxide semiconductor layer in contact with a film having a gas barrier property and which forms a detection circuit are formed over one substrate by the same process, whereby a gas sensor using these transistors may be formed.

Abstract: A method is disclosed for fabricating optoelectronic component structures and traditional circuit elements on a single silicon substrate. Specific examples of optoelectronic components include, but are not limited to: photodiode structures, light emitter structures and waveguide structures. Traditional circuit elements include transistors, diodes, resistors, capacitors and associated metalized interconnects. The method of fabrication is compatible with traditional CMOS, Bi-CMOS and Bipolar processing requirements and design rules.

Abstract: The present application is a photodiode detector array for use in computerized tomography (CT) and non-CT applications. Specifically, the present application is a high-density photodiode arrays, with low dark current, low capacitance, high signal to noise ratio, high speed, and low crosstalk that can be fabricated on relatively large substrate wafers. More specifically the photodiode array of the present application is fabricated such that the PN-junctions are located on both the front side and back side surfaces of the array, and wherein the front side PN-junction is in electrical communication with the back side PN-junction. Still more specifically, the present application is a photodiode array having PN-junctions that are electrically connected from the front to back surfaces and which can be operated in a fully depleted mode at low reverse bias.

Abstract: A method of hybrid stacked Chip for a solar cell onto which semiconductor layers of different materials is provided by stacking tunnel layer and bumps in order to solve the problem of lattices mismatch between the layers for further increasing of the efficiency of solar cell. Electric charges (i.e., current) generated by respective solar cells can be outputted by means of contacts. Further total power P is defined by a summation of powers of respective solar cells, i.e., V1I1+V2I2+ . . . VnIn. This is a great increase in comparison with the power of conventional solar cells connected in series.

Abstract: A method and apparatus to manage the diffusion process by controlling the diffusion path in the semiconductor fabrication process is disclosed. In one embodiment, a method for processing a substrate comprising steps of forming one or more diffusion areas on said substrate; disposing the substrate in a diffusion chamber, wherein the diffusion chamber is under a vacuum condition and a source material therein is heated and evaporated; and diffusing the source material into the diffusion area on said substrate, wherein said source material travels through a diffusion controlling unit adapted to manage the flux thereof in the diffusion chamber, so concentration of the source material is uniform in a diffusion region above the substrate.

Abstract: A method of manufacturing an organic semiconductor thin film includes coating an organic semiconductor solution on a substrate, and shearing the organic semiconductor solution in a direction that results in a shearing stress being applied to the organic semiconductor solution to form the organic semiconductor thin film, wherein a speed of the shearing is controlled such that an intermolecular distance of the organic semiconductor solution is adjusted.

Abstract: A thin film transistor panel includes a substrate, a light blocking layer on the substrate, a first protective film on the light blocking layer, a first electrode and a second electrode on the first protective film, an oxide semiconductor layer on a portion of the first protective film exposed between the first electrode and the second electrode, an insulating layer, a third electrode overlapping with the oxide semiconductor layer and on the insulating layer, and a fourth electrode on the insulating layer. The light blocking layer includes first sidewalls, and the first protective film includes second sidewalls. The first and the second sidewalls are disposed along substantially the same line.

Abstract: Electronic assemblies including substrates and their manufacture are described. One assembly includes a die embedded in a dielectric layer in a multilayer substrate, and a dielectric region embedded in the dielectric layer in the multilayer substrate. The multilayer substrate includes a die side and a land side, with the first dielectric region and the dielectric layer extending to the die side. A plurality of vias are positioned within the first dielectric region, the vias extending to pads on the die side. Other embodiments are described and claimed.

Abstract: Provided is a semiconductor device with a semiconductor chip mounted on a small-sized package substrate that includes a slot, a large number of external connection terminals, and bonding fingers. The bonding fingers are connected to the external connection terminals. The bonding fingers constitute a bonding finger arrangement in a central section and end sections of a bonding finger area along each longer side of the slot. The arrangement includes a first bonding finger array, which is located at a close distance from each longer side of the slot, and a second array, which is located at a farther distance than the distance of the first bonding finger array from each longer side of the slot. The central section of the bonding finger area includes the second bonding finger array, and the end sections of the bonding finger area include the first bonding finger array.

Abstract: A semiconductor device includes a semiconductor chip, a connection electrode including a first land electrode electrically coupled with the semiconductor chip, and a through electrode formed on an upper surface of the first land electrode to be electrically coupled with the first land electrode using a stud bump, and a sealing resin, through which the connection electrode passes, for sealing the semiconductor chip.

Abstract: Disclosed are an active layer ion implantation method and an active layer ion implantation method for thin-film transistor. The active layer ion implantation method comprises: applying a photoresist on the active layer; and implanting ions into the active layer through the photoresist.

Abstract: A first patterned contact layer, for example a gate electrode, is formed over an insulative substrate. Insulating and functional layers are formed at least over the first patterned contact layer. A second patterned contact layer, for example source/drain electrodes, is formed over the functional layer. Insulative material is then selectively deposited over at least a portion of the second patterned contact layer to form first and second wall structures such that at least a portion of the second patterned contact layer is exposed, the first and second wall structures defining a well therebetween. Electrically conductive or semiconductive material is deposited within the well, for example by jet-printing, such that the first and second wall structures confine the conductive or semiconductive material and prevent spreading and electrical shorting to adjacent devices. The conductive or semiconductive material is in electrical contact with the exposed portion of the second patterned contact layer to form, e.g.

Abstract: A method for making an electronic device, such as a MOS transistor, including the steps of forming a plurality of semiconductor islands on an electrically functional substrate, printing a first dielectric layer on or over a first subset of the semiconductor islands and optionally a second dielectric layer on or over a second subset of the semiconductor islands, and annealing. The first dielectric layer contains a first dopant, and the (optional) second dielectric layer contains a second dopant different from the first dopant. The dielectric layer(s), semiconductor islands and substrate are annealed sufficiently to diffuse the first dopant into the first subset of semiconductor islands and, when present, the second dopant into the second subset of semiconductor islands.

Abstract: An enhancement-mode GaN MOSFET with a low leakage current and an improved reliability is formed by utilizing a SiO2/Si3N4 gate insulation layer on an AlGaN (or InAlGaN) barrier layer. The Si3N4 portion of the SiO2/Si3N4 gate insulation layer significantly reduces the formation of interface states at the junction between the gate insulation layer and the barrier layer, while the SiO2 portion of the SiO2/Si3N4 gate insulation layer significantly reduces the leakage current.

Abstract: A device and method for fabrication includes providing a first substrate assembly including a first substrate and a first metal layer formed on the first substrate and a second substrate assembly including a second substrate and a second metal layer formed on the second substrate. The first metal layer is joined to the second metal layer using a cold welding process wherein one of the first substrate and the second substrate includes a semiconductor channel layer for forming a transistor device.

Abstract: A through silicon via structure and a method of fabricating the through silicon via. The method includes: (a) forming a trench in a silicon substrate, the trench open to a top surface of the substrate; (b) forming a silicon dioxide layer on sidewalls of the trench, the silicon dioxide layer not filling the trench; (c) filling remaining space in the trench with polysilicon; after (c), (d) fabricating at least a portion of a CMOS device in the substrate; (e) removing the polysilicon from the trench, the dielectric layer remaining on the sidewalls of the trench; (f) re-filling the trench with an electrically conductive core; and after (f), (g) forming one or more wiring layers over the top surface of the substrate, a wire of a wiring level of the one or more wiring levels closest to the substrate contacting a top surface of the conductive core.

Abstract: A semiconductor structure includes a semiconductor substrate, and an NMOS device at a surface of the semiconductor substrate, wherein the NMOS device comprises a Schottky source/drain extension region. The semiconductor structure further includes a PMOS device at the surface of the semiconductor substrate, wherein the PMOS device comprises a source/drain extension region comprising only non-metal materials. Schottky source/drain extension regions may be formed for both PMOS and NMOS devices, wherein the Schottky barrier height of the PMOS device is reduced by forming the PMOS device over a semiconductor layer having a low valence band.

Abstract: A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate including a metal oxide device. The metal oxide device includes first and second doped regions disposed within the substrate and interfacing in a channel region. The first and second doped regions are doped with a first type dopant. The first doped region has a different concentration of dopant than the second doped region. The metal oxide device further includes a gate structure traversing the channel region and the interface of the first and second doped regions and separating source and drain regions. The source region is formed within the first doped region and the drain region is formed within the second doped region. The source and drain regions are doped with a second type dopant. The second type dopant is opposite of the first type dopant.

Abstract: An electronic component includes a depletion-mode transistor, an enhancement-mode transistor, and a resistor. The depletion-mode transistor has a higher breakdown voltage than the enhancement-mode transistor. A first terminal of the resistor is electrically connected to a source of the enhancement-mode transistor, and a second terminal of the resistor and a source of the depletion-mode transistor are each electrically connected to a drain of the enhancement-mode transistor. A gate of the depletion-mode transistor can be electrically connected to a source of the enhancement-mode transistor.

Abstract: A method of forming a semiconductor memory cell that includes forming the floating and control gates from the same poly layer. Layers of insulation, conductive and second insulation material are formed over a substrate. A trench is formed in the second insulation material extending down to and exposing the conductive layer. Spacers are formed in the trench, separated by a small and defined gap at a bottom of the trench that exposes a portion of the conductive layer. A trench is then formed through the exposed portion of the conductive layer by performing an anisotropic etch through the gap. The trench is filled with third insulation material. Selected portions of the conductive layer are removed, leaving two blocks thereof separated by the third insulation material.

Abstract: Provided are three-dimensional semiconductor devices. A device includes an electrode structure including conductive patterns sequentially stacked on a substrate, a semiconductor pattern penetrating the electrode structure and including channel regions adjacent to the conductive patterns and vertical adjacent regions between the channel regions, and a semiconductor connecting layer extending from an outer sidewall of the semiconductor pattern to connect the semiconductor pattern to the substrate.

Abstract: A fabricating method of a trench-gate metal oxide semiconductor device is provided. The fabricating method includes the steps of defining a first zone and a second zone in a substrate, forming at least one first trench in the second zone, forming a dielectric layer on the first zone and the second zone, filling the dielectric layer in the first trench, performing an etching process to form at least one second trench in the first zone by using the dielectric layer as an etching mask, forming a first gate dielectric layer on a sidewall of the second trench, and filling a conducting material layer into the second trench, thereby forming a first gate electrode.

Abstract: Embodiments of the present invention provide a method of forming contact structure for transistor. The method includes providing a semiconductor substrate having a first and a second gate structure of a first and a second transistor formed on top thereof, the first and second gate structures being embedded in a first inter-layer-dielectric (ILD) layer; epitaxially forming a first semiconductor region between the first and second gate structures inside the first ILD layer; epitaxially forming a second semiconductor region on top of the first semiconductor region, the second semiconductor region being inside a second ILD layer on top of the first ILD layer and having a width wider than a width of the first semiconductor region; and forming a silicide in a top portion of the second semiconductor region.

Abstract: According to one embodiment, an alignment measurement system is configured to measure a position of a mark having the highest identifiability of a plurality of marks formed in a substrate. The plurality of marks are made of mutually different patterns. A device pattern is formed in the substrate using directed self-assembly after the plurality of marks is formed.

Abstract: Provided is an apparatus that includes an integrated circuit located in a first region of a substrate having first and second opposing major surfaces and an alignment mark located in a second region of the substrate and extending through the substrate between the first and second surfaces.

Abstract: A manufacturing method for a shallow trench isolation. First, a substrate is provided, a hard mask layer and a patterned photoresist layer are sequentially formed on the substrate, at least one trench is then formed in the substrate through an etching process, the hard mask layer is removed. Afterwards, a filler is formed at least in the trench and a planarization process is then performed on the filler. Since the planarization process is performed only on the filler, so the dishing phenomenon can effectively be avoided.

Abstract: The present invention provides a method for dicing a substrate with back metal, the method comprising the following steps. The substrate is provided with a first surface and a second surface wherein the second surface is opposed to the first surface. A mask layer is provided on the first surface of the substrate and a thin film layer is provided on the second surface of the substrate. The first surface of the substrate is diced through the mask layer to expose the thin film layer on the second surface of the substrate. A fluid from a fluid jet is applied to the thin film layer on the second surface of the substrate after the thin film layer has been exposed by the dicing step.

Abstract: A wafer processing method of dividing a wafer along a plurality of crossing streets formed on the wafer to obtain individual chips. The wafer processing method includes a modified layer forming step of applying a laser beam having a transmission wavelength to the wafer along each street to thereby form a modified layer inside the wafer and a dividing step of applying an external force to the wafer to thereby divide the wafer into the individual chips along each street with the modified layer functioning as a division start point. In the modified layer forming step, the modified layer is formed at each intersection of the crossing streets at a height where cracking can be avoided on the corner edges of each chip obtained by dividing the wafer.

Abstract: Some embodiments of the present invention relate to a semiconductor device and a method of manufacturing a semiconductor device capable of preventing the deterioration of electrical characteristics. A p-type collector region is provided on a surface layer of a backside surface of an n-type drift region. A p+-type isolation layer for obtaining reverse blocking capability is provided at the end of an element. In addition, a concave portion is provided so as to extend from the backside surface of the n-type drift region to the p+-type isolation layer. A p-type region is provided and is electrically connected to the p+-type isolation layer. The p+-type isolation layer is provided so as to include a cleavage plane having the boundary between the bottom and the side wall of the concave portion as one side.

Abstract: A method of fabricating a graphene oxide material in which oxidation is confined within the graphene layer and that possesses a desired band gap is provided. The method allows specific band gap values to be developed. Additionally, the use of masks is consistent with the method, so intricate configurations can be achieved. The resulting graphene oxide material is thus completely customizable and can be adapted to a plethora of useful engineering applications.

Abstract: A method for making an epitaxial structure is provided. The method includes the following steps. A substrate having an epitaxial growth surface is provided. A buffer layer is formed on the epitaxial growth surface. A carbon nanotube layer is placed on the buffer layer. An epitaxial layer is epitaxially grown on the buffer layer. The substrate and the carbon nanotube layer are removed.

Abstract: A fabricating method of a semiconductor chip includes the following steps. Firstly, a substrate is provided, wherein an amorphous semiconductor layer is formed in a first surface of the substrate. Then, a first metal layer is formed on the amorphous semiconductor layer. Then, a thermal-treating process is performed to result in a chemical reaction between the first metal layer and a part of the amorphous semiconductor layer, thereby producing an amorphous metal semiconductor compound layer. Afterwards, a microwave annealing process is performed to recrystallize the amorphous metal semiconductor compound layer as a polycrystalline metal semiconductor compound layer.

Abstract: Disclosed is a plasma doping apparatus including a processing chamber, a substrate holding unit, a plasma generating mechanism, a pressure control mechanism, a bias power supply mechanism, and a control unit. The control unit controls the pressure within the processing chamber to be a first pressure and controls the bias power to be supplied to the holding unit is to be a first bias power for a first plasma process. The control unit also controls the pressure within the processing chamber to be a second pressure which is higher than the first pressure, and controls the bias power to be supplied to the holding unit to be a second bias power which is lower than the first bias power for a second plasma process.

Abstract: A method for processing a semiconductor assembly is presented. The method includes: (a) contacting at least a portion of a semiconductor assembly with a chalcogen source, wherein the semiconductor assembly comprises a semiconductor layer comprising a semiconductor material disposed on a support; (b) introducing a chalcogen from the chalcogen source into at least a portion of the semiconductor material; and (c) disposing a window layer on the semiconductor layer after the step (b).

Abstract: An integrated circuit and a method of formation provide a contact area formed at an angled end of at least one linearly extending conductive line. In an embodiment, conductive lines with contact landing pads are formed by patterning lines in a mask material, cutting at least one of the material lines to form an angle relative to the extending direction of the material lines, forming extensions from the angled end faces of the mask material, and patterning an underlying conductor by etching using said material lines and extension as a mask. In another embodiment, at least one conductive line is cut at an angle relative to the extending direction of the conductive line to produce an angled end face, and an electrical contact landing pad is formed in contact with the angled end face.

Abstract: Provided is a method of forming a gate insulating film for use in a MOSFET for a power device. An AlN film is formed on a SiC substrate of a wafer W and then the formation of an AlO film and the formation of an AlN film on the formed AlO film are repeated, thereby forming an AlON film having a laminated structure in which AlO films and AlN films are alternately laminated. A heat treatment is performed on the AlON film having the laminated structure.

Abstract: An integrated circuit containing a vertical interconnect that includes a region of interconnect metal continuously surrounding one or more dielectric pillars. The vertical interconnect electrically contacts a top surface of a lower conductive structure. An upper conductive structure contacts a top surface of the vertical interconnect. A process of forming an integrated circuit that includes forming a vertical interconnect that has a region of interconnect metal continuously surrounding one or more dielectric pillars. The vertical interconnect electrically contacts a top surface of a lower conductive structure, and an upper conductive structure contacts a top surface of the vertical interconnect.

Abstract: A method includes forming a connection between a first metal layer and a second metal layer. The second metal layer is over the first metal layer. A via location for a first via between the first metal layer and the second metal layer is identified. Additional locations for first additional vias are determined. The first additional vias are determined to be necessary for stress migration issues. Additional locations necessary for second additional vias are determined. The second additional vias are determined to be necessary for electromigration issues. The first via and the one of the group consisting of (i) the first additional vias and second additional vias (ii) the first additional vias plus a number of vias sufficient for electromigration issues taking into account that the first additional vias, after taking into account the stress migration issues, still have an effective via number greater than zero.

Abstract: A first wiring part has an intermediate layer made of a material different from materials of a first insulator layer and a first conductor layer and located between the first insulator layer and the first conductor layer. In a step of forming a first hole, which penetrates through a first element part and the first insulator layer, from a side of a first semiconductor layer toward the first conductor layer, and forming a second hole, which penetrates through the first element part, the first wiring part, and a second insulator layer, from the side toward the second conductor layer, an etching condition of the first insulator layer when the first hole is formed is that an etching rate for the material of the first insulator layer under the etching condition is higher than an etching rate for the material of the intermediate layer under the etching condition.

Abstract: According to one embodiment, a method for generating mask data is configured to form a circuit pattern on a substrate using a directed self-assembly material. The method includes extracting a first region, setting a second region and setting a third region. The first region does not existing in the circuit pattern and existing in an initial pattern. The initial pattern includes a plurality of interconnect patterns extending in a first direction. The second region is formed by elongating the first region in a second direction intersecting the first direction. The second region straddles the first region in the second direction. The third region includes at least one of the second regions. The directed self-assembly material is disposed in the third region.

Abstract: A polishing agent for polishing a non-oxide single-crystal substrate such as a silicon carbide single-crystal substrate with a high polishing rate to obtain a smooth surface is provided. This polishing agent comprises an oxidant having redox potential of 0.5 V or more and containing a transition metal, silicon oxide particles, cerium oxide particles and a dispersion medium, in which a mass ratio of the silicon oxide particles to the cerium oxide particles is from 0.2 to 20.

Abstract: A polishing composition of the present invention contains a water-soluble polymer having a hydrophilic group, and abrasive grains. A hydrophobic silicon-containing part after being polished with the polishing composition has a water contact angle lower than that of the hydrophobic silicon-containing part after being polished with another composition having the same makeup as the polishing composition except that the water-soluble polymer is not contained therein. Examples of the water-soluble polymer include polysaccharides and alcohol compounds. Another polishing composition of the present invention contains abrasive grains having a silanol group, and a water-soluble polymer. When this polishing composition is left to stand for one day in an environment at a temperature of 25° C., the water-soluble polymer is adsorbed on the abrasive grains at 5,000 or more molecules per 1 ?m2 of surface area of the abrasive grains.

Abstract: A pattern forming method includes forming a pattern forming material film on a substrate as an etching target film, the pattern forming material film having an exposing section that has porosity upon exposure and a non-exposing section, patterning and exposing the pattern forming material film for the exposing section to have the porosity, selectively infiltrating a filling material into voids of the exposing section to reinforce the exposing section, and removing the non-exposing section of the pattern forming material film by dry etching to form a predetermined pattern.

Abstract: Techniques, systems, and apparatuses for performing carbon gap-fill in semiconductor wafers are provided. The techniques may include performing deposition-etching operations in a cyclic fashion to fill a gap feature with carbon. A plurality of such deposition-etching cycles may be performed, resulting in a localized build-up of carbon film on the top surface of the semiconductor wafer near the gap feature. An ashing operation may then be performed to preferentially remove the built-up material from the top surface of the semiconductor wafer. Further groups of deposition-etching cycles may then be performed, interspersed with further ashing cycles.

Abstract: Methods for processing a substrate are described herein. Methods can include positioning a substrate comprising silicon in a processing chamber, delivering a plasma to the surface of the substrate while biasing the substrate, exposing the surface of the substrate to ammonium fluoride (NH4F), and annealing the substrate to a first temperature to sublimate one or more volatile byproducts.

Abstract: A method for combinatorially processing a substrate is provided. The method includes introducing a first etchant into a reactor cell and introducing a fluid into the reactor cell while the first etchant remains in the reactor cell. After initiating the introducing the fluid, contents of the reactor cell are removed through a first removal line and a second removal line, wherein the first removal line extends farther into the reactor cell than the second removal line. A level of the fluid above an inlet to the first removal line is maintained while removing the contents. A second etchant is introduced into the reactor cell while removing the contents through the first removal line and the second removal line. The method includes continuing the introducing of the second etchant until a concentration of the second etchant is at a desired level, wherein the surface of the substrate remains submerged.

Abstract: The present invention provides methods and apparatuses for improving adhesion of dielectric and conductive layers on a substrate to the underlying layer. The methods involve passing a process gas through a plasma generator downstream of the substrate to create reactive species. The underlying layer is then exposed to reactive species that interact with the film surface without undesirable sputtering. The gas is selected such that the interaction of the reactive species with the underlying layer modifies the surface of the layer in a manner that improves adhesion to the subsequently formed overlying layer. During exposure to the reactive species, the substrate and/or process gas may be exposed to ultraviolet radiation to enhance surface modification. In certain embodiments, a single UV cure tool is used to cure the underlying film and improve adhesion.