Abstract: Semiconductor dies are mounted on a heat sink array frame structure. The heat sink array frame structure and the semiconductor dies are assembled together with an insulating substrate that has a corresponding array of apertures on an adhesive tape. The semiconductor dies are connected electrically with electrical contacts on the insulating substrate. The semiconductor dies, heat sinks and electrical connections to the contacts are encapsulated with a mold compound and then the encapsulated array is de-taped and singulated.

Abstract: A method of forming a plurality of bump structures on a substrate includes forming an under bump metallurgy (UBM) layer on the substrate, wherein the UBM layer contacts metal pads on the substrate. The method further includes forming a photoresist layer over the UBM layer, wherein the photoresist layer defines openings for forming the plurality of bump structures. The method further includes plating a plurality of layers in the openings, wherein the metal layers are part of the plurality of bump structures. The method further includes planarizing the plurality of bump structures after the metal layers are plated to a targeted height from a surface of the substrate.

Abstract: A method of fabricating a semiconductor package is provided, including providing an interposer having a plurality of conductive elements, disposing the interposer on a carrier having a plurality of recessed portions for the conductive elements to be received therein such that the interposer is coupled to the carrier, attaching the semiconductor element to the interposer, and removing the carrier. Coupling the interposer to the carrier prevents the conductive elements from displacement under pressure. Therefore, the conductive elements will not be in poor or no electrical contact with the interposer.

Abstract: A method includes the operations performing a first anisotropic etching process to remove a portion of the metal sheet from a top surface of the metal sheet, thereby forming a plurality of first recesses in the metal sheet; mounting a carrier on the top surface of the metal sheet, covering the first recesses; performing a second anisotropic etching process to remove a portion of the metal sheet under the first recesses from the bottom surface of the metal sheet; filling a molding material from the bottom surface of the metal sheet, leaving the bottom surface of the metal sheet exposed; forming a passivation layer on the top surface of the metal sheet, having a plurality of openings therethrough; forming a plurality of first metal vias through the opening; and forming a solder mask layer on the passivation layer, leaving the first metal vias exposed.

Abstract: A package includes a die, an encapsulant, and a capacitor. The package has a package first side and a package second side. The die has a die first side corresponding to the package first side, and has a die second side corresponding to the package second side. The die first side is opposite the die second side. The encapsulant surrounds the die. The capacitor includes a first plate and a second plate in the encapsulant, and opposing surfaces of the first plate and the second plate extend in a direction from the package first side to the package second side. The external conductive connectors are attached to at least one of the package first side and the package second side.

Abstract: Device structures and design structures for a silicon controlled rectifier, as well as methods for fabricating a silicon controlled rectifier. The device structure includes first and second layers of different materials disposed on a top surface of a device region containing first and second p-n junctions of the silicon controlled rectifier. The first layer is laterally positioned on the top surface in vertical alignment with the first p-n junction. The second layer is laterally positioned on the top surface of the device region in vertical alignment with the second p-n junction. The material comprising the second layer has a higher electrical resistivity than the material comprising the first layer.

Abstract: A miniaturized transistor is provided with high yield. Further, a semiconductor device which has high on-state characteristics and which is capable of high-speed response and high-speed operation is provided. In the semiconductor device, an oxide semiconductor layer, a gate insulating layer, a gate electrode layer, an insulating layer, a conductive film, and an interlayer insulating layer are stacked in this order. A source electrode layer and a drain electrode layer are formed in a self-aligned manner by cutting the conductive film so that the conductive film over the gate electrode layer and the conductive layer is removed and the conductive film is divided. An electrode layer which is in contact with the oxide semiconductor layer and overlaps with a region in contact with the source electrode layer and the drain electrode layer is provided.

Abstract: A lateral bipolar junction transistor includes an emitter region; a base region surrounding the emitter region; a gate disposed at least over a portion of the base region; and a collector region surrounding the base region; wherein the portion of the base region under the gate does not under go a threshold voltage implant process.

Abstract: A semiconductor structure is provided, which includes multiple sections arranged along a longitudinal axis. Preferably, the semiconductor structure comprises a middle section and two terminal sections located at opposite ends of the middle section. A semiconductor core having a first dopant concentration preferably extends along the longitudinal axis through the middle section and the two terminal sections. A semiconductor shell having a second, higher dopant concentration preferably encircles a portion of the semiconductor core at the two terminal sections, but not at the middle section, of the semiconductor structure. It is particularly preferred that the semiconductor structure is a nanostructure having a cross-sectional dimension of not more than 100 nm.

Abstract: The semiconductor-on-insulator substrate includes a support, an electrically insulating film, a crystalline film made from semiconductor material, and a protection layer. Germanium ions are implanted in the semiconductor material film through the protection layer so as to form an amorphized area in contact with the protection layer and a crystalline area in contact with the electrically insulating film. The semiconductor material film is annealed so as to recrystallize the amorphized area from the crystalline area.

Abstract: A method of fabricating a fin field effect transistor may include forming a fin portion protruding from a substrate, forming a device isolation layer to cover a lower sidewall of the fin portion, forming a semiconductor layer using an epitaxial method to cover an upper sidewall and a top surface of the fin portion, selectively etching an upper portion of the device isolation layer to form a gap region between a top surface of the device isolation layer and a bottom surface of the semiconductor layer, and forming a gate electrode pattern on the semiconductor layer to fill the gap region. Related devices are also described.

Abstract: A method for fabricating at least one cell of a semiconducting component includes positioning a first conducting polysilicon-type layer on a substrate, above an insulating oxide-type layer. The production of at least one trench within the first conducting layer is included to form two electrically unlinked distinct conducting parts intended to form two transistor gates of respectively two distinct twin cells.

Abstract: A semiconductor device which includes an oxide semiconductor layer, a source electrode and a drain electrode electrically connected to the oxide semiconductor layer, a gate insulating layer covering the oxide semiconductor layer, the source electrode, and the drain electrode, and a gate electrode over the gate insulating layer is provided. The thickness of the oxide semiconductor layer is greater than or equal to 1 nm and less than or equal to 10 nm. The gate insulating layer satisfies a relation where ?r/d is greater than or equal to 0.08 (nm?1) and less than or equal to 7.9 (nm?1) when the relative permittivity of a material used for the gate insulating layer is ?r and the thickness of the gate insulating layer is d. The distance between the source electrode and the drain electrode is greater than or equal to 10 nm and less than or equal to 1 ?m.

Abstract: A semiconductor device may include a through substrate via (TSV) conductive structure that may extend vertically through two or more layers of the semiconductor device. The TSV conductive structure may be coupled to a first voltage supply. The semiconductor device may include substrate layer. The substrate layer may include a first dopant region and a second dopant region. The first dopant region may be coupled to a second voltage supply. The second dopant region may be in electrical communication with the TSV conductive structure. The semiconductor device may include a first metal layer and a first insulator layer disposed between the substrate layer and the first metal layer. The first metal layer may laterally contact the TSV conductive structure. The first and second voltage supply may be adapted to create a capacitance at a junction between the first dopant region and the second dopant region.

Abstract: A method of forming a memory device. The method provides a semiconductor substrate having a surface region. A first dielectric layer is formed overlying the surface region of the semiconductor substrate. A bottom wiring structure is formed overlying the first dielectric layer and a second dielectric material is formed overlying the top wiring structure. A bottom metal barrier material is formed to provide a metal-to-metal contact with the bottom wiring structure. The method forms a pillar structure by patterning and etching a material stack including the bottom metal barrier material, a contact material, a switching material, a conductive material, and a top barrier material. The pillar structure maintains a metal-to-metal contact with the bottom wiring structure regardless of the alignment of the pillar structure with the bottom wiring structure during etching. A top wiring structure is formed overlying the pillar structure at an angle to the bottom wiring structure.

Abstract: Photonic SOI devices are formed by lateral epitaxy of a deposited non-crystalline semiconductor layer over a localized buried oxide created by a trench isolation process or by thermal oxidation. Specifically, and after forming a trench into a semiconductor substrate, the trench can be filled with an oxide by a deposition process or a thermal oxidation can be performed to form a localized buried oxide within the semiconductor substrate. In some embodiments, the oxide can be recessed to expose sidewall surfaces of the semiconductor substrate. Next, a non-crystalline semiconductor layer is formed and then a solid state crystallization is preformed which forms a localized semiconductor-on-insulator layer. During the solid state crystallization process portions of the non-crystalline semiconductor layer that are adjacent exposed sidewall surfaces of the substrate are crystallized.

Abstract: Photonic devices are created by laterally growing a semiconductor material (i.e., a localized semiconductor-on-insulator layer) over a localized buried oxide (BOX) created in a semiconductor by either a trench isolation process or thermal oxidation. In one embodiment, and after trench formation in a semiconductor substrate, the trench is filled with oxide to create a localized BOX. The top surface of the BOX is recessed to depth below the topmost surface of the semiconductor substrate to expose sidewall surfaces of the semiconductor substrate within each trench. A semiconductor material is then epitaxially grown from the exposed sidewall surfaces of the semiconductor substrate.

Abstract: A system and method for forming an isolation trench is provided. An embodiment comprises forming a trench and then lining the trench with a dielectric liner. Prior to etching the dielectric liner, an outgassing process is utilized to remove any residual precursor material that may be left over from the deposition of the dielectric liner. After the outgas sing process, the dielectric liner may be etched, and the trench may be filled with a dielectric material.

Abstract: In one embodiment, die are singulated from a wafer having a back layer by placing the wafer onto a first carrier substrate with the back layer adjacent the carrier substrate, forming singulation lines through the wafer to expose the back layer within the singulation lines, and using a mechanical device to apply localized pressure to the wafer to separate the back layer in the singulation lines. The localized pressure can be applied through the first carrier substrate proximate to the back layer, or can be applied through a second carrier substrate attached to a front side of the wafer opposite to the back layer.

Abstract: A support disk fixing apparatus which includes an upper surface to which a wafer is bonded, a lower surface, a cylindrical side surface between the upper surface and the lower surface, and a chamfered portion between the upper surface and the side surface, includes a base upon which the support disk is placed; and a fixture that is provided on the base, and that has a first surface that abuts against the side surface of the support disk and covers the side surface of the support disk, and a second surface that abuts against the chamfered portion of the support disk and covers the chamfered portion of the support disk.

Abstract: A wafer processing method includes: a protective member providing step of providing a protective member on the front side of a wafer; a wafer quarter generating step of cutting the wafer along the division line extending in a first direction through the center of the wafer and along the division line extending in a second direction perpendicular to the first direction through the center of the wafer, thereby generating four sectorial wafer quarters; a back grinding step of grinding the back side of each wafer quarter to reduce the thickness of the wafer quarter; a frame providing step of supporting the wafer quarter through an adhesive tape to an annular frame; and a wafer quarter dividing step of fully cutting the wafer quarter along all of the division lines extending in the first and second directions, thereby dividing the wafer quarter into the individual devices.

Abstract: In a wafer processing method, a wafer is cut along a division line extending in a first direction through the center of the wafer and along a division line extending in a second direction through the center of the wafer, thereby generating four sectorial wafer quarters. Grooves are formed on the front side of each wafer quarter along other division lines extending in a grid, each groove having a depth corresponding to a finished thickness of each device formed on the wafer quarter. A protective member is provided on the front side of each wafer quarter; and the wafer quarter is held through the protective member on a chuck table. The back side is then ground to reduce the thickness of the wafer quarter until the grooves are exposed to the back side of the wafer quarter, thereby dividing the wafer quarter into the individual devices.

Abstract: In a wafer processing method, grooves are formed on the front side of a wafer along all division lines extending in a first direction and along all division lines extending in a second direction perpendicular to the first direction. Each groove has a depth corresponding to a finished thickness of each device in the wafer. The wafer is cut into four sectorial wafer quarters. A protective member is provided on the front side of each wafer quarter; and the back side of the wafer quarter is ground to reduce the thickness of the wafer quarter to the finished thickness until the grooves are exposed to the back side of the wafer quarter, thereby dividing the wafer quarter into the individual devices.

Abstract: In one embodiment, die are singulated from a wafer having a back layer by placing the wafer onto a first carrier substrate with the back layer adjacent the carrier substrate, forming singulation lines through the wafer to expose the back layer within the singulation lines, and using a mechanical device to apply localized pressure to the wafer to separate the back layer in the singulation lines. The localized pressure can be applied through the first carrier substrate proximate to the back layer, or can be applied through a second carrier substrate attached to a front side of the wafer opposite to the back layer. Heat is applied to the first carrier substrate while the localized pressure is applied.

Abstract: A method includes forming a gate stack over a semiconductor substrate, forming an opening in the semiconductor substrate and adjacent to the gate stack, and performing a first epitaxy to grow a first semiconductor layer in the first opening. An etch-back is performed to reduce a thickness of the first semiconductor layer. A second epitaxy is performed to grow a second semiconductor layer over the first semiconductor layer. The first and the second semiconductor layers have different compositions.

Abstract: Chemical vapor deposition (CVD) systems for forming layers on a substrate are disclosed. Embodiments of the system comprise at least two processing chambers that may be linked in a cluster tool. A first processing chamber provides a chamber having a controlled environmental temperature and pressure and containing a first environment for performing CVD on a substrate, and a second environment for contacting the substrate with a plasma; a substrate transport system capable of positioning a substrate for sequential processing in each environment, and a gas control system capable of maintaining isolation. A second processing chamber provides a CVD system. Methods of forming layers on a substrate comprise forming one or more layers in each processing chamber. The systems and methods are suitable for preparing Group III-V, Group II-VI or Group IV thin film devices.

Abstract: A semiconductor structure is provided, which includes multiple sections arranged along a longitudinal axis. Preferably, the semiconductor structure comprises a middle section and two terminal sections located at opposite ends of the middle section. A semiconductor core having a first dopant concentration preferably extends along the longitudinal axis through the middle section and the two terminal sections. A semiconductor shell having a second, higher dopant concentration preferably encircles a portion of the semiconductor core at the two terminal sections, but not at the middle section, of the semiconductor structure. It is particularly preferred that the semiconductor structure is a nanostructure having a cross-sectional dimension of not more than 100 nm.

Abstract: A method and apparatus for depositing a film on a substrate includes introducing a material and a carrier gas into a heated chamber. The material may be a semiconductor material, such as a cadmium chalcogenide. A resulting mixture of vapor and carrier gas containing no unvaporized material is provided. The mixture of vapor and carrier gas are remixed to achieve a uniform vapor/carrier gas composition, which is directed toward a surface of a substrate, such as a glass substrate, where the vapor is deposited as a uniform film.

Abstract: The method for fabricating a free-standing group III nitride plate (6) comprises the steps of: growing a first group III nitride layer (2) on a foreign growth substrate (1); treating the first group III nitride layer (2) so as to make it porous; growing at a growth temperature within a growth reactor (7) a second group III nitride layer (4) on the first group III nitride layer (2); and separating the second group III nitride layer (4) from the growth substrate (1) so as to form a free-standing group III nitride plate (6). According to the present invention, the step of separating the second group III nitride layer (4) from the growth substrate (6) is performed at the growth temperature and within a growth reactor (7), and comprises selective chemical etching of the porous first group III nitride layer (2).

Abstract: A method for manufacturing pixel structure is provided. A patterned conductor layer including a gate, a scan line and a conductor pattern is formed on a substrate. A gate insulating layer, a metal oxide material layer and an etching stop material layer are formed on the substrate. Using the patterned conductor layer as mask, a patterned photoresist layer is formed on the etching stop material layer through a back exposure process. Using the patterned photoresist layer as mask, a metal oxide channel layer and an etching stop layer are formed above the gate. A source and a drain are formed on the etching stop layer. A passivation layer is formed on the substrate. A halftone mask is used to form a photosensitive layer on the passivation layer. The metal oxide material layer and the etching stop material layer on the scan line and the conductor pattern are removed.

Abstract: A method of manufacturing a semiconductor device having metal gate includes providing a substrate having a first transistor and a second transistor formed thereon, the first transistor having a first gate trench formed therein, forming a first work function metal layer in the first gate trench, forming a sacrificial masking layer in the first gate trench, removing a portion of the sacrificial masking layer to expose a portion of the first work function metal layer, removing the exposed first function metal layer to form a U-shaped work function metal layer in the first gate trench, and removing the sacrificial masking layer. The first transistor includes a first conductivity type and the second transistor includes a second conductivity type. The first conductivity type and the second conductivity type are complementary.

Abstract: A method for fabricating a semiconductor device is disclosed. The method includes forming a gate stack over a substrate, forming spacers adjoining opposite sidewalls of the gate stack, forming a sacrificial layer adjoining the spacers, removing a portion of the sacrificial layer, removing a portion of the spacers to form a recess cavity below the left spacers. Then, a strain feature is formed in the recess cavity. The disclosed method provides an improved method by providing a space between the spacer and the substrate for forming the strained feature, therefor, to enhance carrier mobility and upgrade the device performance.

Abstract: The present invention provides a manufacturing method of a non-volatile memory including forming a gate dielectric layer on a substrate; forming a floating gate on the gate dielectric layer; forming a first charge blocking layer on the floating gate; forming a nitride layer on the first charge blocking layer; forming a second charge blocking layer on the nitride layer; forming a control gate on the second charge blocking layer; and performing a treatment to the nitride layer to get a higher dielectric constant.

Abstract: A semiconductor device comprises a semiconductor substrate, an anorganic isolation layer on the semiconductor substrate and a metallization layer on the anorganic isolation layer. The metallization layer comprises a fuse structure. At least in an area of the fuse structure the metallization layer and the anorganic isolation layer have a common interface.

Abstract: Interconnect structures including a graphene cap located on exposed surfaces of a copper structure are provided. In some embodiments, the graphene cap is located only atop the uppermost surface of the copper structure, while in other embodiments the graphene cap is located along vertical sidewalls and atop the uppermost surface of the copper structure. The copper structure is located within a dielectric material.

Abstract: A method for forming dual damascene structures in a semiconductor structure is disclosed. The method generally includes etching a substrate using a first hard mask to form a plurality of first trenches and vias, forming a set of first conductive lines and via interconnects, removing the first hard mask, etching the substrate using a second hard mask to form a plurality of second trenches and vias, and forming a set of second conductive lines and via interconnects. At least some of the first conductive lines are interspersed between some of the second conductive lines. A planarization process is used on the substrate after forming the first conductive lines and via interconnects before forming the second conductive lines and via interconnects.

Abstract: A method of making a semiconductor device includes forming a dielectric layer over a semiconductor substrate. The method further includes forming a copper-containing layer in the dielectric layer, wherein the copper-containing layer has a first portion and a second portion. The method further includes forming a first barrier layer between the first portion of the copper-containing layer and the dielectric layer. The method further includes forming a second barrier layer at a boundary between the second portion of the copper-containing layer and the dielectric layer wherein the second barrier layer is adjacent to an exposed portion of the dielectric layer. The first barrier layer is a dielectric layer, and the second barrier layer is a metal oxide layer, and a boundary between a sidewall of the copper-containing layer and the first barrier layer is free of the second barrier layer.

Abstract: A metal interconnect structure and a method of manufacturing the metal interconnect structure. Manganese (Mn) is incorporated into a copper (Cu) interconnect structure in order to modify the microstructure to achieve bamboo-style grain boundaries in sub-90 nm technologies. Preferably, bamboo grains are separated at distances less than the “Blech” length so that copper (Cu) diffusion through grain boundaries is avoided. The added Mn also triggers the growth of Cu grains down to the bottom surface of the metal line so that a true bamboo microstructure reaching to the bottom surface is formed and the Cu diffusion mechanism along grain boundaries oriented along the length of the metal line is eliminated.

Abstract: The present invention provides a method of forming Cu interconnects. The method comprises depositing an etch stop layer and an insulating layer subsequently; forming vias and trenches in the insulating layer; depositing a diffusion barrier layer and a copper seed layer using PVD; applying electroplating process to form the copper interconnects; depositing a layer of filling materials and reflowing the filling materials to eliminate the uneven surface topography of the copper interconnection layer; and applying annealing and CMP to planarize the top surface of the copper interconnects, and rinsing. According to the method of forming Cu interconnects, the uneven surface topography after electroplating can be reduced, and the surface topography after CMP can be planarized.

Abstract: A method includes forming a sacrificial layer on a substrate. A hard mask layer is formed on the sacrificial layer. The hard mask layer and the sacrificial layer are etched to form a first plurality of openings in the hard mask layer and the sacrificial layer. A low-k dielectric layer is deposited in the first plurality of openings. The hard mask layer and the sacrificial layer are thereafter removed leaving behind a plurality of low-k dielectric pillar structures having second plurality of openings therebetween. The second plurality of openings are then filled with a copper-containing layer.

Abstract: A method of integrating a fluorine-based dielectric with a metallization scheme is described. The method includes forming a fluorine-based dielectric layer on a substrate, forming a metal-containing layer on the substrate, and adding a buffer layer or modifying a composition of the fluorine-based dielectric layer proximate an interface between the fluorine-based dielectric layer and the metal-containing layer.

Abstract: A semiconductor device is manufactured by etching a semiconductor substrate including an active region, forming a bit line contact hole from which the active region is protruded, forming a first spacer exposing a top of the active region at each of an inner wall and a bottom of the bit line contact hole, forming a bit line contact plug and a bit line over the exposed active region, and forming a second spacer over the semiconductor substrate including not only the bit line contact plug but also the bit line.

Abstract: Method of forming a capture pad on a semiconductor substrate. The method includes providing a semiconductor substrate having an active side and an inactive side and having a plurality of unfilled TSVs extending between the active side and the inactive side; filling the TSVs with a metal; defining capture pad areas on at least one of the active side and the inactive side adjacent to the TSVs, the defined capture pad areas comprising insulator islands and open areas; filling the open areas with the same metal to form a capture pad in direct contact with each of the TSVs, each of the capture pads having an all metal portion that follows an outline of each of the TSVs.

Abstract: A method of forming a pattern in a substrate is provided, in which the substrate having a pattern region is provided first. A plurality of stripe-shaped mask layers is formed on the substrate in the pattern region. Each of at least two adjacent stripe-shaped mask layers among the stripe-shaped mask layers has a protrusion portion and the protrusion portions face to each other. A spacer is formed on sidewalls of the stripe-shaped mask layers, wherein a thickness of the spacer is greater than a half of a distance between two of the protrusion portions. Subsequently, the stripe-shaped mask layers are removed. An etching process is performed by using the spacer as a mask to form trenches in the substrate. Thereafter, the trenches are filled with a material.

Abstract: Fabricating conductive lines in an integrated circuit includes providing a conductive metal in a multi-layer structure, performing a first sputter etch of the conductive metal using methanol plasma, and performing a second sputter etch of the conductive metal using a second plasma, wherein a portion of the conductive metal that remains after the second sputter etch forms the conductive lines. Alternatively, fabricating conductive lines includes providing a conductive metal as an intermediate layer in a multi-layer structure, etching the multi-layer structure to expose the conductive metal, performing a first etch of the conductive metal using methanol plasma, performing a second sputter etch of the conductive metal using a second plasma, wherein a portion of the conductive metal that remains after the second sputter etch forms the conductive lines, forming a liner that surrounds the conductive lines, and depositing a dielectric layer on the multi-layer structure.

Abstract: Methods of forming a semiconductor device structure and sulfur dioxide etch chemistries. The methods and chemistries, which may be plasma chemistries, include use of sulfur dioxide and a halogen-based compound to form a trimmed pattern of a patterning material, such as a resist material, at a critical dimension with low feature width roughness, with low space width roughness, without excessive height loss, and without substantial irregularities in the elevational profile, as compared to trimmed features formed using conventional chemistries and trimming methods.

Abstract: The inventive substrate treatment method includes: an organic solvent supplying step of supplying an organic solvent having a smaller surface tension than a rinse liquid to the upper surface of a substrate so that rinse liquid adhering to the upper surface of the substrate is replaced with the organic solvent; a higher temperature maintaining step of maintaining the upper surface of the substrate at a predetermined temperature higher than the boiling point of the organic solvent to thereby form a gas film of the organic solvent on the entire upper surface of the substrate including the gap of the minute pattern and to form a liquid film of the organic solvent on the gas film, the higher temperature maintaining step being performed after the organic solvent supplying step is started; and an organic solvent removing step of removing the organic solvent liquid film from the upper surface of the substrate.

Abstract: A method of forming a pattern on a substrate includes forming longitudinally elongated first lines and first sidewall spacers longitudinally along opposite sides of the first lines elevationally over an underlying substrate. Longitudinally elongated second lines and second sidewall spacers are formed longitudinally along opposite sides of the second lines. The second lines and the second sidewall spacers cross elevationally over the first lines and the first sidewall spacers. The second sidewall spacers are removed from crossing over the first lines. The first and second lines are removed in forming a pattern comprising portions of the first and second sidewall spacers over the underlying substrate. Other methods are disclosed.

Abstract: According to one embodiment, a pattern formation method includes: forming a block copolymer layer containing a polystyrene derivative and an acrylic having 6 or more carbon atoms on a side chain in an opening of a resist layer provided on an underlayer and having the opening; forming a first layer containing the polystyrene derivative and a second layer containing the acrylic in the opening by phase-separating the block copolymer layer; and removing the second layer.

Abstract: A palladium plated aluminum component of a semiconductor plasma processing chamber comprises a substrate including at least an aluminum or aluminum alloy surface, and a palladium plating on the aluminum or aluminum alloy surface of the substrate. The palladium plating comprises an exposed surface of the component and/or a mating surface of the component.