Abstract: An apparatus and method for performing nuclear magnetic resonance (NMR) or magnetic resonance imaging (MRI) on samples in metallic holders and vessels or in proximity to metallic objects is disclosed.

Abstract: A system and method for generating preamplifier feedback in magnetic resonance imaging (MRI) systems are provided. A preamplifier arrangement for the MRI system includes a plurality of preamplifiers with each of the preamplifiers connected to a different channel of a multi-channel coil array of the MRI system. The preamplifier arrangement further includes a feedback network connected to each of the plurality of preamplifiers with each of the feedback networks configured to generate negative feedback at one or more oscillation frequencies.

Abstract: A method for MR spectroscopy includes the steps of (a) switching at least one phase coding gradient for spatial coding of a spectral information to be detected, and (b) detection of the spectral information, and repeating (a) and (b) until a predetermined raw data space has been scanned. Specific spectral information is detected in (b) when the at least one phase coding gradient respectively has a value of 0. This specific spectral information is evaluated in order to determine a property of the spectral information already detected in (b), or still to be detected in (b).

Abstract: A magnetic resonance imaging apparatus includes a spectrum acquisition unit and a determining unit. The spectrum acquisition unit acquires a frequency spectrum of magnetic resonance signals from a metabolic product in a target region in an object. The determining unit determines the number of (a) integrations and/or (b) phase encodes of magnetic resonance signals for obtaining the frequency spectrum depending on a factor influencing the frequency spectrum.

Abstract: This disclosure is generally drawn to methods, systems, appliances and/or apparati related to obtaining magnetic resonance imaging (MRI) images. More specifically, the disclosure relates to obtaining MRI images using arterial spin labeling (ASL) and blood-oxygen-level dependence functional magnetic resonance imaging (BOLD-fMRI) techniques. In some examples, a method of obtaining magnetic resonance imaging (MRI) image(s) is provided. An example method may include providing arterial spin labeling (ASL) labeling, obtaining at least one ASL acquisition after ASL labeling, and obtaining at least one blood-oxygen-level dependence functional magnetic resonance imaging (BOLD-fMRI) acquisition after ASL labeling.

Abstract: A method of MR with spatial encoding to generate an image or spectroscopic data of an object of investigation inside an MR apparatus comprises the steps of (a) selecting a volume of interest within the object of investigation, (b) applying an RF pulse to generate a transverse magnetization within the object of investigation, (c) preparing a nonlinear phase distribution within the object of investigation by application of spatially encoding magnetic fields (SEMs), the SEMs comprising of a nonlinear gradient field or a combination of linear and nonlinear gradient fields, (d) effecting primary spatial encoding through application of SEMs, and (e) recording MR signals originating from the object of investigation. Step (c) or (d) thereby comprises applying a sequence of at least two SEMs, at least one of which contains a nonlinear field gradient and at least two of the SEMs having different field geometries.

Abstract: Electromagnetic proximity detection method for a buried structure executed with a mobile detection device, including sensing an electromagnetic field emitted from the structure as an analog electrical signal and digitalizing the analog electrical signal as a digital signal, performed after or while filtering the analog and/or digital signal. The proximity of the buried structure is determined by analyzing the digital signal, wherein the detection method can be alternatively executed in at least two of the following modes of detection: Power-Mode of detection, Radio-Mode of detection or Active-Mode of detection. An additional Switching-Mode of operation includes a repeated sequential detection in at least two of the mentioned modes of detection and is done by automatic subsequent alternating of the mode of detection with a minimum rate of alternation that an area of detection is coverable by the at least two modes of detection in a single execution of the detection method.

Abstract: A ground fault detection circuit according to the present invention is a ground fault detection circuit that detects the occurrence of a ground fault of a battery that is insulated, and that includes: an AC signal generation section that generates an AC signal; a first capacitive element that couples the AC signal generated by the AC signal generation section to the battery; a voltage division section that voltage divides the AC signal that is coupled to the battery by the first capacitive element; a ground fault detection unit that detects a ground fault of the battery based on an AC component of an input signal; and a second capacitive element that couples the AC signal that has been voltage divided by the voltage division section to the ground fault detection unit as the input signal.

Abstract: A method for testing a conductive web includes moving a conductive web past at least one electrostatic probe, providing an alternating current or voltage which generates an alternating current to the at least one electrostatic probe, measuring a current or voltage in the at least one electrostatic probe induced by a capacitance between the conductive web and the at least one electrostatic probe, comparing the measured current or voltage to a reference value, and determining a level of bagginess of the conductive web based on the step of comparing.

Abstract: Disclosed herein are systems and methods for identifying a fault type in an electric power delivery system using an angle difference between a total zero-sequence current and a total negative-sequence current and a comparison of phase-to-phase currents against a threshold. The angle difference falls into one of a number of predetermined angle difference sectors. Each sector is associated with a phase-to-ground fault type and a phase-to-phase-to-ground fault type or two phase-to-phase-to-ground fault types. The phase-to-phase current(s) of the indicated phase-to-phase-to-ground fault type(s) associated with the sector are compared with a threshold to determine which of the fault types of the sector is the actual fault type. The threshold may be a multiple of a maximum phase-to-phase current.

Abstract: A calibration substrate having at least one calibration standard with at least two electrical connection points, each for one measurement gate of a vector network analyzer. At least one electrical connection point is formed of at least one calibration standard having a switch, wherein the switch has a first electrical contact electrically connected to an electrical connection point of the calibration standard, a second electrical contact designed for electrically connecting to a measurement gate of the vector network analyzer, and a third electrical contact, wherein the switch is designed such that an electrical contact is established either between the first and third electrical contact or between the first and second electrical contact.

Abstract: A signal acquisition system has a signal acquisition probe having probe tip circuitry coupled to a resistive center conductor signal cable. The resistive center conductor signal cable is coupled to a compensation system in a signal processing instrument via an input node and input circuitry in the signal processing instrument. The signal acquisition probe and the signal processing instrument have mismatched time constants at the input node with the compensation system having an input amplifier with feedback loop circuitry and a compensation digital filter providing pole-zero pairs for maintaining flatness over the signal acquisition system frequency bandwidth.

Abstract: A concentric coplanar capacitive sensor includes a charged central disc forming a first electrode, an outer annular ring coplanar with and outer to the charged central disc, the outer annular ring forming a second electrode, and a gap between the charged central disc and the outer annular ring. The first electrode and the second electrode may be attached to an insulative film. A method provides for determining transcapacitance between the first electrode and the second electrode and using the transcapacitance in a model that accounts for a dielectric test piece to determine inversely the properties of the dielectric test piece.

Abstract: A surface-conforming obscured feature detector includes a plurality of sensor plates, each having a capacitance that varies based on the dielectric constant of the materials that compose the surrounding objects and the proximity of those objects. A sensing circuit is coupled to the sensor plates 32 to measure the capacitances of the sensor plates. A controller is coupled to the sensing circuit to analyze the capacitances measured by the sensing circuit. One or a plurality of indicators are coupled to the controller, and are selectively activated to identify the location of an obscured feature behind a surface.

Abstract: A micro-electro-mechanical system (MEMS) actuator circuit and method. The circuit includes a current mirror, a voltage divider having an interior contact and coupled between the mirror output and a potential, an operational amplifier having an input coupled to the interior contact and a switch having input/output contacts separately coupled to the amplifier output and the mirror input and having a switch control. The amplifier output can be coupled to a digital control circuit which can be coupled to the switch control contact and to a digital to analog circuit (DAC) which can be coupled to the digital control circuit and to another amplifier input. An enable signal at the switch control couples the switch input/output contacts together. The capacitance of a MEMS capacitor coupled to the mirror output is determined by measurement of time for the amplifier output to switch from one level to another following a change in DAC output potential.

Abstract: A battery emulation device for simulating a battery cell voltage at a terminal of a battery control unit in accordance with a setpoint value includes a control unit configured to determine the setpoint value and provide the determined setpoint value via a galvanically isolated interface; and at least one emulation channel, each including: a voltage source; an amplifier unit; connection lines for connecting the emulation channel; measurement lines; and a fault simulation device configured to simulate fault states.

Abstract: An embodiment of a test apparatus for executing a test of a set of electronic devices having a plurality of electrically conductive terminals, the test apparatus including a plurality of electrically conductive test probes for exchanging electrical signals with the terminals, and coupling means for mechanically coupling the test probes with the electronic devices. In an embodiment, the coupling means includes insulating means for keeping each one of at least part of the test probes electrically insulated from at least one corresponding terminal during the execution of the test. Each test probe and the corresponding terminal form a capacitor for electro-magnetically coupling the test probe with the terminal.

Abstract: A test system for testing a multilayer 3-dimensional integrated circuit (IC), where two separate layers of IC circuits are temporarily connected in order to achieve functionality, includes a chip under test with a first portion of the 3-dimensional IC, and a test probe chip with a second portion of the 3-dimensional IC and micro-electrical-mechanical system (MEMS) switches that selectively complete functional circuits between the first portion of the 3-dimensional IC in a first IC layer to circuits within the second portion of the 3-dimensional IC in a second IC layer. The MEMS switches include tungsten (W) cone contacts, which make the selective electrical contacts between circuits of the chip under test and the test probe chip and which are formed using a template of graded borophosphosilicate glass (BPSG).

Abstract: The present invention provides a method and apparatus for bypassing silicon bugs. One exemplary embodiment of the method includes using a logic element formed on a substrate to detect a predefined trigger condition indicating onset of a functional bug during operation of a semiconductor device formed on the substrate. The method also includes modifying operation of the semiconductor device to avoid onset of the functional bug by taking a predefined action associated with the predefined trigger condition.

Abstract: Fault detection apparatuses and methods for detecting a processing or hardware performance fault of a semiconductor production tool have been provided. In an exemplary embodiment, a method for detecting a fault of a semiconductor production tool includes sensing a signal associated with a test component of the production tool during operation of the production tool and converting the signal to an electronic test signal. A prerecorded signature signal corresponding to the test component is provided and the test signal and the prerecorded signature signal are compared.

Abstract: A method for monitoring a controller for controlling and/or monitoring a three-phase electric motor, in particular an asynchronous or synchronous motor, wherein two phase currents are measured and an error signal is generated if at least one of the two measured phase currents is essentially zero. An error signal is also generated if none of the two measured phase currents is essentially zero, but a sum formed of the two measured phase currents is essentially zero.

Abstract: Under a condition that rotor rotation speeds ?es are equal, winding wire currents Id, Iq are equal, and winding wire inductances Ld, Lq are equal in first and second electric motors (1, 2), a magnet temperature anomaly detector (30) provided in a microcomputer (5) calculates a change ratio d(|?ml??mr|)/dt of a magnetic flux difference between the first and second electric motors (1, 2) based on the difference Vql*?Vqr* between a q-axis voltage command value Vql* corresponding to the first electric motor (1) and a q-axis voltage command value Vqr corresponding to the second electric motor (2), and then when the change ratio d(|?ml??mr|)/dt of the magnetic flux difference is more than a predetermined threshold Sh1, it is determined that a permanent magnet of at least any one of the electric motors (1, 2) has a temperature anomaly.

Abstract: Pre-Charge Static Logic (PCSL), is an asynchronous-logic Quasi-Delay-Insensitive architecture based on Static-Logic, featuring fully-range Dynamic Voltage Scaling including robust operation in the sub-threshold voltage regime, with simultaneous low hardware overheads, high-speed and yet low power dissipation. The invented PCSL logic circuit achieves this by integration of the Request sub-circuit into the Static-Logic cell. During the initial phase, the output of Static-Logic cell (within the PCSL logic circuit) is pre-charged. During the evaluate phase, the Static-Logic cell computes the input and the PCSL logic circuit outputs the computation.

Abstract: The disclosure relates generally to triple-redundant sequential state (TRSS) machines formed as integrated circuits on a semiconductor substrate, such as CMOS, and computerized methods and systems of designing the triple-redundant sequential state machines. Of particular focus in this disclosure are sequential state elements (SSEs) used to sample and hold bit states. The sampling and holding of bits states are synchronized by a clock signal thereby allowing for pipelining in the TRSS machines. In particular, the clock signal may oscillate between a first clock state and a second clock state to synchronize the operation of the SSE according to the timing provided by the clock states. The SSEs have a self-correcting mechanism to protect against radiation induced soft errors. The SSE may be provided in a pipeline circuit of a TRSS machine to receive and store a bit state of bit signal generated by combinational circuits within the pipeline circuit.

Abstract: In accordance with some embodiments, the present disclosure relates to a dual mode control interface that can be used to provide both a radio frequency front end (RFFE) serial interface and a two-mode general purpose input/output (GPIO) interface within a single digital control interface die. In certain embodiments, the dual mode control interface, or digital control interface, can communicate with a power amplifier. Further, the dual mode control interface can be used to set the mode of the power amplifier.

Abstract: A control circuit comprises a first NOR gate, a first NMOS transistor, and a first PMOS transistor. The control circuit also comprises an output node. The control circuit further comprises a half latch keeper circuit coupled to a gate of the first NMOS transistor and to a gate of the first PMOS transistor. The half latch keeper circuit is configured to keep the output node at a logical 1 during a standby mode. The control circuit additionally comprises an operational PMOS transistor coupled to the output node. An output of the first NOR gate is coupled to a gate of the operational PMOS transistor. The control circuit is configured to turn off the operational PMOS transistor during the standby mode.

Abstract: A circuit has a stacked structure having at least one symmetric FET at a bottom of the stack. More particularly, the circuit has a stacked structure which includes an asymmetric FET and a symmetric FET. The symmetric FET is placed at the bottom of the stacked structure closer to ground than the asymmetric FET.

Abstract: A method of buffering data from core circuitry includes generating a first sourcing control signal responsive to indication signals indicating an operating voltage and output data, generating a second sourcing control signal responsive to the indication signals, and applying the operating voltage to an output terminal in response to the first sourcing control signal and the second sourcing control signal. The first sourcing control signal swings between the operating voltage and a reference voltage. The reference voltage is a signal selected from among a plurality of internal voltages in response to selection signals generated as a result of decoding the indication signals.

Abstract: A three-dimensional (3D) gate driver integrated circuit includes a high-side integrated circuit stacked on a low-side integrated circuit where the high-side integrated circuit and the low-side integrated circuit are interconnected using through-silicon vias (TSV). As thus formed, the high-side integrated circuit and the low-side integrated circuit can be formed without termination regions and without buried layers. The 3D gate driver integrated circuit improves ease of high voltage integration and improves the ruggedness and reliability of the gate driver integrated circuit.

Abstract: A post driver implemented using core device transistors to drive an output connection between the high and low voltage levels of an I/O voltage range. The post driver is made from a plurality of core devices operable within a core voltage range that is less than the I/O voltage range. The plurality of core devices is cascaded between upper and lower power connections set to the full I/O voltage range. The post driver has a voltage clamping element, such as a diode, having a predefined threshold voltage and connected to the core devices so as to maintain the voltage difference across the terminals thereof within the core voltage range.

Abstract: A high voltage half-bridge driver circuit has a high voltage terminal and a floating node to be connected with a high side switch therebetween. When turning on the high side switch, a high voltage offset detection circuit detects a voltage related to the voltage at the floating node for triggering a zero voltage switching signal.

Abstract: Recycling energy in a clock distribution network is provided. A circuit includes a clock driver associated with a clock signal and having an output connected to a first load capacitance. The circuit also includes a second load capacitance connected in parallel with the first load capacitance. The circuit further includes a power transfer circuit including an inductor and a transmission gate connected in series between the first load capacitance and the second load capacitance. The power transfer circuit controls a flow of energy between the first load capacitance and the second load capacitance based on the clock signal.

Abstract: A low voltage isolation switch is suitable for receiving from a connection node a high voltage signal and transmitting said high voltage signal to a load via a connection terminal. The isolation switch includes a driving block connected between first and second voltage reference terminals and including a first driving transistor coupled between the first voltage reference (Vss) and a first driving circuit node and a second driving transistor coupled between the driving circuit node and the second supply voltage reference. The switch comprises an isolation block connected to the connection terminal (pzt), the connection node, and the driving central circuit node and including a voltage limiter block, a diode block and a control transistor. The control transistor is connected across the diode block between the connection node and the connection terminal and has a control terminal connected to the driving central circuit node.

Abstract: A dynamic latch has a pair of parallel pass gates (a first parallel pass gate that receives a seed signal, and a second parallel pass gate that receives a data signal). A first latch logic circuit performs logic operations using signals output by the parallel pass gates to produce an updated data signal. An additional pass gate is operatively connected to the first latch logic circuit. An additional pass gate controls passage of the updated data signal. An inverter receives the updated data signal from the pass gate, and inverts and outputs the updated data signal as an output data signal. Thus, the dynamic latch comprises two inputs into the pair of parallel pass gates and performs only one of four logical operations on a received data signal. The four logical operations are performed using the signals applied to the two inputs.

Abstract: A multi-phase frequency divider comprises first and second latches configured to receive a first input clock having a first frequency and a first phase, wherein the second latch receives the inverted first input clock. The first and second latches generate a plurality of output clocks each having a frequency that equals the first frequency divided by a predetermined divider ratio. The plurality of output clocks each have different phases staggered from the first phase. The frequency divider also comprises at least a first delay latch electrically connected between the first and second latches. The first delay latch is configured to generate, based on an output clock generated by the first latch and a second input clock at the first frequency and a second phase, two delayed output clocks. These two delayed output clocks have a frequency that equals the first frequency divided by the predetermined ratio with different staggered phases.

Abstract: A synchronization method for current differential protection comprises: selecting a point on the transmission line protected by the current differential protection; measuring the current and the voltage of each of the terminals of said transmission line; calculating the compensating voltage at the selected point respectively according to the measured current and the voltage of the each terminal; detecting and calculating the synchronization error by comparing all the compensating voltages.

Abstract: A reset circuit and a reset method of a portable terminal are provided. The reset circuit of a portable terminal includes an input unit for generating a certain input signal for reset according to a user input, a reset unit for generating a manual reset input signal according to an input of the certain input signal, for performing a control operation to cut-off power to be supplied to a Power Management IC (PMIC) using a signal generated during an operation maintenance time interval of the portable terminal and the manual reset input signal, and for performing a control operation to resupply the power to the PMIC according to an input signal from the input unit or completion of a preset timer, and a power supply unit for supplying the power.

Abstract: A phase locked loop is provided. The phase locked loop includes a detector, a controlled oscillator and a filtering unit coupled between the detector and the controlled oscillator. The detector generates a phase difference signal according to a reference frequency and an oscillation signal. The controlled oscillator generates the oscillation signal according to a filtered signal. The filtering unit filters the phase difference signal to generate the filtered signal, and the filtering unit has a high frequency filter of which a pole is greater than the reference frequency and less than a frequency of the oscillation signal.

Abstract: The present disclosure relates to a frequency synthesizer. The frequency synthesizer includes a phase comparator having first and second input nodes. The first input node receives a reference signal having a reference frequency. A channel control block has an input that receives a channel word and an output coupled to the second input node of the phase comparator. A local oscillator (LO) output node provides an LO signal having an LO frequency based on the reference frequency and the channel word. A feedback back couples the LO output node to the second input node of the phase comparator through the channel control block. A non-linear error correction element is operably coupled on a coupling path extending between the phase comparator and the DCO.

Abstract: A cascaded phase-locked loop (PLL) clock generation technique reduces frequency drift of a low-jitter clock signal in a holdover mode. An apparatus includes a first PLL circuit configured to generate a control signal based on a first clock signal and a first divider value. The apparatus includes a second PLL circuit configured to generate the first clock signal based on a low-jitter clock signal and a second divider value. The apparatus includes a third PLL circuit configured to generate the second divider value based on the first clock signal, a third divider value, and a second clock signal. The low-jitter clock signal may have a greater temperature dependence than the second clock signal and the second clock signal may have a higher jitter than the low-jitter clock signal.

Abstract: A receiving circuit includes: a sampling circuit to sample input data in synchronization with first clock to obtain boundary data, and sample the input data in synchronization with second clock to obtain center data; a decision feedback equalizer to perform equalization on the center data using an equalization coefficient, and output first output data; a first comparator circuit to perform binary decision on the boundary data and output second output data; a phase detection circuit to detect phase information of the input data using the first output data and the second output data; a phase difference computation circuit to calculate phase difference of the first output data using the equalization coefficient; a first phase adjustment circuit to adjust phase of the first clock using the phase information; and a second phase adjustment circuit to adjust phase of the second clock using the phase information and the phase difference.

Abstract: This invention provides a loop filter device and a method for IC designers to adjust the pole or zero location of a phase lock loop (PLL) circuit. The pole and zero location are controlled by an amplifier and some on-chip resistor and capacitor components. The effective capacitance is magnified by the gain of the amplifier. The advantage of the loop filter device and the method according to embodiments of the present invention provides a feasible way to achieve a very low bandwidth in the PLL circuit without a huge external surface-mount capacitor.

Abstract: A phase-locked loop (PLL) for clock delay adjustment and a method thereof are disclosed. The method includes the following steps. A reference clock signal and a clock signal are generated. The reference clock signal is fed through an N-divider to generate an output clock signal having a frequency 1/N of the reference clock signal. In a phase frequency detector, a control signal is generated in accordance with a phase difference and a frequency difference between the output clock signal and a feedback signal generated by a voltage controlled oscillator coupled to the phase frequency detector. The control signal is then fed through a charge pump and a loop filter to generate a voltage control signal according to the control signal. Moreover, in an adjustable delay element, a blended delay signal is generated according to a clock signal and the voltage control signal.

Abstract: Aspects of the disclosure provide a circuit. The circuit includes a depletion mode transistor coupled to a power supply and a current path coupled with the depletion mode transistor in series to provide a current to charge a capacitor. The current path has a first resistance during a first stage, such as when the circuit initially receives power, and has a second resistance during a second stage when the capacitor is charged to have a predetermined voltage level.

Abstract: A method of operating a circuit includes receiving a first data signal at a first node. The first node is coupled to a second node to couple the first data signal to the second node. After coupling the first node to the second node, an inversion is enabled from the second node to a third node. An inversion from the third node to the fourth node is provided. After the enabling the inversion from the second node to the third node, the first node is decoupled from the second node. After the enabling the inversion from the second node to the third node, the second node is coupled to the third node. An inversion from the fourth node to the third node is enabled and the second node is decoupled from the fourth node.

Abstract: A method for reducing average current consumption in a local oscillator (LO) path is disclosed. An LO signal is received at a master frequency divider and a slave frequency divider. Output from the master frequency divider is mixed with an input signal to produce a first mixed output. Output from the slave frequency divider is mixed with the input signal to produce a second mixed output. The second mixed output is forced to be in phase with the first mixed output.

Abstract: Provided is an adjustment apparatus that adjusts signal output timings, comprising a control section that causes a first signal output section to output a signal having a rising edge and causes a second signal output section to output a signal having a falling edge; a signal acquiring section that acquires a composite signal obtained by combining the signal output by the first signal output section and the signal output by the second signal output section; and an adjusting section that adjusts a timing difference between a signal output timing of the first signal output section and a signal output timing of the second signal output section, such that the signal acquiring section acquires the composite signal having a composite waveform in which the rising edge and the falling edge overlap.

Abstract: A clock driver includes a clock interconnect running to multiple lanes of an integrated circuit chip, the interconnect including a positive clock line and a negative clock line. A clock generator generates a clock signal and a source inductor, through which the clock generator draws DC power, helps drive the clock signal down the interconnect. The source inductor may be tunable. A distributed (or tunable) inductor is connected to and positioned along the positive and negative clock lines between the source inductor and an end of the interconnect. Multiple distributed inductors may be positioned and optionally tuned such as to create a resonant response in the clock signal with substantially similar quality and amplitude as delivered to the multiple lanes. Any of the distributed and source inductors may be switchable to change inductance of the distributed inductors and thus change the clock frequency in the lanes for different communication standards.

Abstract: Embodiments of an apparatus are disclosed that may allow for the translation of signals from one power domain to another with well-balanced rise and fall times over a wide operational range. The apparatus may include an input buffer, a voltage shift circuit, and output circuit, and an output driver. The input buffer may be configured to generate a buffered version and delayed inverted version of an external signal at a first voltage level. The voltage shift circuit may be configured to generate two internal signals at a second voltage level dependent upon the output signals of the input buffer. The output circuit may be configured to generate two output driver signals at the second voltage level dependent upon the output signals of the voltage shift circuit. The output driver circuit may be configured to generate an output signal at the second voltage level dependent on the two output driver signals.

Abstract: According to one embodiment, a semiconductor switch includes a first element that includes a switching element and an anti-parallel diode. The switching element has a breakdown voltage and is coupled to a control terminal and second and third terminals. The semiconductor switch further includes a second element having a breakdown voltage lower than that of the first element. The second element is coupled to a control terminal and second and third terminals. The semiconductor switch also includes a flyback diode having a breakdown voltage substantially similar to that of the first element. A negative electrode of the first element is connected to a negative electrode of the second element and the flyback diode is connected in parallel between a positive terminal of the first element and a positive terminal of the second element. The control terminal for the first element and the control terminal for the second element are coupled to one or more control circuits independently of each other.