Patents Issued in July 29, 2014
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Patent number: 8791493Abstract: An exemplary light-emitting diode (LED) package includes an electrically insulating substrate, an electrode structure embedded in the insulating substrate, and a plurality of LED chips electrically connecting with the electrodes of the electrode structure respectively. The electrode structure includes a first electrode, a second electrode and a third electrode located between the first and second electrodes. Top surfaces of the first, second and third electrodes are exposed out of a top surface of the insulating substrate to support the LED chips. Bottom surfaces of the first and second electrodes are exposed out of a bottom surface of the substrate to connect with welding pads of a printed circuit board. A bottom surface of the third electrode is received in the substrate.Type: GrantFiled: July 31, 2013Date of Patent: July 29, 2014Assignee: Advanced Optoelectronic Technology, Inc.Inventors: Che-Hsang Huang, Pin-Chuan Chen, Lung-Hsin Chen, Wen-Liang Tseng, Yu-Liang Huang
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Patent number: 8791494Abstract: Disclosed are a light emitting device and a light emitting device package. The light emitting device includes a light emitting structure including a first conductive semiconductor layer, an active layer on the first conductive semiconductor layer, and a second conductive semiconductor layer on the active layer, an adhesive layer contacting a top surface of the first conductive semiconductor layer, a first electrode contacting a top surface of the first conductive semiconductor and a top surface of the adhesive layer, and a second electrode contacting the second conductive semiconductor layer, wherein the adhesive layer contacting the first electrode is spaced apart from the second electrode.Type: GrantFiled: October 16, 2013Date of Patent: July 29, 2014Assignee: LG Innotek Co., Ltd.Inventors: Hwan Hee Jeong, Sang Youl Lee, Ji Hyung Moon, June O Song, Kwang Ki Choi
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Patent number: 8791495Abstract: Disclosed is a light emitting device package. The light emitting device package includes a body; first and second electrode layers on the body; a light emitting device electrically connected to the first and second electrode layers on the body; a luminescent layer on the light emitting device; and an encapsulant layer including particles on the luminescent layer, wherein an effective refractive index of the encapsulant layer has a deviation of 10% or less with respect to an effective refractive index of the luminescent layer.Type: GrantFiled: January 4, 2011Date of Patent: July 29, 2014Assignee: LG Innotek Co., Ltd.Inventor: Geun Ho Kim
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Patent number: 8791496Abstract: A silicone resin composition includes (1) an organopolysiloxane having at least two alkenylsilyl groups in one molecule, (2) an organopolysiloxane having at least two hydrosilyl groups in one molecule, (3) a hydrosilylation catalyst, and (4) a curing retarder, wherein the curing retarder contains tetraalkylammonium hydroxide.Type: GrantFiled: July 20, 2012Date of Patent: July 29, 2014Assignee: Nitto Denko CorporationInventor: Hiroyuki Katayama
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Patent number: 8791497Abstract: A light-emitting device package mold and a method of manufacturing a lens of a light-emitting device package. The light-emitting device package mold includes a convex unit, an inner circumference of which has a hemispherical shape; a flat panel unit that forms a flat panel by extending from an edge of the convex unit; a cylindrical unit extending in a vertical direction with respect to an upper surface of the flat panel unit; and an injection hole and a discharge hole that penetrate through the convex unit, wherein the discharge hole is formed in a horizontal direction with respect to the flat panel unit.Type: GrantFiled: November 14, 2012Date of Patent: July 29, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Hun-yong Park, Dae-young Kim, Choo-ho Kim, Jomg-o Lim, Yong-rak Jeong
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Patent number: 8791498Abstract: A semiconductor light emitting device, includes: a stacked structural unit including a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, and a light emitting layer provided therebetween; and an electrode including a first and second metal layers, the first metal layer including silver or silver alloy and being provided on a side of the second semiconductor layer opposite to the light emitting layer, the second metal layer including at least one element selected from gold, platinum, palladium, rhodium, iridium, ruthenium, and osmium and being provided on a side of the first metal layer opposite to the second semiconductor layer. A concentration of the element in a region including an interface between the first and second semiconductor layers is higher than that of the element in a region of the first metal layer distal to the interface.Type: GrantFiled: March 8, 2010Date of Patent: July 29, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Katsuno, Yasuo Ohba, Kei Kaneko, Mitsuhiro Kushibe
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Patent number: 8791499Abstract: An improved laser light emitting diode. The device has a gallium nitride substrate structure, which includes a surface region. The device also has an epitaxial layer overlying the surface region and a p-n junction formed within a portion of the epitaxial layer. In a preferred embodiment, the device also has one or more plane or line defects spatially configured in a manner to be free from intersecting the p-n junction, the one or more plane or line defects being at least 1×106 cm?2.Type: GrantFiled: May 24, 2010Date of Patent: July 29, 2014Assignee: Soraa, Inc.Inventors: Rajat Sharma, Eric M. Hall
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Patent number: 8791500Abstract: A semiconductor device having a lateral insulated gate bipolar transistor includes a first conductivity type drift layer, a second conductivity type collector region formed in a surface portion of the drift layer, a second conductivity type channel layer formed in the surface portion of the drift layer, a first conductivity type emitter region formed in a surface portion of the channel layer, and a hole stopper region formed in the drift layer and located between the collector region and the emitter region. Holes are injected from the collector region into the drift layer and flow toward the emitter region through a hole path. The hole stopper region blocks a flow of the holes and narrows the hole path to concentrate the holes.Type: GrantFiled: December 19, 2012Date of Patent: July 29, 2014Assignee: DENSO CORPORATIONInventors: Youichi Ashida, Shigeki Takahashi
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Patent number: 8791501Abstract: An integrated passive device (IPD) structure includes an electronic component having an active surface and an opposite inactive surface. The IPD structure further includes a passive device structure extending through the electronic component between the active surface and the inactive surface and having a portion(s) formed on the active surface, the inactive surface, or both the active and inactive surfaces. Accordingly, the IPD structure includes the functionality of the electronic component, e.g., an integrated circuit chip, and of the passive device structure, e.g., one or more capacitors, resistors, inductors, or surface mounted components. By integrating the passive device structure with the electronic component to form the IPD structure, separate mounting of passive component(s) to the substrate is avoided this minimizing the substrate size.Type: GrantFiled: December 3, 2010Date of Patent: July 29, 2014Inventors: Ruben Fuentes, Brett Dunlap
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Patent number: 8791502Abstract: The present invention discloses a semiconductor device, comprising: a substrate, a channel layer epitaxially grown in the substrate, a gate stack structure on the channel layer, gate spacers on both sides of the gate stack structure, and source/drain areas on both sides of the channel layer in the substrate, characterized in that the carrier mobility of the channel layer is higher than that of the substrate. In accordance with the semiconductor device and the method of manufacturing the same in the present invention, forming the device channel region by filling the trench with epitaxial high-mobility materials in a gate last process can enhance the carrier mobility in the channel region, thereby the device response speed is substantially improved and the device performance is greatly enhanced.Type: GrantFiled: November 30, 2011Date of Patent: July 29, 2014Assignee: The institute of microelectronics Chinese Academy of ScienceInventor: Guilei Wang
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Patent number: 8791503Abstract: A conductive field plate is formed between the drain electrode and gate of each cell of a III-Nitride semiconductor and is connected to the source electrode to reduce the electric field between the gate and the drain. The electrodes may be supported on N+ III-Nitride pad layers and the gate may be a Schottky gate or an insulated gate.Type: GrantFiled: September 16, 2008Date of Patent: July 29, 2014Assignee: International Rectifier CorporationInventor: Michael A. Briere
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Patent number: 8791504Abstract: A circuit structure includes a substrate, a nucleation layer of undoped aluminum nitride, a graded buffer layer comprising aluminum, gallium, nitrogen, one of silicon and oxygen, and a p-type conductivity dopant, a ungraded buffer layer comprising gallium, nitrogen, one of silicon and oxygen, and a p-type conductivity dopant without aluminum, and a bulk layer of undoped gallium nitride over the ungraded buffer layer. The various dopants in the graded buffer layer and the ungraded buffer layer increases resistivity and results in layers having an intrinsically balanced conductivity.Type: GrantFiled: October 20, 2011Date of Patent: July 29, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chi-Ming Chen, Po-Chun Liu, Hung-Ta Lin, Chin-Cheng Chang, Chung-Yi Yu, Chia-Shiung Tsai, Ho-Yung David Hwang
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Patent number: 8791505Abstract: A semiconductor device includes: a second nitride semiconductor layer formed on a first nitride semiconductor layer, and having a larger band gap than the first nitride semiconductor layer; and an electrode filling a recess formed in the first and second nitride semiconductor layers. The first nitride semiconductor layer has a two-dimensional electron gas layer immediately below the second nitride semiconductor layer. The electrode and the second nitride semiconductor layer are in contact with each other at a first contact interface. The electrode and a portion of the first nitride semiconductor layer corresponding to the two-dimensional electron gas layer are in contact with each other at a second contact interface connected below the first contact interface. The first contact interface is formed such that a width of the recess increases upward. The second contact interface is more steeply inclined than the first contact interface.Type: GrantFiled: March 7, 2013Date of Patent: July 29, 2014Assignee: Panasonic CorporationInventors: Yusuke Kinoshita, Satoshi Tamura, Yoshiharu Anda, Tetsuzo Ueda
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Patent number: 8791506Abstract: Embodiments disclosed herein include methods in which a pair of openings are formed into semiconductor material, with the openings being spaced from one another by a segment of the semiconductor material. Liners are formed along sidewalls of the openings, and then semiconductor material is isotropically etched from bottoms of the openings to merge the openings and thereby completely undercut the segment of semiconductor material. Embodiments disclosed herein may be utilized in forming SOI constructions, and in forming field effect transistors having transistor gates entirely surrounding channel regions. Embodiments disclosed herein also include semiconductor constructions having transistor gates surrounding channel regions, as well as constructions in which insulative material entirely separates an upper semiconductor material from a lower semiconductor material.Type: GrantFiled: September 2, 2011Date of Patent: July 29, 2014Assignee: Micron Technology, Inc.Inventors: Ted Taylor, Xiawan Yang
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Patent number: 8791507Abstract: A layout of a semiconductor device is capable of reliably reducing a variation in gate length due to the optical proximity effect, and enables flexible layout design to be implemented. Gate patterns (G1, G2, G3) of a cell (C1) are arranged at the same pitch, and terminal ends (e1, e2, e3) of the gate patterns are located at the same position in the Y direction, and have the same width in the X direction. A gate pattern (G4) of a cell (C2) has protruding portions (4b) protruding toward the cell (C1) in the Y direction, and the protruding portions (4b) form opposing terminal ends (eo1, eo2, eo3). The opposing terminal ends (eo1, eo2, eo3) are arranged at the same pitch as the gate patterns (G1, G2, G3), are located at the same position in the Y direction, and have the same width in the X direction.Type: GrantFiled: March 18, 2013Date of Patent: July 29, 2014Assignee: Panasonic CorporationInventors: Kazuyuki Nakanishi, Masaki Tamaru
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Patent number: 8791508Abstract: A Gallium Nitride (GaN) series of devices—transistors and diodes are disclosed—that have greatly superior current handling ability per unit area than previously described GaN devices. The improvement is due to improved layout topology. The devices also include a simpler and superior flip chip connection scheme and a means to reduce the thermal resistance. A simplified fabrication process is disclosed and the layout scheme which uses island electrodes rather than finger electrodes is shown to increase the active area density by two to five times that of conventional interdigitated structures. Ultra low on resistance transistors and very low loss diodes can be built using the island topology. Specifically, the present disclosure provides a means to enhance cost/effective performance of all lateral GaN structures.Type: GrantFiled: April 13, 2011Date of Patent: July 29, 2014Assignee: GaN Systems Inc.Inventors: John Roberts, Ahmad Mizan, Girvan Patterson, Greg Klowak
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Patent number: 8791509Abstract: In a multiple gate transistor, the plurality of Fins of the drain or source of the transistor are electrically connected to each other by means of a common contact element, wherein enhanced uniformity of the corresponding contact regions may be accomplished by an enhanced silicidation process sequence. For this purpose, the Fins may be embedded into a dielectric material in which an appropriate contact opening may be formed to expose end faces of the Fins, which may then act as silicidation surface areas.Type: GrantFiled: November 17, 2009Date of Patent: July 29, 2014Assignee: GLOBALFOUNDRIES Inc.Inventors: Sven Beyer, Patrick Press, Rainer Giedigkeit, Jan Hoentschel
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Patent number: 8791510Abstract: A semiconductor device includes a gate structure on a semiconductor substrate, an impurity region at a side of the gate structure and the impurity region is within the semiconductor substrate, an interlayer insulating layer covering the gate structure and the impurity region, a contact structure extending through the interlayer insulating layer and connected to the impurity region, and an insulating region. The contact structure includes a first contact structure that has a side surface surrounded by the interlayer insulating layer and a second contact structure that has a side surface surrounded by the impurity region. The insulating region is under the second contact structure.Type: GrantFiled: June 5, 2012Date of Patent: July 29, 2014Assignee: Samsung Electronics Co., Ltd.Inventor: Young-Kyu Lee
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Patent number: 8791511Abstract: A semiconductor device is disclosed which has a high voltage isolation structure that is a RESURF structure, wherein it is possible to reduce a displacement current generated by dV/dt noise, and a method of manufacturing the semiconductor device. It is possible to increase a lateral resistance without changing the total amount of electric charges in the uppermost surface p-type diffusion layer by using an uppermost surface p-type diffusion layer configuring a double-RESURF structure being formed so that high concentration regions with a deep diffusion depth and low concentration regions with a shallow diffusion depth are alternately arranged adjacent to each other. As a result, it is possible to reduce a displacement current generated by dV/dt noise.Type: GrantFiled: May 15, 2013Date of Patent: July 29, 2014Assignee: Fuji Electric Co., Ltd.Inventor: Akihiro Jonishi
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Patent number: 8791512Abstract: An imaging device is formed in a semiconductor substrate. The device includes a matrix array of photosites. Each photosite is formed of a semiconductor region for storing charge, a semiconductor region for reading charge specific to said photosite, and a charge transfer circuit configured so as to permit a transfer of charge between the charge storage region and the charge reading region. Each photosite further includes at least one buried first electrode. At least one part of that buried first electrode bounds at least one part of the charge storage region. The charge transfer circuit for each photosite includes at least one second buried electrode.Type: GrantFiled: September 23, 2011Date of Patent: July 29, 2014Assignees: STMicroelectronics (Crolles 2) SAS, STMicroelectronics SAInventors: Francois Roy, Julien Michelot
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Patent number: 8791513Abstract: A metal wiring suitable for a substrate of large size is provided. The present invention is characterized in that at least one layer of conductive film is formed on an insulating surface, a resist pattern is formed on the conductive film, and the conductive film having the resist pattern is etched to form a metal wiring while controlling its taper angle ? in accordance with the bias power density, the ICP power density, the temperature of lower electrode, the pressure, the total flow rate of etching gas, or the ratio of oxygen or chlorine in etching gas. The thus formed metal wiring has less fluctuation in width or length and can satisfactorily deal with an increase in size of substrate.Type: GrantFiled: May 7, 2012Date of Patent: July 29, 2014Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Koji Ono, Hideomi Suzawa
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Patent number: 8791514Abstract: An apparatus and method to decrease light saturation in a photosensor array and increase detection efficiency uses a light distribution profile from a scintillator-photodetector geometry to configure the photosensor array to have a non-uniform sensor cell pattern, with varying cell density and/or varying cell size and shape. A solid-state photosensor such as a SiPM sensor having such a non-uniform cell structure realizes improved energy resolution, higher efficiency and increased signal linearity. In addition the non-uniform sensor cell array can have improved timing resolution due to improvements in statistical fluctuations. A particular embodiment for such photosensors is in PET medical imaging.Type: GrantFiled: July 2, 2012Date of Patent: July 29, 2014Assignees: Siemens Medical Solutions USA, Inc., Siemens AktiengesellschaftInventors: Debora Henseler, Ronald Grazioso, Nan Zhang
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Patent number: 8791515Abstract: Provided are spin field effect logic devices, the logic devices including: a gate electrode; a channel formed of a magnetic material above the gate electrode to selectively transmit spin-polarized electrons; a source on the channel; and a drain and an output electrode on the channel outputting electrons transmitted from the source. The gate electrode may control a magnetization state of the channel in order to selectively transmit the electrons injected from the source to the channel.Type: GrantFiled: June 11, 2013Date of Patent: July 29, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Ki-ha Hong, Jong-seob Kim, Jai-Kwang Shin
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Patent number: 8791516Abstract: A semiconductor device having a novel structure is provided. The semiconductor device includes a first p-type transistor, a second n-type transistor, a third transistor, and a fourth transistor. One of a source and a drain of the third transistor is connected to a wiring supplying first potential, and the other is connected to one of a source and a drain of the first transistor. One of a source and a drain of the second transistor is connected to the other of the source and the drain of the first transistor, and the other is connected to one of a source and a drain of the fourth transistor. The other of the source and the drain of the fourth transistor is connected to a wiring supplying second potential lower than the first potential. An oxide semiconductor material is used in channel formation regions of the third transistor and the fourth transistor.Type: GrantFiled: May 16, 2012Date of Patent: July 29, 2014Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Kazuaki Ohshima
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Patent number: 8791517Abstract: According to one embodiment, a semiconductor device includes at least one semiconductor region provided in a semiconductor substrate, and a capacitor group including a plurality of capacitors provided in the semiconductor region, each capacitor including a capacitor insulating film provided on the semiconductor region, a capacitor electrode provided on the capacitor insulating film, and at least one diffusion layer provided in the semiconductor region adjacent to the capacitor electrode.Type: GrantFiled: March 21, 2011Date of Patent: July 29, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Hiroyuki Kutsukake, Yoshiko Kato, Yoshihisa Watanabe, Koichi Fukuda, Kazunori Masuda
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Patent number: 8791518Abstract: A method for manufacturing a semiconductor device is disclosed. In the method for manufacturing the semiconductor device, a capacitor structure is modified to ensure capacitance of the capacitor, and the height of the capacitor is reduced to prevent defects such as a leaning capacitor or a poor bridge from being generated, such that the fabrication process of semiconductor devices is simplified and therefore the semiconductor devices can be stably manufactured.Type: GrantFiled: January 10, 2012Date of Patent: July 29, 2014Assignee: Hynix Semiconductor Inc.Inventor: Sang Heon Kim
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Patent number: 8791519Abstract: A transition metal oxide dielectric material is doped with a non-metal in order to enhance the electrical properties of the metal oxide. In a preferred embodiment, a transition metal oxide is deposited over a bottom electrode and implanted with a dopant. In a preferred embodiment, the metal oxide is hafnium oxide or zirconium oxide and the dopant is nitrogen. The dopant can convert the crystal structure of the hafnium oxide or zirconium oxide to a tetragonal structure and increase the dielectric constant of the metal oxide.Type: GrantFiled: May 7, 2010Date of Patent: July 29, 2014Assignee: Micron Technology, Inc.Inventors: Jiutao Li, Shuang Meng
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Patent number: 8791520Abstract: Provided are nonvolatile memory devices and a method of forming the same. A tunnel insulating pattern is provided on a substrate, and a floating gate is provided on the tunnel insulating pattern. A floating gate cap having a charge trap site is provided on the floating gate, and a gate dielectric pattern is provided on the floating gate cap. A control gate is provided on the gate dielectric pattern.Type: GrantFiled: January 7, 2011Date of Patent: July 29, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Jaeduk Lee, Albert Fayrushin, ByungKyu Cho, Jungdal Choi, Sunghoi Hur, Kwang Soo Seol, Dohyun Lee
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Patent number: 8791521Abstract: A semiconductor device includes an interelectrode insulating film formed between a charge storage layer and a control electrode layer. The interelectrode insulating film is formed in a first region above an upper surface of an element isolation insulating film, a second region along a sidewall of the charge storage layer, and a third region above an upper surface of the charge storage layer. The interelectrode insulating film includes a first stack including a first silicon nitride film or a high dielectric constant film interposed between a first and a second silicon oxide film or a second stack including a second high dielectric constant film and a third silicon oxide film, and a second silicon nitride film formed between the control electrode layer and the first or the second stack. The second silicon nitride film is relatively thinner in the third region than in the first region.Type: GrantFiled: March 19, 2012Date of Patent: July 29, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Koji Nakahara, Kazuhiro Matsuo, Masayuki Tanaka, Hirofumi Iikawa
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Patent number: 8791522Abstract: A non-volatile memory and a manufacturing method thereof are provided. A first oxide layer having a protrusion is formed on a substrate. A pair of doped regions is formed in the substrate at two sides of the protrusion. A pair of charge storage spacers is formed on the sidewalls of the protrusion. A second oxide layer is formed on the first oxide layer and the charge storage spacers. A conductive layer is formed on the second oxide layer.Type: GrantFiled: October 12, 2011Date of Patent: July 29, 2014Assignee: MACRONIX International Co., Ltd.Inventors: Chih-Chieh Cheng, Shih-Guei Yan, Cheng-Hsien Cheng, Wen-Jer Tsai
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Patent number: 8791523Abstract: A nonvolatile semiconductor storage device includes: a structural body; semiconductor layers; a memory film; a connecting member; and a conductive member. The structural body is provided above a memory region of a substrate including the memory region and a non-memory region, and includes electrode films stacked along a first axis perpendicular to a major surface of the substrate. The semiconductor layers penetrate through the structural body along the first axis. The memory film is provided between the electrode films and the semiconductor layer. The connecting member is provided between the substrate and the structural body and connected to respective end portions of two adjacent ones of the semiconductor layers. The conductive member is provided between the substrate and the connecting member, extends from the memory region to the non-memory region, includes a recess provided above the non-memory region, and includes a first silicide portion provided in the recess.Type: GrantFiled: March 16, 2012Date of Patent: July 29, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Hiromitsu Iino, Tadashi Iguchi
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Patent number: 8791524Abstract: According to one embodiment, a method is disclosed for manufacturing a nonvolatile semiconductor memory device. The method can includes forming a semiconductor layer containing an impurity and forming a pattern on the semiconductor layer. The method can include forming first insulating layers in a stripe shape from a surface of the semiconductor layer toward an inside and forming a first insulating film on the semiconductor layer and on the first insulating layers to form a stacked body including electrode layers on the first insulating film. The method can include forming a pair of holes in the stacked body and forming a space portion connected to a lower end of the holes. The method can include forming a memory film on a side wall of the holes. In addition, the method can include forming a channel body layer on a surface of the memory film.Type: GrantFiled: March 16, 2012Date of Patent: July 29, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Daigo Ichinose, Hanae Ishihara
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Patent number: 8791525Abstract: A power semiconductor device that includes a stack of a thin metal layer and a thick metal layer over the active region thereof, and a method for the fabrication thereof.Type: GrantFiled: February 25, 2008Date of Patent: July 29, 2014Assignee: International Rectifier CorporationInventors: Robert Montgomery, Hugo Burke, Philip Parsonage, Susan Johns, David Paul Jones
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Patent number: 8791526Abstract: A vertical type integrated circuit device includes a substrate and a pillar vertically protruding from the substrate. The pillar includes a lower impurity region and an upper impurity region therein and a vertical channel region therebetween. A portion of the pillar including the lower impurity region therein includes a mesa laterally extending therefrom. The device further includes a first conductive line extending on a first sidewall of the pillar and electrically contacting the lower impurity region, and a second conductive line extending on a second sidewall of the pillar adjacent the vertical channel region. The second conductive line extends in a direction perpendicular to the first conductive line and is spaced apart from the mesa. Related devices and methods of fabrication are also discussed.Type: GrantFiled: September 28, 2010Date of Patent: July 29, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Jae-man Yoon, Hyeong-sun Hong, Kwang-youl Chun, Makoto Yoshida, Deok-sung Hwang, Chul Lee
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Patent number: 8791527Abstract: An integrated circuit including one or more transistors in which source and drain regions are formed as embedded silicon-germanium (eSiGe). Guard ring structures in the integrated circuit are formed in single-crystal silicon, rather than in eSiGe. In one example, p-channel MOS transistors have source/drain regions formed in eSiGe, while the locations at which p-type guard rings are formed are masked from the recess etch and the eSiGe selective epitaxy. Defects caused by concentrated crystal strain at the corners of guard rings and similar structures are eliminated.Type: GrantFiled: April 23, 2012Date of Patent: July 29, 2014Assignee: Texas Instruments IncorporatedInventor: Gregory Charles Baldwin
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Patent number: 8791528Abstract: A method of manufacturing a microelectronic device including forming a dielectric layer surrounding a dummy feature located over a substrate, removing the dummy feature to form an opening in the dielectric layer, and forming a metal-silicide layer conforming to the opening. The metal-silicide layer may then be annealed.Type: GrantFiled: August 23, 2010Date of Patent: July 29, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Tung Lin, Chih-Wei Chang, Chii-Ming Wu, Mei-Yun Wang, Chaing-Ming Chuang, Shau-Lin Shue
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Patent number: 8791529Abstract: An object is to provide a field effect transistor (FET) having a conductor-semiconductor junction, which has excellent characteristics, which can be manufactured through an easy process, or which enables high integration. Owing to the junction between a semiconductor layer and a conductor having a work function lower than the electron affinity of the semiconductor layer, a region into which carriers are injected from the conductor is formed in the semiconductor layer. Such a region is used as an offset region of the FET or a resistor of a semiconductor circuit such as an inverter. Further, in the case of setting up such an offset region and a resistor in one semiconductor layer, an integrated semiconductor device can be manufactured.Type: GrantFiled: April 2, 2013Date of Patent: July 29, 2014Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Yasuhiko Takemura
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Patent number: 8791530Abstract: A compliant micro device transfer head and head array are disclosed. In an embodiment a micro device transfer head includes a spring arm having integrated electrode leads that is deflectable into a space between a base substrate and the spring arm.Type: GrantFiled: September 6, 2012Date of Patent: July 29, 2014Assignee: LuxVue Technology CorporationInventors: Andreas Bibl, Dariusz Golda
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Patent number: 8791531Abstract: A package is provided. The package has a substrate and a cover. A MEMS die is provided having a diaphragm. A CMOS die is provided wherein at least a portion of the CMOS die is positioned between the diaphragm and the substrate.Type: GrantFiled: October 21, 2011Date of Patent: July 29, 2014Assignee: Knowles Electronics, LLCInventors: Peter V. Loeppert, David Giesecke, Anthony Minervini, Jeffrey Niew, Lawrence Grunert
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Patent number: 8791532Abstract: The sensor assembly comprises a substrate (1), such as a flexible printed circuit board, and a sensor chip (2) flip-chip mounted to the substrate (1), with a first side (3) of the sensor chip (2) facing the substrate (1). A sensing area (4) and contact pads (5) are integrated on the first side (3) of the sensor chip (2) and located in a chamber (17) between the substrate (1) and the sensor chip (2). Chamber (17) is bordered along at least two sides by a dam (16). Underfill (18) and/or solder flux is arranged between the sensor chip (2) and the substrate (1), and the dam (16) prevents the underfill from entering the chamber (17). An opening (19) extends from the chamber to the environment and is located between the substrate (1) and the sensor chip (2) or extends through the sensor chip (2).Type: GrantFiled: November 18, 2009Date of Patent: July 29, 2014Assignee: Sensirion AGInventors: Markus Graf, Werner Hunziker, Franziska Brem, Felix Mayer
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Patent number: 8791533Abstract: There are disclosed herein various implementations of semiconductor packages having an interposer configured for magnetic signaling. One exemplary implementation includes a die transmit pad in an active die for transmitting a magnetic signal corresponding to a die electrical signal produced by the active die, and an interposer magnetic tunnel junction (MTJ) pad in the interposer for receiving the magnetic signal. A sensing circuit is coupled to the interposer MTJ pad for producing a receive electrical signal corresponding to the magnetic signal. In one implementation, the sensing circuit is configured to sense a resistance of the interposer MTJ pad and to produce the receive electrical signal according to the sensed resistance.Type: GrantFiled: January 30, 2012Date of Patent: July 29, 2014Assignee: Broadcom CorporationInventors: Xiangdong Chen, Sam Ziqun Zhao, Kevin Kunzhong Hu, Sampath K. V. Karikalan, Rezaur Rahman Khan, Pieter Vorenkamp
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Patent number: 8791534Abstract: In a perpendicular magnetization domain wall motion MRAM in which the magnetizations of both ends of a magnetization free layer are pinned by magnetization pinned layers, the increase of a write current due to leakage magnetic field from the magnetization pinned layer is prevented. A first displacement is present between a first boundary line and a first vertical line, where a curve portion, which crosses a first magnetization free layer, of an outer circumferential line of a first magnetization pinned layer is the first boundary line, a segment which links a center of a magnetization free region and a center of a first magnetization pinned region is a first segment, and a segment, which is a vertical line of the first segment, and which comes in contact with the first boundary line is the first vertical line.Type: GrantFiled: June 16, 2011Date of Patent: July 29, 2014Assignee: NEC CorporationInventors: Shunsuke Fukami, Tetsuhiro Suzuki, Kiyokazu Nagahara, Nobuyuki Ishiwata, Norikazu Ohshima
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Patent number: 8791535Abstract: A memory includes a semiconductor substrate. Magnetic tunnel junction elements are provided above the semiconductor substrate. Each of the magnetic tunnel junction elements stores data by a change in a resistance state, and the data is rewritable by a current. Cell transistors are provided on the semiconductor substrate. Each of the cell transistors is in a conductive state when the current is applied to the corresponding magnetic tunnel junction element. Gate electrodes are included in the respective cell transistors. Each of the gate electrodes controls the conductive state of the corresponding cell transistor. In active areas, the cell transistors are provided, and the active areas extend in an extending direction of intersecting the gate electrodes at an angle of (90?atan(?)) degrees.Type: GrantFiled: August 19, 2013Date of Patent: July 29, 2014Assignee: Kabushiki Kaisha ToshibaInventor: Yoshiaki Asao
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Patent number: 8791536Abstract: Disclosed herein is a stacked chip package including an image sensor including a recess formed on a surface thereof, and a digital signal processor chip that is positioned within the recess. Also disclosed herein is a method of fabricating a stacked chip package including the steps of forming a recess on a surface of an image sensor and positioning a digital signal processor in the recess of the image sensor.Type: GrantFiled: January 18, 2012Date of Patent: July 29, 2014Assignee: Aptina Imaging CorporationInventors: Larry Kinsman, Yu Te Hsieh
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Patent number: 8791537Abstract: Disclosed is a flexible radiation detector including a substrate, a switching device on the substrate, an energy conversion layer on the switching device, a top electrode layer on the energy conversion layer, a first phosphor layer on the top electrode layer, and a second phosphor layer under the substrate.Type: GrantFiled: April 26, 2012Date of Patent: July 29, 2014Assignee: Industrial Technology Research InstituteInventors: Issac Wing-Tak Chan, Chao-Chiun Liang, Heng-Yin Chen, Ming-Hua Yeh
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Patent number: 8791538Abstract: A light receiving region includes a plurality of light detecting sections 10. The light detecting sections 10 has a second contact electrode 4A. The second contact electrode 4A is arranged at a position overlapping a first contact electrode 3A, so as to contact the first contact electrode. Further, a resistive layer 4B is continued to the second contact electrode 4A.Type: GrantFiled: October 19, 2012Date of Patent: July 29, 2014Assignee: Hamamatsu Photonics K.K.Inventors: Koei Yamamoto, Terumasa Nagano, Kazuhisa Yamamura, Kenichi Sato, Ryutaro Tsuchiya
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Patent number: 8791539Abstract: Ultra-thin semiconductor devices, including piezoresistive sensing elements can be formed in a wafer stack that facilitates handling many thin device dice at a wafer level. Three embodiments are provided to form the thin dice in a wafer stack using three different fabrication techniques that include anodic bonding, adhesive bonding and fusion bonding. A trench is etched around each thin die to separate the thin die from others in the wafer stack. A tether layer, also known as a tether, is used to hold thin dice or dice in a wafer stack. Such as wafer stack holds many thin dice together at a wafer level for handling and enables easier die picking in packaging processes.Type: GrantFiled: February 24, 2012Date of Patent: July 29, 2014Assignee: Continental Automotive Systems, Inc.Inventors: Xiaoyi Ding, Jeffrey J. Frye, Gregory A. Miller
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Patent number: 8791540Abstract: Ultra-thin semiconductor devices, including piezo-resistive sensing elements can be formed a wafer stack that facilitates handling many thin device dice at a wafer level. Three embodiments are provided to form the thin dice in a wafer stack using three different fabrication techniques that include anodic bonding, adhesive bonding and fusion bonding. A trench is etched around each thin die to separate the thin die from others in the wafer stack. A tether layer, also known as a tether, is used to hold thin dice or dice in a wafer stack. Such as wafer stack holds many thin dice together at a wafer level for handling and enables easier die picking in packaging processes.Type: GrantFiled: February 24, 2012Date of Patent: July 29, 2014Assignee: Continental Automotive Systems, Inc.Inventors: Xiaoyi Ding, Jeffrey J. Frye, Gregory A. Miller
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Patent number: 8791541Abstract: Provided is a method of fabricating a backside illuminated image sensor that includes providing a device substrate having a frontside and a backside, where pixels are formed at the frontside and an interconnect structure is formed over pixels, forming a re-distribution layer (RDL) over the interconnect structure, bonding a first glass substrate to the RDL, thinning and processing the device substrate from the backside, bonding a second glass substrate to the backside, removing the first glass substrate, and reusing the first glass substrate for fabricating another backside-illuminated image sensor.Type: GrantFiled: July 5, 2012Date of Patent: July 29, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuan-Chieh Huang, Dun-Nian Yaung, Chih-Jen Wu, Chen-Ming Huang
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Patent number: 8791542Abstract: According to an embodiment, a solid-state imaging device includes a photoelectric, conversion element. The photoelectric conversion element includes a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer. In the solid-state imaging device, D2m3/L2m3×ni32/N2<D1M2/L1M2×ni22/N2 and D1m1/L1m1×ni12/N1<D1m2/L1m2×ni22/N1 are established.Type: GrantFiled: December 28, 2012Date of Patent: July 29, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Shuichi Toriyama, Koichi Kokubun, Hiroki Sasaki