Abstract: A local coil and a magnetic resonance imaging system are provided. The local coil includes an antenna part, an adjustment part and a transmission part. The antenna part includes a first capacitor connected in series for adjusting a frequency of the antenna part. The adjustment part includes a tuning/detuning diode and is connected in parallel to the first capacitor, and the tuning/detuning diode is used for adjusting tuning and detuning of the antenna part. The transmission part includes a radio-frequency transmission line that connects the antenna part and the adjustment part, and the transmission part provides a phase difference of an odd multiple of 180° between the antenna part and the tuning/detuning diode.

Abstract: A device includes: a static magnetic field generating device including static magnetic field generating sources generating a homogeneous magnetic field in a space; gradient magnetic field generating sources superimposing a gradient magnetic field on the homogeneous magnetic field, and conductor rings arranged between the static magnetic field generating sources and the gradient magnetic field generating sources in a pair of arranging regions on both sides in a direction of the homogeneous magnetic field in a region where the homogeneous magnetic field is generated (imaging region), respectively, the conductor rings being separated from each other and making a pair. The conductor rings are mechanically connected to the gradient magnetic field generating device or the static magnetic field generating device. This provides an MRI device 1 capable of reduction in vibration with suppression of the image quality deterioration of the tomographic images.

Abstract: Discriminating between a cable locating signal and a false cable locating signal is described. A reference signal, which contains a locating signal frequency impressed on it, is transmitted in a way which provides for detection of a phase shift between the locating signal and the false locating signal. Based on the phase shift, a receiver is used to distinguish the locating signal from the false locating signal.

Abstract: A method is disclosed as part of an overall process in which a boring tool is moved through the ground within a given region along a particular path in an orientation which includes pitch. A locating signal is transmitted from the boring tool which signal exhibits a field defined forward point within a reference surface which field defined forward point is vertically above an inground forward point on the particular path through which the boring tool is likely to pass. The method establishes a predicted depth of the boring tool at the inground forward point by first identifying the field defined forward point. The signal strength of the locating signal is then measured at the field defined forward point as being representative of the depth of the boring tool at an inground upstream point which is the current location of the boring tool. With the boring tool at the upstream inground point, the pitch of the boring tool is determined.

Abstract: The invention relates to a device for measuring an electric current between a vehicle battery and an electrical consumer connected to the vehicle battery. The claimed device includes a bus bar which picks up the electric current in the vehicle battery and guides it further to the electrical consumer, on which a first current sensor and a second current sensor which is different from the first current sensor are arranged, the current sensors being designed to measure, independently from each other, the electric current circulating in the bus bar.

Abstract: A method of testing a secondary battery includes step A of charging the secondary battery to a predetermined charge voltage, step B of setting aside the secondary battery for a predetermined time (tb) after the step A, step C of discharging the secondary battery to a predetermined discharge voltage after the step B, and step D of detecting a battery voltage increase for a preset time (t2) after a predetermined time (t1) has elapsed after the step C. This method of testing a secondary battery can evaluate a measurement of how much the negative electrode active material layer covers the positive electrode active material layer based on the battery voltage increase detected in the step D.

Abstract: Methods and systems for determining a target temperature and/or adjusting a temperature associated with a battery, such as a vehicle battery. In some implementations of such methods, a temperature-scaled battery capacity of at least a portion of a battery may be determined at a measured temperature. The temperature-scaled battery capacity may be compared with a capacity threshold and, upon determining that the temperature-scaled battery capacity is below the capacity threshold, a target battery temperature for the at least a portion of the battery may be determined and/or set.

Abstract: A method and apparatus that reduce common mode variations experienced by a voltage sensing component. A measurement component such as a BATFET or an external sensing resistor, receives, at its source, a voltage from the top of a battery having a voltage VPH_PWR. A voltage sensing component, such as an ADC, is powered by the voltage from the battery. A power referenced component, such as a power referenced LDO, tracks the voltage from the battery and outputs the tracked voltage minus a predetermined voltage amount to a negative side of the voltage sensing component.

Abstract: A processing device for a battery pack including a plurality of batteries has a voltage detection section configured to detect the voltage of each of the batteries, a first processing section configured to perform first processing for discharging the battery pack, and a second processing section configured to perform second processing for individually charging the batteries. The second processing section is configured to suppress a voltage drop by performing the second processing on the battery of which the voltage value has been reduced to a first predetermined value during the discharging in the first processing.

Abstract: A method for determining a circuit element parameter in a ground fault circuit interrupter circuit. An electrical signal provided to a first node is used to generate another electrical signal at a second node. The electrical signal at the second node is multiplexed with a modulation signal to generate a modulated signal that is then filtered and converted into a digital representation of a portion of the circuit element parameter. The electrical signal at the second node is multiplexed with the modulation signal after it has been phase shifted to produce a modulated signal that is filter and converted into a digital representation of another portion of the circuit element parameter. In another aspect, a slope based solenoid self-test method is used for self-testing in a GFCI circuit. Alternatively, a method for determining a wiring fault is provided using a digital filter.

Abstract: The disclosure relates to a method for detecting an arc in a DC circuit. The method includes measuring and analyzing an AC component (IAC) of a current (I) flowing in the circuit and determining at least one parameter of the AC component (IAC). The level of a DC component (IDC) of the current (I) is varied and a degree of correlation between the level of the DC component (IDC) of the current (I) flowing in the DC circuit and the at least one parameter of the AC component (IAC) is determined. An arc is detected and selectively signaled based on the degree of the determined correlation. The disclosure also relates to an apparatus for carrying out the method and to an inverter comprising such an apparatus.

Abstract: Broadband antenna system comprising a plurality of antenna elements and a plurality of amplifiers; wherein every antenna element of said plurality of antenna elements is configured for operating in a predetermined frequency range and is associated with an amplifier of said plurality of amplifiers which is configured for said predetermined frequency range; said plurality of antenna elements covering a broadband range.

Abstract: An antenna device includes a sensor electrode having a capacitance configured to change upon an object approaching or contacting the sensor electrode, a sensor circuit electrically connected to the sensor electrode, an antenna section, and a substrate having the sensor circuit mounted thereon and having the sensor electrode fixed thereto. The sensor circuit is configured to detect the capacitance. The substrate is inserted into the antenna section. This antenna device allows components to be easily positioned during assembly.

Abstract: A method of filling level measurement in a container (12) having a first medium (14) and at least one second medium (16) arranged thereabove, in particular a foam layer, wherein an electromagnetic signal is transmitted, in particular along a probe (28) arranged in the container (12), and a signal curve (S) of the signal reflected in the container (12) is recorded, wherein a signal time of flight (t) up to a border transition (18, 20) to the first medium (14) and/or up to the second medium (16) is determined with reference to the signal curve (S) and a filling level of the first medium (14) and/or a filling level of the second medium (16) is determined from the signal time of flight (t). In this respect, the border transition (18, 20) is recognized from the integral over the signal curve (S), the integral starting from a reference position (t0).

Abstract: A sensor device for detecting a number of objects, has a number of electrode configurations forming a sensor surface, each electrode configuration having a number of measurement electrodes and each electrode configuration being associated with at least one transmitter electrode, and an evaluation device coupled to the measurement electrodes and the transmitter electrodes, which is adapted for using a time multiplexing method for applying an alternating signal to one of the transmitter electrodes, and to apply a predetermined constant electrical potential to the remaining transmitter electrodes, and tapping an electrical signal indicating the position of the object relative to the sensor surface at the measurement electrodes associated with the transmitter electrode having the electrical alternating signal applied.

Abstract: A hybrid sensor includes a proximity sensor section and a load sensor section. The proximity sensor section includes a first base material, a plurality of first front-side electrodes, a plurality of first back-side electrodes, and a protective layer. Each of these members is made of an elastomer. The proximity sensor section detects the approach and coordinates of an object to be detected, based on a change in capacitance between the first front-side electrode and the first back-side electrode which is caused by the approach of the object to be detected. The load sensor section detects pressing and coordinates of the object to be detected, based on a load that is applied from the object to be detected via the proximity sensor section.

Abstract: In one embodiment, a method comprises generating a first current at a current source having a magnitude based on the magnitude of a second current flowing from a capacitive node of a touch sensor in the absence of a touch with respect to the capacitive node. The method further includes generating a third current from the capacitive node of the touch sensor in the presence of a touch with respect to the capacitive node. The first current and the third current are summed to cancel out at least a portion of the third current. The method further includes integrating, by an integrator, the sum of the first current and the third current to generate an output voltage.

Abstract: A moisture meter for determining the moisture content of particulate material is provided. The moisture meter comprises a frame part, a space, a measuring cup disposed within said space for receiving a sample of the particulate material which moisture is to be measured, and moisture measuring means. The moisture meter comprises a swiping means for removing at least partly a part of a sample of particulate material which moisture is to be measured, which part of the sample of particulate material extends out of the inner space of the measuring cup through the open end of the measuring cup. The swiping means are movably attached to the frame part for movement in a swiping path where a swiping member of the swiping means is configured to move essentially along the open end of the measuring cup.

Abstract: A handheld device to detect pathogens may include a handheld impedance sensor to measure impedance of the pathogen having a socket and a sensing circuit being positioned in the socket to provide the pathogen.

Abstract: Hundreds of thousands of concrete bridges and hundreds of billions of tons of concrete require characterization with time for corrosion. Accordingly, protocols for rapid testing and improved field characterization systems that automatically triangulate electrical resistivity and half-cell corrosion potential measurements would be beneficial allowing discrete/periodic mapping of a structure to be performed as well as addressing testing for asphalt covered concrete. Further, it is the low frequency impedance of rebar in concrete that correlates to corrosion state but these are normally time consuming vulnerable to noise. Hence, it would be beneficial to provide a means of making low frequency electrical resistivity measurements rapidly. Further, prior art techniques for electrical rebar measurements require electrical connection be made to the rebar which increases measurement complexity/disruption/repair/cost even when no corrosion is identified.

Abstract: A load testing machines includes: six resistance units; six cooling fans; insulators between the resistance units and the cooling fans; and connection cables, in which: each of the resistance units includes a plurality of steps of resistor groups arranged in a z-direction and each formed of a plurality of rod-shaped resistors parallel to a x-direction connected together in series arranged at predetermined intervals in a y-direction; the six cooling fans face the resistance units, respectively, in the z-direction; the connection cables are cables used for serially and detachably connecting resistor groups next to each other in the y-direction of two resistance units next to each other in the y-direction with an interval of not smaller than a second distance in between; and the insulators each have a size corresponding to the rated voltage of a target power supply of a power supply load test to be conducted using a resistance unit group.

Abstract: A chip-to-chip signal transmission system is provided, which includes a first chip, a second chip, and a dielectric layer. A signal transmission is performed between a transmitter of the first chip and a receiver of the second chip through a transmission-metal-pad unit and a receiving-metal-pad unit. The transmitter transmits a transmission-testing-coupling signal through the transmission-metal-pad unit according to a driving-testing signal when the transmitter receives the driving-testing signal. A first testing unit receives the transmission-testing-coupling signal and outputs a transmission-testing signal according to the transmission-testing-coupling signal. A second testing unit transmits a receiving-testing-coupling signal through the receiving-metal-pad unit according to the driving-testing signal when the second testing unit receives the driving-testing signal.

Abstract: According to one embodiment, a stack includes first and second wiring structures and an inspection circuit. The inspection circuit includes a switching circuit having an input terminal, a drive terminal, and an output terminal electrically connected with a discharge mechanism. The inspection circuit is configured such that, in a state where a first electric connection is made in the first wiring structure and a second electric connection is made in the second wiring structure, at the time of applying charges to first and second electrodes, the charge applied to the second electrode flows to the drive terminal through the second wiring structure to bring the input terminal and the output terminal of the switching circuit into an electrically conducted state, and the charge applied to the first electrode flows to the discharge mechanism through the first wiring structure and the switching circuit.

Abstract: The use of a power sink function in IC testing results in a simple and rapid method for testing ICs, and assembled modules, at elevated temperature profiles without the use of environmental ovens. Testing IC devices at elevated temperatures may be useful for ‘burn-in’, for ‘hot sort’ performance testing that may be used in electronic devices such as DRAM memory, logic, communication devices, and microprocessors. The power sink function may be implemented as an additional isolated area of active devices, or as a section of the circuit that is not involved in the testing procedure. Alternately, the power dissipation circuit may consist of a resistive path between two external pins that are not used for IC operation, where the resistor may be on the IC or on the package. This allows for control of the temperature level and profile by simple adjustment of the voltage between the two external pins.

Abstract: Testing methods and systems are described. One method for testing an electronic device includes providing a probe in electrical contact with a device. The method also includes positioning an interface of the probe and the device in a liquid medium. The method also includes transmitting a current from the probe through the interface while the interface is in the liquid medium. Other embodiments are described and claimed.

Abstract: A semiconductor evaluating device includes a chuck stage for holding a semiconductor device serving as a measuring object, a contact probe for evaluating an electrical characteristic of the semiconductor device by getting contact with the semiconductor device held on the chuck stage, and a fluid spraying portion for spraying a fluid onto the semiconductor device.

Abstract: A probe apparatus has probe wires with a contact pattern on one side. The contact pattern is for contacting a respective contact pattern on another test equipment or component, such as a circuit board. The probe wires have tips that probe a device desired for testing. Signals are transmitted through the probe wires from the probe card, for example, through a circuit board to other diagnostic equipment. The contact of the probe card with the circuit board allows signals to be transferred through the probe wires to the other diagnostic equipment. On another side of the probe card is a connector structure. The connector structure includes a retainer that can allow the probe card to be replaced from a test system, such as allowing it to be connected and disconnected from a holder.

Abstract: A method and apparatus for an enhanced reverberation chamber are disclosed. In one embodiment, one or more positioners are coupled to a tuner, such that when the tuner moves, the positioner moves. A device involved with a test may be mounted to the positioner so that when the positioner moves, the device moves.

Abstract: A startup boot cycle test system for testing a mobile multi-function device under test (DUT) that has a power manager and a main system processor is described. The system includes an external power source and a tester device. The external power source provides an input current to the power manager, which in turn provides a boot current, drawn from the input current, to the main system processor. The tester device connects to a test point in the DUT using a contact test probe to draw a margin current from the boot current. The resulting diminished boot current is used by the processor to boot. The tester device detects whether the processor successfully boots using the diminished boot current using a data input connector connected between the DUT and tester device. Other embodiments are also described and claimed.

Abstract: A testing device includes a test board, a number of locating pins, a pin holder, a number of metal pins, a connector holder, a connector, a number of elastic elements, and a pressure block. The test board is electrically connected with a testing circuit. The locating pins are fixed on the testing board to guide the connector holder. Bottoms of the number of metal pins are vertically fixed in the pin holder. The elastic elements are arranged between the pin holder and the connector holder for pushing the connector holder back to its original position after testing. The connector is set in the connector holder and connected with an electronic device to be tested. The pressure block is positioned above the connector holder and used to push the connector holder down to the pin holder to make the testing contacts in the connector contact the metal pins.

Abstract: A wafer testing probe card includes a printed circuit board, a flexible circuit board, an elastic piece, and a probe unit. The flexible circuit board is electrically connected to the printed circuit board. The elastic piece is disposed between the printed circuit board and the flexible circuit board. The probe unit includes a probe head and a plurality of probes. The probe head is fixed on the printed circuit board and has a plurality of through holes. The probes respectively pass through the through holes and move up and down relative to the probe head.

Abstract: Some embodiments relate to a method for semiconductor processing. In this method, a semiconductor wafer is provided. A surface region of the semiconductor wafer is probed to determine whether excess charge is present on the surface region. Based on whether excess charge is present, selectively inducing a corona discharge to reduce the excess charge. Other techniques are also provided.

Abstract: A fault detecting circuit in a string of LEDs D1-Dc containing comparing operational amplifiers IC1/IC2 connected to a current source is divided into sections, D1-Da, D2-Db, and D3-Dc, wherein the common between the Da cathode and the D2 anode is connected to the noninverting input of IC1, while the common between the Db cathode and the D3 anode is connected to the noninverting input of IC2, and to the string D1-Db is connected in parallel to a divider comprising R1/R2, while the string comprising D2-Dc is connected in parallel to a divider comprising R3/R4, and the common of R1/R2 is connected to the inverting input of IC1 and the common of R3/R4 is connected to the inverting input of IC2, while the outputs of IC1/IC2 are connected to the bases of corresponding transistors T1/T2, whose emitters are connected to ground and collectors are connected to the voltage source and also to the output terminal.

Abstract: Systems and methods for determining a malfunctioning device in a plasma system, are described. One of the methods includes receiving an indication whether plasma is generated within a plasma chamber of the plasma system. The plasma system includes a processing portion and a power delivery portion. The method further includes determining whether the plasma system operates within constraints in response to receiving the indication that the plasma is generated, determining a value of a variable at an output of the power delivery portion when the processing portion is decoupled from the power delivery portion, and comparing the determined value with a pre-recorded value of the variable. The method includes determining whether the determined value is outside a range of the pre-recorded value and determining that the malfunctioning device within the power delivery portion upon determining that the determined value is outside the range of the pre-recorded value.

Abstract: A redriver chip is inserted between a transmitter chip and a receiver chip and re-drives differential signals from the transmitter chip to the receiver chip. The redriver chip has switched output termination that switches to a high value to detect far-end termination at the receiver chip, and to a low value for signaling. An output detector detects when the receiver chip has termination to ground and enables switched input termination to provide termination to ground on the lines back to the transmitter chip so that the far-end termination on the receiver chip is mirrored back to the transmitter chip, hiding the redriver chip. An input signal detector detects when the transmitter chip begins signaling and enables an equalizer, limiter, pre-driver, and output stage to re-drive the signals to the receiver chip. The input signal detector also causes the switched output termination to switch to the low value termination for signaling.

Abstract: Integrated circuits with sequential logic circuitry are provided. Sequential logic circuitry may include a chain of bypassable clocked storage elements coupled between a speed critical input terminal and a speed critical output terminal. Combinational logic circuits may be interposed between each adjacent pair of bypassable clocked storage elements in the chain. Dynamic voltage-frequency scaling (DVFS) control circuitry may provide an adjustable power supply voltage to the combinational logic circuits and may provide an adjustable clock signal to control the clocked storage elements. The DVFS control circuitry may be used to selectively enable at least some of the bypassable clocked storage elements while disabling other bypassable clocked storage elements so that the power supply voltage can be reduced while maintaining the same operating frequency. The power supply voltage and the frequency of the clock signal can be adjusted to provide the desired voltage-frequency tradeoff.

Abstract: A system on chip (SoC) has a nonvolatile memory array of n rows by m columns coupled to one or more of the core logic blocks. M is constrained to be an odd number. Each time a row of m data bits is written, parity is calculated using the m data bits. Before storing the parity bit, it is inverted. Each time a row is read, parity is checked to determine if a parity error is present in the recovered data bits. A boot operation is performed on the SoC when a parity error is detected.

Abstract: A novel method for designing an integrated circuit (“IC”) by rescaling an original set of circuits in a design of the IC is disclosed. The original set of circuits to be rescaled includes sequential nodes, combinational nodes, and interconnects. Each sequential node is associated with a phase of a clock. The method generates a rescaled set of circuits that includes multiple replica sets of the circuits. Each replica set of circuits includes sequential nodes, combinational nodes, and interconnects that are identical to nodes and interconnects in the original set of circuits. Each sequential node is associated with a phase of a clock that is at a fraction of the phase of its corresponding sequential element in the original set. The method connects nodes in each replica set of circuits to a logically equivalent node in another replica set. The method replaces the original set of circuits with the rescaled set of circuits.

Abstract: An integrated circuit (“IC”) that includes a configurable routing fabric with controllable storage elements is described. The routing fabric provides a communication pathway that routes signals to and from source and destination components. The routing fabric may provide the ability to selectively store the signals passing through the routing fabric within the storage elements of the routing fabric. In this manner, a source or destination component may continually perform operations (e.g., computational or routing) irrespective of whether a previous signal from or to such a component is stored within the routing fabric. The source and destination components include configurable logic circuits, configurable interconnect circuits, and various other circuits that receive or distribute signals throughout the IC.

Abstract: A configurable logic block (CLB) and an operation method of the CLB are provided. The CLB includes memory units and a selecting circuit. The memory unit includes a first resistive non-volatile memory (RNVM) element and a second RNVM element. Top electrodes (TEs) of the first and second RNVM elements are coupled to an output terminal of the memory unit. Bottom electrodes (BEs) of the first and second RNVM elements are respectively coupled to a first bias terminal and a second bias terminal of the memory unit. The selecting circuit selects one of the memory units according to an input logic value and determines an output logic value of the CLB according to an output logic value of the selected memory unit.

Abstract: In accordance with one aspect of the invention, a hole is formed within an LE array of a PLD by interrupting the LE array base signal routing architecture such that a hole is left for IP function block to be incorporated. An interface region is provided for interfacing the remaining LE array base signal routing architecture to the IP function block.

Abstract: A level shifter and integrated level shifter and metastability resolution flop circuit are disclosed. A circuit includes a generation circuit, in a first voltage domain, coupled to receive a logic signal via a single-ended input and configured to generate true and complementary values of the logic signal. The circuit further includes a storage circuit coupled to receive the true and complementary values of the logic signal from the generation circuit. The storage circuit is configured to store the true and complementary values of the logic signal. The storage circuit is in a second voltage domain. The circuit further includes an output circuit coupled to the storage circuit and configured to provide a differential output signal having true and complementary values corresponding to the true and complementary values of the logic signal. The circuit may be combined with a latch circuit coupled to receive the differential output signal.

Abstract: Described herein is a high-voltage level-shifter (HVLS) that can be used for both NMOS and PMOS bridges, exhibits a higher voltage tolerance for over-clocking than traditional level-shifters, has reduced crowbar current in its input driver, and no contention in its output driver. The HVLS comprises an input driver including a first signal conditioning unit, the input driver operating on a first power supply level and for conditioning an input signal as a first signal in the first signal conditioning unit; and a circuit to receive the first signal and to provide a second signal based at least in part on the first signal, the second signal being level-shifted from the first power supply level to a second power supply level, wherein the second power supply level is higher than the first power supply level.

Abstract: The present disclosure provides for a clock distribution network for distributing clocking signals within a synchronous sequential logic circuit. The clock distribution network distributes the one or more clock signals by inductively and/or capacitively coupling a clocking signal from a primary distribution node to various secondary distribution nodes within the synchronous sequential logic circuit. The various secondary distribution nodes resonate at respective resonant frequencies to generate other clocking signals for use within the synchronous sequential logic circuit in response to receiving the clocking signal.

Abstract: In an exemplary implementation, a detection circuit for regulating a power converter is configured to receive a combined sense signal comprising a first sense signal from the power converter superimposed with a second sense signal from the power converter. The detection circuit is further configured to generate a first detect signal from the combined sense signal and generate a second detect signal from the combined sense signal. The first detect signal can correspond to the first sense signal and the second detect signal can correspond to the second sense signal. The detection circuit can generate a filtered signal corresponding to the first sense signal from the combined sense signal to generate the first detect signal from the combined sense signal. Also, the detection circuit can generate an offset signal based on the combined sense signal to generate the second detect signal from the combined sense signal.

Abstract: The present invention provides for a differential driver for transmitting a differential signal including: a first power source to supply a first voltage; a second power source to supply a second voltage that is less than the first voltage; a current steering circuit coupled between the first power source and the second power source, the current steering circuit for steering a current into either a positive differential output node or a negative differential output node to transmit the differential signal according to a data signal and a dataN signal; a resistor interposed between the first power source and the current steering circuit; and a constant current sink interposed between the current steering circuit and the second power source, the constant current sink for sinking the current having a substantially constant value, in which, the dataN signal is the inverse of the data signal.

Abstract: A gate/source driving apparatus includes a first gate/source driving chip and a second gate/source driving chip. The first gate/source driving chip includes a plurality of first charge pump circuits, each of which has a voltage input end, a voltage output end, a first capacitor end, and a second capacitor end. The second gate/source driving chip includes a plurality of second charge pump circuits, each of which also has a voltage input end, a voltage output end, a first capacitor end, and a second capacitor end. The voltage output end of at least one of the first charge pump circuits is coupled to the voltage input end of at least one of the second charge pump circuits.

Abstract: Current drivers and biasing circuitry at least partly compensate for manufacturing variations and environmental variations such as supply voltage, temperature, and fabrication process.

Abstract: An electronic device has a power control module for causing selected functional blocks to run in a low power mode of operation, while leaving other functional blocks supplied continuously with power. A power mode control distribution network includes serially connected chains of buffers in a distribution tree for distributing power mode control signals received at a common input end to respective output ends which are connected to respective functional blocks. In the low power mode of operation the power control module causes power to be supplied continuously to output buffers at the output ends of the chains while causing power supplied to other buffers to be reduced or cut-off. The output buffers include feedback paths for causing the states of the output buffers prior to the low power mode of operation to latch during the low power mode of operation.

Abstract: Techniques including methods and apparatus for calibrating a local clock are provided in an implantable medical device. The implantable medical device includes a telemetry module for receiving a remote signal transmitted by an external device. The received signal is provided to a clocking circuit having a clocking circuit for computation of a calibration factor based on a difference between phases of the clock signal generated by the local clock and transitions in the received remote signal. The calibration factor may be derived as a function of an edge of the clock signal lagging or leading relative to a corresponding edge of the remote signal.