Abstract: A PLL includes an oscillator, multiple time-to-digital converters (TDCs) and a system for the remaining functionality. The TDCs measure the oscillator's phase against respective multiple reference clocks. The system compares the respective measured phases with respective desired phases to obtain phase error signals. One is selected to close the loop. The others are monitored and adjusted when not equal to zero. When a new reference clock must be used, the loop is changed from including the old phase error signal to the new. The old phase error was zero because the loop was in lock, the new phase error is zero because it was monitored and adjusted. Therefore, upon switching the loop from the old to the new phase error signal, the loop remains locked and switching is hitless.

Abstract: A rotational synchronizer for metastability resolution is disclosed. A synchronizer includes a plurality of M+1 latches each coupled to receive data through a common data input. The synchronizer further includes a multiplexer having a N inputs each coupled to receive data from an output of a corresponding one of the M+1 latches, and an output, wherein the multiplexer is configured to select one of its inputs to be coupled to the output. A control circuit is configured to cause the multiplexer to sequentially select outputs of the M+1 latches responsive to N successive clock pulses, and further configured to cause the M+1 latches to sequentially latch data received through the common data input.

Abstract: An integrated circuit package including an induction-coupled clock distribution system is disclosed. An exemplary embodiment of the disclosure includes a transmission module coupled to a main clock line, a clock reception module coupled to the transmission module, the clock reception module including a clock output line, and an electronic circuit coupled to the clock output line of the clock reception module, the electronic circuit including at least one clocked element and configured to operate synchronously with a clocking signal received through the clock output line of the clock reception module. The transmission module may be disposed on the supporting case of the IC package, and the electronic circuit and the clock reception module may be disposed on the semiconductor die of the IC package.

Abstract: One or more techniques or systems for locking a phase locked loop (PLL) are provided herein. In some embodiments, a multi-phase time-to-digital converter (TDC) includes a first phase finder, a phase predictor, a second phase finder, and a phase switch. For example, the first phase finder is configured to generate a first fractional phase signal based on a multi-phase variable clock (CKV) signal. For example, the phase predictor is configured to generate a phase select (QSEL) signal or a multi-phase CKV select (CKVSEL) signal based on a frequency command word (FCW) signal or the multi-phase CKV signal. For example, the second phase finder is configured to generate a second fractional phase signal based on the CKVSEL signal or the QSEL signal. For example, the phase switch is configured to select the first or second fractional phase signal based on a phase error (PHE) signal.

Abstract: The invention generally relates to phase locked loops (PLL), and more specifically to ultra-low bandwidth phase locked loops. The invention may be for example embodied in an integrated circuit implementing a phase locked loop or a method for operating a phase locked loop. The invention provides a PLL with a control stage that uses only two storage cells, a counter and a digital-to-analog (DAC) converter. In comparison to prior-art PLLs using storage cells the configuration of the invention's control stage reduces the chip area required for the PLL reduced. The invention further suggests PVT compensation mechanisms for a PLL and implementing a PLL that has lower peaking in its frequency response, which results in better settling response.

Abstract: A clock recovery circuit includes: a phase comparison circuit to compare a data signal and a recovered clock; a charge pump circuit to output a current based on a phase difference signal; a loop filter to convert the current into a control voltage; an oscillation circuit to generate a first sine-wave clock having a frequency corresponding to the control voltage and a second sine-wave clock having a phase obtained by shifting a phase of the first sine-wave clock by 90 degrees; and a clock selector to select, as the recovered clock, the first sine-wave clock or the second sine-wave clock, a selected clock having a voltage difference between a voltage at a transition of the data signal and a center of an amplitude is larger than a voltage difference between a voltage of a non-selected clock at the time and a center of an amplitude of the non-selected clock.

Abstract: A delay-lock loop includes two feedback loops for controlling delay elements in the delay-lock loop. The first feedback loop includes a feedback circuit for generating a feedback signal indicating a delay adjustment based on a phase difference between an input clock signal to the delay-locked loop and an output clock signal generated by the delay-locked loop. The second feedback loop includes a power regulator that generates a regulated signal by regulating a power supply using the feedback signal as a reference. The delay-lock loop further includes a variable delay circuit including a resistor-capacitor network. The variable delay circuit controls a capacitance in the resistor-capacitor network based on the feedback signal and controls a resistance of the resistor-capacitor network based on the regulated signal. In this way, variable delay circuit generates the output clock signal by delaying the input clock signal based on both the feedback signal and the regulated signal.

Abstract: A PLL includes an oscillator, a time-to-digital converter (TDC) and a system for the remaining functionality. The TDC measures the oscillator's phase against a reference clock. The measured phase has an integer part obtained from a modulus-K counter, and a fractional part measured by a fine TDC. The system compares the measured phase with a desired phase, and filters it to obtain a parameter that controls the oscillator frequency. The TDC may also include a synchronization block to align the fine TDC and a pulse hider to reduce the power used by the fine TDC. The system may include an integrator to calculate the integer part of the desired phase, a second integrator to calculate the fractional part, and an interpolator for an even finer fraction. A method to obtain fast lock includes using the phase error rate of change to control the oscillator frequency.

Abstract: An apparatus, comprising: a NFET current mirror having a first NFET and a second NFET; a PFET gate-coupled to the drain of the second NFET, wherein the PFET has a larger gain than the second NFET; a driver NFET having a gate that is coupled to the drain the PFET; wherein the second NFET is coupled through its source to the drain of the driver NFET.

Abstract: The present invention discloses a PWM signal generation circuit and a PWM signal generation method. The PWM signal generation circuit includes: a reference signal generation circuit for generating a reference signal according to an input voltage; a variable ramp signal generation circuit for generating a variable ramp signal; and a comparator circuit for comparing the reference signal with the variable ramp signal to generate a PWM signal. A rising slope and/or a falling slope of the variable ramp signal is variable.

Abstract: A system on chip (SoC) includes one or more core logic blocks that are configured to operate on a lower supply voltage and a memory array configured to operate on a higher supply voltage. Each bitcell in the memory has two ferroelectric capacitors connected in series between a first plate line and a second plate line to form a node Q. A data bit voltage is transferred to the node Q by activating a write driver to provide the data bit voltage responsive to the lower supply voltage. The data bit voltage is boosted on the node Q by activating a sense amp coupled to node Q of the selected bit cell, such that the sense amp senses the data bit voltage on the node Q and in response increases the data bit voltage on the node Q to the higher supply voltage.

Abstract: In one embodiment, a clock generator generates a clock signal, and a clock channel generates a filtered clock signal from the clock signal. The clock channel comprises at least one filter that (i) attenuates noise in at least one Nyquist zone of the clock signal adjacent to the fundamental frequency and (ii) passes at least one harmonic frequency of the clock signal other than the fundamental frequency. A digital-to-analog converter (DAC) digitizes an analog input signal based on the filtered clock signal. Attenuating noise in the Nyquist zones reduces jitter of the filtered clock signal, and passing at least one harmonic frequency of the clock signal other than the fundamental frequency limits the degradation of the slew rate of the clock signal. As a result, the filtered clock signal increases the signal-to-noise ratio of the output of the DAC.

Abstract: An electronic device is powered by a first power supply and connected to an external device powered by a second power supply. The electronic device comprises a master controller, a conversion module, and a detection module. The master controller outputs first information. The conversion module converts the first information into second information based on a first voltage from the first power supply and a second voltage from the second power supply to control the external device to execute corresponding functions. The detection module is connected with the first power supply and the conversion module, and generates a pull-up voltage when the voltage of the second power supply is in an abnormal state. The conversion module further converts the first information into a second information based on the voltage of the first power supply and the pull-up voltage. The pull-up voltage is larger than the first voltage.

Abstract: The present disclosure provides an attenuator and associated methods of operations. An exemplary attenuator includes an input terminal, an output terminal, a voltage reference terminal, a first attenuation segment coupled with the input terminal and the output terminal, and a second attenuation segment coupled with the first attenuation segment and the voltage reference terminal. The attenuator further includes at least two switches coupled with the input terminal and the output terminal in parallel with the first attenuation segment, where at least some of the at least two switches have an associated voltage control terminal. For example, the attenuator includes a first switch and a second switch coupled with the input terminal and the output terminal in parallel with the first attenuation segment, wherein a first voltage control terminal is coupled with the first switch and a second voltage control terminal is coupled with the second switch.

Abstract: An attenuation circuit uses a voltage controlled variable resistance transistor as a signal attenuator for receivers operating in the zero Hz to about 30 MHz range. The transistor functions in the linear region to linearize the transistor resistance characteristics used for signal attenuation. In an exemplary application, the attenuation circuit is used as an RF attenuator for AM radio broadcast receivers and amplifiers with automatic gain control. Multiple attenuation circuits can be coupled in parallel, each attenuation circuit having a different sized variable resistance transistor, to form sequentially activated stages that increase the range of attenuation while minimizing distortion.

Abstract: A power line carrier communication reception circuit which can precisely receive a signal to be superimposed at such a signal level that leakage of an electromagnetic wave does not cause a problem while employing a simplified configuration is provided. The power line carrier communication reception circuit may include an amplifier which is connected to a power line and amplifies a received signal to be superimposed on the power line; two capacitors which are connected in series between both power sources of the amplifier; and a clipper circuit which connects connection points of these capacitors to the power line and limits the received signal in a predetermined range of a reference voltage between the capacitors, and in which the amplifier compares the signal limited by the clipper circuit and the reference voltage and amplifies the signal.

Abstract: System and method for controlling one or more switches. The system includes a first converting circuit, a second converting circuit, and a signal processing component. The first converting circuit is configured to convert a first current and generate a first converted voltage signal based on at least information associated with the first current. The second converting circuit is configured to convert a second current and generate a second converted voltage signal based on at least information associated with the second current. The signal processing component is configured to receive the first converted voltage signal and the second converted voltage signal and generate an output signal based on at least information associated with the first converted voltage signal and the second converted voltage signal.

Abstract: An electronic device is described, the device including a first circuit arranged to transfer a signal with a first predetermined phase shift, a second circuit, connected in series with the first circuit, arranged to transfer a signal with a second predetermined phase shift, and a resistance connected in parallel with the first and second circuits, wherein the first circuit includes a first capacitance connected between a first pair of nodes, a second capacitance connected between a second pair of nodes, and a first transformer having a first winding connected between the first pair of nodes and a second winding connected between the second pair of nodes.

Abstract: A switch circuit, a control circuit, a grounding wire and a control wire are formed on a substrate. The switch circuit connects an antenna terminal with one of multiple high frequency terminals. The control circuit outputs a control signal to the switch circuit. The grounding wire is disposed between the switch circuit and the control circuit and extends from a location proximate to an edge of the substrate to a location proximate to an opposite edge of the substrate. The control wire that carries the control signal is disposed between one end of the grounding wire and an edge of the semiconductor substrate.

Abstract: A monitor circuit includes a reference voltage generating unit that generates first and second reference voltages, a first amplifier unit that amplifies a differential voltage between the first reference voltage and the second reference voltage, a second amplifier unit that amplifies a differential voltage between an internal power supply voltage being supplied to a functional block provided in the semiconductor integrated circuit and the first reference voltage, and a comparator unit that compares an amplification result of the first amplifier unit with an amplification result of the second amplifier unit and outputs a comparison result as a measurement result.

Abstract: An integrated circuit includes a voltage regulator to supply a regulated voltage and a data output that couples to an unterminated transmission line. The circuit draws a variable amount of power from the voltage regulator according to the data. The voltage regulator includes a first current generation circuit to provide a data transition-dependent current.

Abstract: Embodiments of the present invention may include a filter with programmable components, a tuning signal generator, a comparator, and a feedback system. The tuning signal generator may input first and second test signals into the filter and the comparator may sample the output of the filter in response to each respective signal. The comparator may then compare the sampled outputs to predetermined values. In response to the comparator's output, the feedback system may vary the programmable components of the filter until the search of the programmable components is exhausted, yielding first and second tuning results. Finally, the feedback system may determine a final tuning result based on the first and second tuning results. Consequently, the filter's actual corner frequency may be within an acceptable range of a desired corner frequency.

Abstract: Provided is an operational amplifier circuit having a high tolerance for clock phase difference fluctuations. An FIR filter is used to add an input signal of the FIR filter to a signal obtained by delaying the input signal of the FIR filter. In this manner, chopper noise can be removed. Thus, the operational amplifier circuit may have a high tolerance for clock phase difference fluctuations regardless of the phase difference between clocks for controlling a chopper circuit and the FIR filter.

Abstract: Techniques for reducing ringing arising from L-C coupling in a boost converter circuit during a transition from a boost ON state to a boost OFF state. In an aspect, during an OFF state of the boost converter circuit, the size of the high-side switch coupling a boost inductor to the load is gradually increased over time. In this manner, the on-resistance of the high-side switch is decreased from a first value to a second (lower) value over time, which advantageously reduces ringing (due to high quality factor or Q) when initially entering the OFF state, while maintaining low conduction losses during the remainder of the OFF state. Further techniques are provided for implementing the high-side switch as a plurality of parallel-coupled transistors.

Abstract: Aspects disclosed herein relate to using a processor controlled switcher architecture with a high-efficiency PA control. A wireless communications device may be include a processor, a power amplifier and a processor controller PA switcher. In an aspect, the processor may be a modem, a RF chip, etc. In one example, the PA switcher may be configured to receive a switcher control signal on the control line. In an aspect, the switcher control signal may be based on future characteristics of an input signal. The PA switcher may be further configured to select a voltage path from among a plurality of voltage paths based on the switcher control signal to provide a supply voltage to the lower pass filter associated with the PA.

Abstract: Techniques for preventing reverse current in applications wherein a tracking supply voltage is placed in parallel with a switching power stage. The tracking supply voltage may be boosted to a level higher than a battery supply voltage using, e.g., a boost converter. In an aspect, a negative current detection block is provided to detect negative current flow from the boosted tracking supply voltage to the battery supply voltage. A high-side switch of the switching power stage may be disabled in response to detecting the negative current. To prevent false tripping, the tracking supply voltage may be further compared with the battery supply voltage, and a latch may be provided to further control the high-side switch.

Abstract: A method and generator for modifying interactions between a load and the generator are described. The method includes applying output power to the load using a power amplifier, controlling a level of the output power responsive to a power control setting, and adjusting a conduction angle of the power amplifier to reduce a level of sensitivity of the power amplifier to variations of an impedance of the load. The generator includes a compensation subsystem coupled to the power amplifier that controls a conduction angle of the power amplifier to enable a sensitivity of the power amplifier to be adjusted.

Abstract: Apparatus and methods for biasing a power amplifier are disclosed. In one embodiment, a method of biasing a power amplifier includes shaping an enable signal using a time-dependent signal generator to generate a control current, amplifying the control current using a current amplifier to generate a correction current, and generating a bias current for a power amplifier using a primary biasing circuit. The primary biasing circuit is configured to use the correction current to correct for a variation in gain of the power amplifier when the power amplifier is enabled.

Abstract: A zero-crossing amplifier unit for use in high speed analog-digital-converters. A gain stage compares a sampling voltage at an input node with a provided threshold voltage to obtain a gain stage output signal. A voltage controlled current source provides a load current depending on a time window between an initial slope and an end slope of the gain stage output signal. A slope control means increases a duration of a rise and/or fall time of at least one of the initial and end slopes of the gain stage output signal.

Abstract: Amplifiers with improved isolation are disclosed. In an exemplary design, an apparatus (e.g., a wireless device, an integrated circuit, etc.) includes an amplifier having a gain transistor, first and second cascode transistors, and a shunt transistor. The gain transistor receives an input signal and provides an amplified signal. The first cascode transistor is coupled between the gain transistor and an intermediate node and receives the amplified signal. The second cascode transistor is coupled between the intermediate node and an output node and provides an output signal. The shunt transistor is coupled between the intermediate node and circuit ground. The first and second cascode transistors are enabled to provide the output signal. The shunt transistor is (i) disabled when the cascode transistors are enabled and (ii) enabled to short the intermediate node to circuit ground when the cascode transistors are disabled.

Abstract: The present disclosure provides a radio frequency signal amplifier and amplifying system using coaxial cables to apply bias voltages to the control terminals of the transistors. The radio frequency signal amplifier includes a transistor connected between an input terminal and an output terminal, a first coaxial cable configured to couple a bias voltage to a control terminal of the transistor, a feed line connected between the bias voltage and the first coaxial cable, and a second coaxial cable connected between an open stub and the control terminal of the transistor.

Abstract: Since a high-frequency signal that is output from a high-frequency oscillator circuit section is detected in a detector circuit and a bias of a negative voltage is supplied from a bias circuit section to the high-frequency amplifier circuit section with a detection voltage that is detected, a negative power supply circuit such as a DC/DC converter or a peripheral circuit is not required, and since a negative bias voltage can be supplied to a high-frequency amplifier circuit, downsizing can be achieved with a low cost.

Abstract: Proposed is a bias circuit for a transistor in a C class amplifier. The bias circuit comprises: a class AB amplifier bias voltage generating means adapted to generate a bias voltage at an output terminal; and a transistor connected between the output terminal and a first reference voltage, the control terminal of the transistor being connected to a second reference voltage via a switch. Closure of the switch connects the second reference voltage to the control terminal of the transistor to cause a shift in the bias voltage generated by the class AB amplifier bias voltage generating means to achieve a predetermined class C bias voltage at the output terminal.

Abstract: Various embodiments described herein provide systems and methods for improved performance for power amplifiers, particularly GaN power amplifiers. According to some embodiments, a power amplifier (e.g., GaN power amplifier) utilizes adaptive predistortion and adaptive closed-loop control of the drain current of the power amplifier to achieve improved power amplifier performance.

Abstract: Techniques for dynamically generating a headroom voltage for an envelope tracking system. In an aspect, an initial headroom voltage is updated when a signal from a power amplifier (PA) indicates that the PA headroom is insufficient. The initial headroom voltage may be updated to an operating headroom voltage that includes the initial voltage plus a deficiency voltage plus a margin. In this manner, the operating headroom voltage may be dynamically selected to minimize power consumption while still ensuring that the PA is linear. In a further aspect, a specific exemplary embodiment of a headroom voltage generator using a counter is described.

Abstract: A triple cascode power amplifier is provided. The triple cascode power amplifier includes a first-stage transistor pair, a second-stage transistor pair and a third-stage transistor pair. The first-stage transistor pair comprises two first-stage transistors that respectively receive two dynamic bias voltages with opposite polarities. The second-stage transistor pair is coupled with the first-stage transistor pair to form a first node and comprise two second-stage transistors coupled with each other to form a second node. The third-stage transistor pair is coupled with the second-stage transistor pair and comprises two third-stage transistors for outputting a differential signal. The first-stage transistor pair and the second-stage transistor pair are low voltage components while the third-stage transistor pair is a high voltage component. The power amplifier transforms the differential signal into a single-ended signal for output.

Abstract: There are provided a ring oscillator having a plurality of delay circuits to be ring-connected. At least one of the plurality of delay circuits has a delay element formed in a layout region including the same layout shape as the layout shape of an SRAM cell, and a path circuit connected in parallel to the delay element. The delay element outputs an output signal to a delay circuit in the next stage within the plurality of delay circuits in response to one of rise transition and fall transition of a signal input to the input terminal of the delay element from a delay circuit in the previous stage within the plurality of delay circuits. The path circuit outputs an output signal to the delay circuit in the next stage in response to the transition other than the one transition.

Abstract: A single-ended ring oscillation device for generating a fully differential signal is provided. The single-ended oscillation device includes a single-ended ring oscillator and a phase processing unit. The single-ended ring oscillator includes an odd number of inverting delay units. The inverting delay units sequentially generate a first signal, a second signal and a third signal. The phase processing unit generates an intermediate signal according to the first signal and the third signal, and outputs the intermediate signal and a delayed version of the second signal as a fully differential signal. The intermediate signal and the second signal are opposite to each other in phase.

Abstract: A crystal controlled oscillator of the present disclosure includes: an oscillator circuit for oscillator output, a first oscillator circuit, a second oscillator circuit, a heating unit, a pulse generator, a frequency difference detector, an addition unit, a circuit unit, a frequency measuring unit, a determination unit, and a signal selector. The signal selector is configured to: select a control signal where electric power supplied to the heating unit is smaller than supplied electric power in the detection range in a case where a frequency in a set period at the train of pulses is out of the detection range at the high temperature side; select a control signal where electric power supplied to the heating unit becomes a preset value in a case where a frequency in the set period at the train of pulses is out of the detection range at the low temperature side.

Abstract: A relaxation oscillator for generating an output clock signal includes an RC circuit, a self-biased comparator stage, and a logic circuit. The RC circuit generates first and second comparator input signals that are provided to the self-biased comparator stage. The self-biased comparator stage includes first and second input stages and a voltage reference circuit. Each of the first and second input stages in conjunction with the voltage reference circuit forms a comparator, i.e., first and second comparators corresponding to the first and second input stages, respectively. The self-biased comparator stage generates first and second comparator output signals, based on the first and second comparator input signals. The first and second comparator output signals are provided to the logic circuit that generates the output clock signal.

Abstract: Systems and methods for amplitude loop control for oscillators. In some embodiments, an electronic circuit may include oscillator circuitry configured to produce a periodic signal, and control circuitry operably coupled to the oscillator circuitry, the control circuitry including switched capacitor circuitry configured to determine a difference between maximum and minimum peak voltage values of the periodic signal, the control circuit configured to control a voltage amplitude of the periodic signal based upon the difference. In other embodiments, a method may include receiving a clock signal from a clock generator, determining, using a switched capacitor circuit, a first peak voltage value of the clock signal, determining, using the switched capacitor circuit, a second peak voltage value of the clock signal, and controlling a bias current applied to the clock generator based upon a difference between the first and second peak voltage values.

Abstract: A crystal resonator includes a crystal element and excitation electrodes. The crystal element includes an ? crystal region and a ? crystal region that have mutually different positive/negative directions along an X-axis. Each two or more of the ? crystal regions and the ? crystal regions are alternately formed along a direction perpendicular to the X-axis. The excitation electrodes are formed on both surfaces of the respective ? crystal region and ? crystal region other than crystal regions positioned at both end portions of a row of the ? crystal regions and the ? crystal regions.

Abstract: A crystal resonator includes a plate-shaped crystal element, excitation electrodes, and a second crystal region. The plate-shaped crystal element is supported to a supporting portion. The crystal element is configured to vibrate at a thickness shear vibration. The excitation electrodes are disposed at both surfaces of a first crystal region of the crystal element. The second crystal region is positioned outside with respect to the excitation electrodes. The second crystal region is formed at a peripheral edge portion of the crystal element so as to occupy a region of equal to or more than 75% of a whole circumference of the crystal element. The second crystal region has a positive/negative direction of an X-axis of a crystal different from a positive/negative direction of an X-axis of a crystal of the first crystal region.

Abstract: A matching network for matching the impedance of a load to an impedance of an electrical energy source has an output, an input, an inductance, a capacitance, and a series connection of a nonlinear impedance and the inductance or the capacitance. The series connection is connected in parallel to the output or parallel to the input.

Abstract: A module substrate includes: a multilayered wiring substrate that includes wiring layers; and embedded duplexers that are embedded in the multilayered wiring substrate and electrically connected to the wiring layers, wherein the embedded duplexers include duplexers supporting at least two bands of Band1, Band2, Band5, and Band8.

Abstract: A piezoelectric thin film resonator includes: a substrate; a piezoelectric film located on the substrate; a lower electrode and an upper electrode facing each other across at least a part of the piezoelectric film; and an insertion film that is inserted into the piezoelectric film, is located in at least a part of an outer periphery region in a resonance region in which the lower electrode and the upper electrode face each other across the piezoelectric film, and is not located in a center region of the resonance region.

Abstract: A transformer filter arrangement including a transformer having a first winding and a second winding is provided. Both of the first and the second windings are located between an outer border and an inner border, which is inside the outer border. The transformer filter arrangement further includes at least one reactive sub circuit, each including at least one inductor. The first winding of the transformer is divided into a plurality of winding segments. At least a first one of the at least one reactive sub circuit being connected in series with the winding segments of the first winding between two such winding segments, and having at least one of the at least one inductor located inside said inner border.

Abstract: The present invention relates generally to digital elliptic filters, and more particularly, but not exclusively to multi-layer digital elliptic filters and methods for their fabrication.

Abstract: A filter includes a case, a number of resonant columns received in the case, a partition walls received in the case and located between the adjacent resonant columns, a number of blend strips fastened on the partition walls, and a cover covering on the case. The cover defines a number of regulating through hole corresponding to the resonant columns and the blend strips and includes a number of regulating bolts passing through the regulating through hole to couple with the resonant columns and the blend strips. The regulating bolts move upwards and downwards in the regulating through holes to regulate a transmission zero of the filter.

Abstract: A structure of a battery relay is provided comprising a plunger movable upward and downward. The plunger comprises a lower portion, an upper portion, and an intermediate portion. A guide is fixed to a housing and supports the intermediate portion. A return spring is disposed on the lower portion and supports the plunger. A traveling contact is integrally formed with the plunger and movable upward and downward. A stationary contact is fixedly disposed at a lower side of the traveling contact. An exciting coil is connected to a battery switch and moves the plunger downward by being excited when the battery switch is turned on. A movable spring formed as a compression spring, is disposed on an upper portion of the traveling contact, and has one end fixed to an upper end of the plunger and another end fixed to an upper end of the guide.