Abstract: The invention provides a recombinant carboxydotrophic Clostridia microorganism with increased overall utilization of NADPH relative to a parent microorganism. Further, the invention provides a method of producing a recombinant carboxydotrophic Clostridia microorganism which exhibits increased NADPH utilization relative to a parental microorganism. In particular, the invention relates to increasing the overall utilization of NADPH in a recombinant carboxydotrophic Clostridia microorganism in order to increase the production of at least one fermentation product by the microorganism.

Abstract: The present invention relates to methods for constructing a filamentous fungal strain for production of multiple recombinant polypeptides having biological activity. The present invention also relates to methods for producing multiple recombinant polypeptides having biological activity in a filamentous fungal strain. The present invention also relates to filamentous fungal strains expressing multiple recombinant polypeptides having biological activity.

Abstract: Example methods, systems, and computer readable media are provided for monitoring operating processes. An example method includes monitoring an equipment parameter associated with an asset in an operating process unit and monitoring a process parameter associated with the asset. The example method includes determining an asset health corresponding to the asset. The asset health is determined based on a potential state of corrosion associated with the asset by comparing a corrosivity index to a corrosion threshold. The corrosivity index is a function of at least one of current values or changes in the monitored equipment parameter or the monitored process parameter over time.

Abstract: A measuring device is provided for determining the type and/or concentration a gaseous analyte from a set of analytes in a gaseous carrier. It comprises a housing having a passage to a cavity. A gas sensor with a heated metal-oxide sensing layer is arranged in the cavity. In order to gain a better understanding of the type of the analyte, diffusion effects are exploited by taking into account that the diffusion process through the passage as well as the catalytic reaction rate at the metal-oxide sensing layer depend on the type of the analyte. These material parameters can be determined by taking several measurements in a non-steady state of the concentration of the analyte within the cavity or while varying the reaction rate.

Abstract: The present invention provides a probe that further promotes ionization in proteomic analysis using mass spectrometry, and a high-sensitive mass spectrometry method for a protein using such a probe. Further, the present invention provides an ionization-enhancing probe that can be used even for a protein that has a high degree of hydrophobicity and quickly turns over, and a high-sensitive mass spectrometry method for a protein using such a probe. A thiol probe for a protein, which is represented by the following formula (I): [Chemical Formula 1] wherein R1 represents a linker group, and R2 represents a substituted ammonium group or a substituted amino group. A mass spectrometry method for a protein, comprising the steps of: obtaining a modified protein by reacting the thiol probe with a protein to be subjected to mass spectrometry; and subjecting the modified protein to mass spectrometry.

Abstract: Disclosed are methods and systems for the analysis of thiopurine drug metabolites in a sample using liquid chromatography/mass spectrometry.

Abstract: Methods of selectively detecting the presence of at least one compound in a gaseous medium. A silicon substrate can be exposed to the gaseous medium under conditions to adsorb the at least one compound to the silicon substrate to form a modified silicon substrate. The modified silicon substrate can be analyzed to determine if the at least one compound was present in the gaseous medium. The step of analyzing can include using X-ray spectroscopy.

Abstract: An apparatus for detecting a chemical of interest in a fluid or estimating a concentration of the chemical in the fluid includes: a carrier configured to be conveyed through a borehole penetrating an earth formation; a first temperature sensor disposed at the carrier and configured to sense a temperature of the fluid and provide a first temperature output; and a second temperature sensor disposed at the carrier and covered with an exothermic reaction material that experiences an exothermic reaction when exposed to the chemical of interest and configured to sense a temperature and provide a second temperature output. The apparatus further includes a processor coupled to the first temperature sensor and the second temperature sensor and configured to detect the chemical or estimate the concentration using the first temperature output and the second temperature output.

Abstract: A fluorescence reader for an optical assay arrangement that includes a polymeric sample substrate having a reaction site-surface and a substrate surface. The fluorescence reader includes a light source arranged to illuminate the reaction site-surface through the substrate surface, and a detector device arranged to detect fluorescent light emitted from the reaction site-surface and transmitted through the substrate surface, the substrate surface being configured to increase transmission of emitted fluorescent light by suppression of total internal reflection.

Abstract: The present invention relates to a method of applying a spot of an unlabelled biomolecule, e.g. antibody or protein antigen, to a surface of a reaction chamber of a diagnostic assay. This method comprising the steps of applying to the surface of the reaction chamber a solution comprising a sugar and comprising a non-labelled biomolecule, e.g. antibody or protein antigen, and allowing the solution to dry. In this method the biomolecule is in a concentration sufficient to saturate the binding places for a protein on the surface where the solution has been applied to. The present invention relates to a reaction chamber of a diagnostic device for performing a biomolecule, e.g. antibody or protein antigen, based detection assay. Herein,the reaction chamber comprises a detection region with one or more spots of an unlabelled biomoleculespots bound to the detection region. The one or more spots have a diameter of between 0.1 to 0.5 mm. The spot comprises a sugar and a protein and comprises between 0.01 and 0.

Abstract: An electrically passive device and method for in-situ acoustic emission, and/or releasing, sampling and/or measuring of a fluid or various material(s) is provided. The device may provide a robust timing mechanism to release, sample and/or perform measurements on a predefined schedule, and, in various embodiments, emits an acoustic signal sequence(s) that may be used for triangulation of the device position within, for example, a hydrocarbon reservoir or a living body.

Abstract: Methods of enhancing signal ratio between calibrators in an assay for an analyte include conducting an assay for the analyte with zero concentration of analyte in a first calibrator to determine a first signal level. The reagents employed in the assay comprise an antibody reagent comprising an antibody for the analyte wherein a hinge region of the antibody is conjugated to a moiety. The assay for the analyte is also conducted with a second concentration of analyte in a second calibrator to determine a second signal level wherein the second analyte concentration is greater than zero and wherein the reagents employed in the assay comprise the antibody reagent. A ratio of the first signal level to the second signal level is determined and evaluated.

Abstract: Disclosed in this specification is a method for detecting an analyte using buoyant particles and chemical moieties to give buoyant particle composites that exhibit SERS and can be used for detecting the analytes in a liquid sample. A method is provided for detecting analytes of interest by contacting the analyte with a buoyant particle that comprises a first chemical moiety, such as a SERS-active component, allowing the analyte of interest to bind to the first chemical moiety. The resulting composite localizes in a discrete location of the liquid sample through a buoyant force. The composite is then detected by measuring the Raman scattered light in the discrete location of the liquid sample.

Abstract: The present disclosure relates to a phenytoin biosensor. In some embodiments, the phenytoin biosensor may comprise a microcantilever, a self-assembly monolayer, and a phenytoin antibody layer. The self-assembly monolayer may immobilize on the microcantilever surface. The phenytoin antibody layer may immobilize on the self-assembly monolayer. The phenytoin antibody layer may be used to bind with phenytoin drug samples. The present disclosure further relates to methods for measuring the concentration of phenytoin drug samples.

Abstract: The present invention is directed to novel assays for detecting target molecules. The assays employ small size, detectably labeled, magnetic nanoparticles associated with a capture molecule. The detection assay is accelerated by applying magnetic field during the assay. The assays of the invention can be used to enhance the efficiency of the detection step in dot blot, Western blot and ELISA.

Abstract: In order to provide an immunoassay method and an immunoassay apparatus capable of further reducing errors due to non-target substances, a detector measures a measurement specimen and detects information regarding the binding number of carrier particles included in the measurement specimen. A controller classifies, based on the information regarding the binding number, particles included in the measurement specimen into groups, the groups being classified in accordance with the binding numbers.

Abstract: In a centrifugal microfluidic device for conducting capture assays, a microfluidic platform rotates in a plane of rotation and has at least one capture surface for immobilizing a target particle of interest in the device. The capture surface oriented so that it is not parallel to the plane of rotation of the device and is positionally fixed in the device during operation of the device. The centrifugal force arising from rotation of the device forces the target particles against the capture surface. Capture efficiency is independent of the rate of flow of the fluid and independent of the rate of rotation of the microfluidic platform.

Abstract: A method of manufacturing a magnetoresistive-based device includes etching a hard mask layer, the etching having a selectivity greater than 2:1 and preferably less than 5:1 of the hard mask layer to a photo resist thereover. Optionally, the photo resist is trimmed prior to the etch, and oxygen may be applied during or just subsequent to the trim of the photo resist to increase side shrinkage. An additional step includes an oxygen treatment during the etch to remove polymer from the structure and etch chamber.

Abstract: Embodiments of the present disclosure generally provide apparatus and method for improving processing uniformity by reducing external magnetic noises. One embodiment of the present disclosure provides an apparatus for processing semiconductor substrates. The apparatus includes a chamber body defining a vacuum volume for processing one or more substrate therein, and a shield assembly for shielding magnetic flux from the chamber body disposed outside the chamber body, wherein the shield assembly comprises a bottom plate disposed between the chamber body and the ground to shield magnetic flux from the earth.

Abstract: A resin application apparatus includes: an optical property measurement unit measuring an optical property of light emitted from a light emitting diode (LED) chip which is mounted on a package body and to which transparent resin is not applied; and a resin application unit applying light conversion material-containing transparent resin to the LED chip in accordance with a resin application amount which is decided depending on the optical property measured by the optical measurement unit.

Abstract: A microelectronic package may include a first microelectronic unit including a semiconductor chip having first chip contacts, an encapsulant contacting an edge of the semiconductor chip, and first unit contacts exposed at a surface of the encapsulant and electrically connected with the first chip contacts. The package may include a second microelectronic unit including a semiconductor chip having second chip contacts at a surface thereof, and an encapsulant contacting an edge of the chip of the second unit and having a surface extending away from the edge. The surfaces of the chip and the encapsulant of the second unit define a face of the second unit. Package terminals at the face may be electrically connected with the first unit contacts through bond wires electrically connected with the first unit contacts, and the second chip contacts through metalized vias and traces formed in contact with the second chip contacts.

Abstract: A process for producing a substrate for a liquid ejection head in which a depressed portion is formed on a second surface that is a surface opposite to a first surface of a silicon substrate having an element formation region on the first surface with a peripheral side region left, the process including the steps of (1) forming an etching mask layer covering the second surface of the silicon substrate; (2) subjecting the etching mask layer and the silicon substrate to laser abrasion processing to form a pattern opening that does not pass through the silicon substrate; and (3) performing a wet etching process to the silicon substrate where the pattern opening is formed from a side of the second surface to form the depressed portion. The depressed portion is formed over a center side region including a position corresponding to the element formation region.

Abstract: A process for producing a semiconductor chip having a substrate and a bump formed on the substrate including (1) forming, on a substrate, a conductor gold for plating to be a base of plating growth; (2) forming a mask for plating on the conductor gold for plating; (3) performing plating using the mask for plating to form the bump and a dummy pattern; (4) removing the mask for plating; (5) etching the conductor gold for plating; and (6) applying a shock to at least the dummy pattern. The amount of side etching of the conductor gold for plating is grasped from a state of separation of the dummy pattern due to the shock in the step (6).

Abstract: A photoelectric conversion device includes a plurality of photoelectric conversion regions disposed over a substrate, and a colored region disposed among the photoelectric conversion regions over the substrate, the colored region forming an image over the substrate.

Abstract: A device having a carrier, a light-emitting structure, and first and second electrodes is disclosed. The light-emitting structure includes an active layer sandwiched between a p-type GaN layer and an n-type GaN layer, the active layer emitting light of a predetermined wavelength in the active layer when electrons and holes from the n-type GaN layer and the p-type GaN layer, respectively, combine therein. The first and second electrodes are bonded to the surfaces of the p-type and n-type GaN layers that are not adjacent to the active layer. The n-type GaN layer has a thickness less than 1.25 ?m. The carrier is bonded to the light emitting structure during the thinning of the n-type GaN layer. The thinned light-emitting structure can be transferred to a second carrier to provide a device that is analogous to conventional LEDs having contacts on the top surface of the LED.

Abstract: A packaged optical device includes a substrate having a surface region with light emitting diode devices fabricated on a semipolar or nonpolar GaN substrate. The light emitting diodes emit polarized light and are characterized by an overlapped electron wave function and a hole wave function. Phosphors within the package are excited by the polarized light and, in response, emit electromagnetic radiation of a second wavelength.

Abstract: A method for manufacturing a light emitting device package is provided. In the method, a growth substrate including a plurality of light emitting devices disposed on a top surface of the growth substrate is prepared. A first package substrate having a bonding pattern corresponding to a portion of the plurality of light emitting devices is prepared, and the bonding pattern is disposed on a top surface of the first package substrate. The portion of the plurality of light emitting devices and the bonding pattern are bonded by disposing the top surface of the growth substrate to face the top surface of the first package substrate. The portion of the plurality of light emitting devices is separated from the growth substrate. The portion of the plurality of light emitting devices joined to the bonding pattern is packaged.

Abstract: The present invention relates to a GaN type LED device and a method of manufacturing the same. More particularly, there are provided a GaN type LED device including an LED chip; and a submount eutectic-bonded with the LED chip through an adhesive layer, wherein the adhesive layer is configured by soldering a plurality of metallic layers in which a first metallic layer and a second metallic layer are sequentially stacked, and the second metallic layer is formed in a paste form. Further, the present invention provides a method of manufacturing the GaN type LED device.

Abstract: It is known that a light-emitting element utilizing organic EL deteriorates due to moisture. Therefore, a sealing technique to prevent moisture permeation is important. A light-emitting device including a light-emitting element utilizing organic EL is manufactured over a support substrate having flexibility and a high heat dissipation property (e.g., stainless steel or duralumin), and the light-emitting device is sealed with a stack body having moisture impermeability and a high light-transmitting property or with glass having moisture impermeability and a high light-transmitting property and having a thickness greater than or equal to 20 ?m and less than or equal to 100 ?m.

Abstract: A method for reducing dislocations or other defects in a light emitting device, such as light emitting diode (LED), by in-situ introducing nanoparticles into at least one of a defect-controlling layer, an n-type layer, a p-type layer, and a quantum well of the light emitting device. A light emitting device is provided, and nanoparticles are dispensed in-situ in at least one of a defect-controlling layer, an n-type layer, a p-type layer, and a quantum well of the light emitting device.

Abstract: The present invention provides a vertical type sensor, including a substrate; a first electrode formed on the substrate; a sensing layer formed on the first electrode layer and reactive to a target substance, wherein the first electrode layer is interposed between the substrate and the sensing layer; and a second electrode layer formed on the sensing layer and having a plurality of openings, wherein the sensing layer is interposed between the first electrode layer and the second electrode layer, and the target substance contacts the sensing layer via the plurality of openings. The vertical type sensor of the present invention provides instant, sensitive and rapid detection.

Abstract: A method of fabricating electrical connections in an integrated MEMS device is disclosed. The method comprises forming a MEMS wafer. Forming a MEMS wafer includes forming one cavity in a first semiconductor layer, bonding the first semiconductor layer to a second semiconductor layer with a dielectric layer disposed between the first semiconductor layer and the second semiconductor layer, and etching at least one via through the second semiconductor layer and the dielectric layer and depositing a conductive material on the second semiconductor layer and filling the at least one via. Forming a MEMS wafer also includes patterning and etching the conductive material to form one standoff and depositing a germanium layer on the conductive material, patterning and etching the germanium layer, and patterning and etching the second semiconductor layer to define one MEMS structure. The method also includes bonding the MEMS wafer to a base substrate.

Abstract: A device includes a semiconductor substrate, and a capacitive sensor having a back-plate, wherein the back-plate forms a first capacitor plate of the capacitive sensor. The back-plate is a portion of the semiconductor substrate. A conductive membrane is spaced apart from the semiconductor substrate by an air-gap. A capacitance of the capacitive sensor is configured to change in response to a movement of the polysilicon membrane.

Abstract: An optical component is fixed precisely on a sensor chip. After a sensor chip including a front surface having a sensor plane with a plurality of light receiving elements is mounted face-up over a wiring substrate, an adhesive is disposed on the front surface of the sensor chip at a plurality of positions, and a plurality of spacers having adherence is formed by curing this adhesive. Then, an adhesive paste is disposed on the front surface of the sensor chip. Then, an optical component held by a bonding tool is disposed on the front surface via the spacer and the adhesive. After that, the bonding tool is separated from the optical component and the optical component is fixed by curing the adhesive in a state in which a load is not applied to the optical component.

Abstract: A wafer packaging method includes the following steps. A light transmissive carrier is provided. A hydrolytic temporary bonding layer is formed on the light transmissive carrier. A first surface of a light transmissive protection sheet is bonded to the hydrolytic temporary bonding layer, such that the hydrolytic temporary bonding layer is located between the light transmissive protection sheet and the light transmissive carrier. A second surface of the light transmissive protection sheet facing away from the first surface is bonded to a third surface of a wafer. The light transmissive carrier, the hydrolytic temporary bonding layer, the light transmissive protection sheet, and the wafer are immersed in a high temperature liquid, such that adhesion force of the hydrolytic temporary bonding layer is eliminated. The light transmissive protection sheet and the wafer are obtained from the high temperature liquid.

Abstract: A CIS and a method of manufacturing the same, the CIS including a substrate having a first surface and second surface opposite thereto, the substrate including an APS array region including a photoelectric transformation element and a peripheral circuit region; an insulating interlayer on the first surface of the substrate and including metal wirings electrically connected to the photoelectric transformation element; a light blocking layer on the peripheral circuit region of the second surface of the substrate, exposing the APS array region, and including a plurality of metal wiring patterns spaced apart from one another to form at least one drainage path along a boundary region between the APS array region and the peripheral circuit region; a color filter layer on the second surface of the substrate covering the APS array region and the light blocking layer; and a microlens on the color filter layer on the APS array region.

Abstract: A method for forming image sensors includes providing a substrate and forming a plurality of photo diode regions, each of the photo diode regions being spatially disposed on the substrate. The method also includes forming an interlayer dielectric layer overlying the plurality of photo diode regions, forming a shielding layer formed overlying the interlayer dielectric layer, and applying a silicon dioxide bearing material overlying the shielding layer. The method further includes etching portions of the silicon dioxide bearing material to form a plurality of first lens structures, and continuing to form each of the plurality of first lens structures to provide a plurality of finished lens structures.

Abstract: Photovoltaic modules may include multiple flexible thin film photovoltaic cells electrically connected in series by a substantially transparent top sheet having an embedded conductive wire grid pattern. Methods of manufacturing photovoltaic modules including integrated multi-cell interconnections are provided.

Abstract: A method of tailoring the dopant profile of a workpiece by modulating one or more operating parameters is disclosed. In one embodiment, the workpiece may be a solar cell and the desired dopant profile may include a heavily doped surface region and a highly doped region. These two regions can be generated by varying one or more of the parameters of the ion implanter. For example, the extraction voltage may be changed to affect the energy of the implanted ions. The ionization energy can be changed to affect the species of ions being generated from the source gas. In another embodiment, the source gasses that are ionized may be changed to affect the species being generated. After the implant has been performed, thermal processing is performed which minimizes the diffusion of the ions in the workpiece.

Abstract: Embodiments of the invention contemplate formation of a high efficiency solar cell utilizing a laser patterning process to form openings in a passivation layer while maintaining good film properties of the passivation layer on a surface of a solar cell substrate. In one embodiment, a method of forming an opening in a passivation layer on a back surface of a solar cell substrate includes transferring a substrate having a passivation layer formed on a back surface of a substrate into a laser patterning apparatus, the substrate having a first type of doping atom on the back surface of the substrate and a second type of doping atom on a front surface of the substrate, providing laser radiation generated by the laser patterning apparatus from the front surface transmitting through the substrate to the passivation layer disposed on the back surface of the substrate, and forming openings in the passivation layer.

Abstract: Embodiments of the invention generally relate to methods for fabricating photovoltaic devices, and more particularly to methods for in-situ cleaning of a solar cell substrates. In one embodiment, a method of manufacturing a solar cell device is provided. The method comprises exposing a single or poly crystalline silicon substrate to a wet clean process to clean the surfaces of the crystalline substrate, loading the crystalline silicon substrate into a processing system having a vacuum environment, exposing at least one surface of the crystalline silicon substrate to an in-situ cleaning process in the vacuum environment of the processing system, and forming one or more passivation layers on at least one surface of the crystalline silicon substrate in the processing system.

Abstract: A method of fabricating a semiconductor device includes attaching a semiconductor substrate to a carrier using a carrier fixing layer, where the semiconductor substrate including a plurality of semiconductor chips. The method further includes forming gaps between adjacent ones of the chips. The gaps may be formed using one or more chemicals or light which act to remove portions of the semiconductor substrate to expose the carrier fixing layer. Additional portions of the carrier fixing layer are then removed to allow for removal of the chips from the carrier.

Abstract: A method includes providing an integrated circuit (IC) die assembly that includes a substrate and an IC die mounted on a portion of a major surface of the substrate, dispensing an interface material on the IC die, positioning a portion of a heat spreader in contact with the interface material, and dispensing an adhesive between one side of the heat spreader facing the IC die assembly and exposed portions of a major surface of an encapsulant on the substrate.

Abstract: A method for manufacturing a semiconductor device includes: forming, in element regions of a semiconductor wafer, electrodes and a insulator on peripheral part of the electrodes so that a height of the insulator is higher than that of the electrodes; forming, on the front face of the semiconductor wafer, a groove for surrounding a periphery of the electrodes with the insulator being sandwiched between the electrodes and the groove, the groove being formed so that a height of the groove is lower than that of the insulator and the groove extends to an outer circumferential edge of the semiconductor wafer; bonding adhesives onto the electrodes in the element regions so that a height of the adhesives is higher than that of the insulator, and bonding, onto the adhesives, a base material for covering the front face of the semiconductor wafer; and processing a rear face of the semiconductor wafer.

Abstract: A conformal coating on a semiconductor die provides adhesion between the die and a support. No additional adhesive is necessary to affix the die on the support. The conformal coating protects the die during assembly, and serves to electrically insulate the die from electrically conductive parts that the die may contact. The conformal coating may be an organic polymer, such as a parylene, for example. Also, a method for adhering a die onto a support, which may optionally be another die, includes providing a coating of a conformal between the die and the support, and heating the coating between the die and the support. The conformal coating may be provided on a die attach area of a surface of the die, or on a die mount region of a surface of the support, or on both a die attach area of a surface of the die and on a die mount region of a surface of the support; and the conformal coating may be provided following placement of the die on the support.

Abstract: A method of making a microelectronic assembly can include molding a dielectric material around at least two conductive elements which project above a height of a substrate having a microelectronic element mounted thereon, so that remote surfaces of the conductive elements remain accessible and exposed within openings extending from an exterior surface of the molded dielectric material. The remote surfaces can be disposed at heights from said surface of said substrate which are lower or higher than a height of the exterior surface of the molded dielectric material from the substrate surface. The conductive elements can be arranged to simultaneously carry first and second different electric potentials: e.g., power, ground or signal potentials.

Abstract: A method of manufacturing a reduced free-charge carrier lifetime semiconductor structure includes forming a plurality of transistor gate structures in trenches arranged in a semiconductor substrate, forming a body region between adjacent ones of the transistor gate structures and forming an end-of-range irradiation region between adjacent ones of the transistor gate structures, the end-of-range irradiation region having a plurality of vacancies.

Abstract: A method for fabricating a power semiconductor device is disclosed. A substrate having thereon a plurality of die regions and scribe lanes is provided. A first epitaxial layer is formed on the substrate. A hard mask is formed on the first epitaxial layer. A trench is etched into the first epitaxial layer through an opening in the hard mask. The opening and the trench both traverse the die regions and scribe lanes in their longitudinal direction. The hard mask is then removed. A second epitaxial layer is formed in the trench. After polishing the second epitaxial layer, a third epitaxial layer is formed to cover the first and second epitaxial layers.

Abstract: In one general aspect, a method can include implanting a first dopant, simultaneously, in a portion of a laterally diffused metal oxide semiconductor (LDMOS) device and in a portion of a resistor device included in a semiconductor device. The method can also include implanting a second dopant, simultaneously, in a portion of the LDMOS device and in a portion of a bipolar junction transistor (BJT) device in the semiconductor device.

Abstract: A SGT production method includes a step of forming first and second fin-shaped silicon layers, forming a first insulating film, and forming first and second pillar-shaped silicon layers; a step of forming diffusion layers by implanting an impurity into upper portions of the first and second pillar-shaped silicon layers, upper portions of the first and second fin-shaped silicon layers, and lower portions of the first and second pillar-shaped silicon layers; a step of forming a gate insulating film and first and second polysilicon gate electrodes; a step of forming a silicide in upper portions of the diffusion layers formed in the upper portions of the first and second fin-shaped silicon layers; and a step of depositing an interlayer insulating film, exposing and etching the first and second polysilicon gate electrodes, then depositing a metal, and forming first and second metal gate electrodes.