Abstract: A trench MOSFET with embedded schottky rectifier having at least one anti-punch through implant region using reduced masks process is disclosed for avalanche capability enhancement and cost reduction. The source regions have a higher doping concentration and a greater junction depth along sidewalls of the trenched source-body contacts than along adjacent channel regions near the gate trenches.

Abstract: A method of forming a buried bit line is provided. A substrate is provided and a line-shaped trench region is defined in the substrate. A line-shaped trench is formed in the line-shaped trench region of the substrate. The line-shaped trench includes a sidewall surface and a bottom surface. Then, the bottom surface of the line-shaped trench is widened to form a curved bottom surface. Next, a doping area is formed in the substrate adjacent to the curved bottom surface. Lastly, a buried conductive layer is formed on the doping area such that the doping area and the buried conductive layer together constitute the buried bit line.

Abstract: An epitaxial process includes the following steps. A substrate including a first area and a second area is provided. A first gate and a second gate are formed respectively on the substrate of the first area and the second area. A first spacer and a second spacer are respectively formed on the substrate beside the first gate and the second gate at the same time. A first epitaxial structure is formed beside the first spacer and then a second epitaxial structure is formed beside the second spacer by the first spacer and the second spacer respectively.

Abstract: A method produces a transistor. The method forms a strain-producing layer on a base layer and then removes at least one portion of the strain-producing layer to create at least one opening in the strain-producing layer. This leaves first and second portions of the strain-producing layer on the substrate. The first and second portions of the strain-producing layer comprise source and drain stressor regions of the transistor. The method then grows a channel region in the opening of the strain-producing layer from the base layer, forms a gate insulator on the channel region, and forms a gate conductor on the gate insulator.

Abstract: To provide a manufacturing method of a semiconductor device including a memory cell having a higher reliability. First and second stacked structures in a memory cell formation region are formed so as to have a larger height than a third stacked structure in a transistor formation region, and then an interlayer insulating layer is formed so as to cover these stacked structures and then polished.

Abstract: A method includes recessing isolation regions, wherein a portion of a semiconductor strip between the isolation regions is over top surfaces of the recessed isolation regions, and forms a semiconductor fin. A dummy gate is formed to cover a middle portion of the semiconductor fin. An Inter-Layer Dielectric (ILD) is formed to cover end portions of the semiconductor fin. The dummy gate is then removed to form a first recess, wherein the middle portion is exposed to the first recess. The middle portion of the semiconductor fin is removed to form a second recess. An epitaxy is performed to grow a semiconductor material in the second recess, wherein the semiconductor material is between the end portions. A gate dielectric and a gate electrode are formed in the first recess. The gate dielectric and the gate electrode are over the semiconductor material.

Abstract: A process for forming reversible resistance-switching memory cells having resistance-switching nano-particles which provide a reduced contact area to top and bottom electrodes of the memory cells, thereby limiting a peak current. Recesses are formed in a layered semiconductor material above the bottom electrodes, and one or more coatings of nano-particles are applied. The nano-particles self-assemble in the recesses so that they are positioned in a controlled manner. A top electrode material is then deposited. In one approach, the recesses are formed by spaced-apart trenches, and the nano-particles self-assemble along the spaced-apart trenches. In another approach, the recesses for each resistance-switching memory cell are separate from one another, and the resistance-switching memory cells are pillar-shaped. The coatings can be provided in one layer, or in multiple layers which are separated by an insulation layer.

Abstract: Fabrication methods for semiconductor device structures are provided. In an exemplary embodiment, a method of fabricating an electrically-isolated FinFET semiconductor device includes the steps of forming a silicon oxide layer over a semiconductor substrate including a silicon material and forming a first hard mask layer over the silicon oxide layer. The method further includes the steps of forming a first plurality of void spaces in the first hard mask layer and forming a second hard mask layer in the first plurality of void spaces. Still further, the method includes the steps of removing the remaining portions of the first hard mask layer, thereby forming a second plurality of void spaces in the second hard mask layer, extending the second plurality of void spaces into the silicon oxide layer, and forming a plurality of fin structures in the extended second plurality of void spaces.

Abstract: A method for forming an isolation structure includes the following steps. A hard mask layer is formed on a substrate and a trench is formed in the substrate and the hard mask layer. A protective layer is formed to cover the trench and the hard mask layer. A first isolation material is filled into the trench. An etching process is performed to etch back part of the first isolation material.

Abstract: A method of forming a buried word line structure is provided. A first mask layer, an interlayer and a second mask layer are sequentially formed on a substrate, wherein the second mask layer has a plurality of mask patterns and a plurality of gaps arranged alternately, and the gaps includes first gaps and second gaps arranged alternately. A dielectric pattern is formed in each first gap and spacers are simultaneously formed on sidewalls of each second gap, wherein a first trench is formed between the adjacent spacers and exposes a portion of the first mask layer. The mask patterns are removed to form second trenches. An etching process is performed by using the dielectric patterns and the spacers as a mask, so that the first trenches are deepened to the substrate and the second trenches are deepened to the first mask layer.

Abstract: A substrate includes a first region having a first resistivity, for optimizing a field effect transistor, a second region having a second resistivity, for optimizing an npn subcollector of a bipolar transistor device and triple well, a third region having a third resistivity, with a high resistivity for a passive device, a fourth region, substantially without implantation, to provide low perimeter capacitance for devices.

Abstract: Methods are provided for fabricating integrated circuits. In accordance with one embodiment, the method includes forming a portion of a semiconductor substrate at least partially bounded by a confinement isolation material. A liner dielectric is formed overlying the confinement isolation material and is treated to passivate a surface thereof An epitaxial layer of semiconductor material is then grown overlying the portion of semiconductor substrate.

Abstract: According to one embodiment, a method of manufacturing a semiconductor device includes providing a substrate, supplying a first liquid including a terpene to a surface of the substrate, supplying a second liquid including a silicon-containing compound to the surface of the substrate, and converting the silicon-containing compound to a silicon oxide compound.

Abstract: Methods processing substrates are provided. The method may include providing a bonding layer between a substrate and a carrier to bond the substrate to the carrier, processing the substrate while the substrate is supported by the carrier, and removing the bonding layer to separate the substrate from the carrier. The bonding layer may include a thermosetting glue layer and thermosetting release layers provided on opposing sides of the thermosetting glue layer.

Abstract: A laser processing method for performing laser processing to a workpiece. The laser processing method includes: a filament forming step of applying a first pulsed laser beam having a transmission wavelength to the workpiece to thereby form a filament as an optical transmission line in the workpiece so that the filament extends from the surface of the workpiece to be irradiated with the first pulsed laser beam to the inside of the workpiece, the filament having a refractive index higher than that of the workpiece; and a laser processing step of applying a second pulsed laser beam to the filament after performing the filament forming step to thereby transmit the second pulsed laser beam along the filament, thereby processing the workpiece with the second pulsed laser beam.

Abstract: Laser and plasma etch wafer dicing where a mask is formed covering ICs formed on the wafer, as well as any bumps providing an interface to the ICs. The semiconductor wafer is coupled to a film frame by an adhesive film. The mask is patterned by laser scribing to provide a patterned mask with gaps. The laser scribing exposes regions of the semiconductor wafer, below thin film layers from which the ICs are formed. The semiconductor wafer is plasma etched through the gaps in the patterned mask while the film frame is maintained at an acceptably low temperature with a chamber shield ring configured to sit beyond the wafer edge and cover the frame. The shield ring may be raised and lowered, for example, on lifter pins to facilitate transfer of the wafer on frame.

Abstract: Methods of dicing substrates having a plurality of ICs. A method includes forming a mask, patterning the mask with a femtosecond laser scribing process to provide a patterned mask with gaps, and ablating through an entire thickness of a semiconductor substrate to singulate the IC. Following laser-based singulation, a plasma etch is performed to remove a layer of semiconductor sidewall damaged by the laser scribe process. In the exemplary embodiment, a femtosecond laser is utilized and a 1-3 ?m thick damage layer is removed with the plasma etch. Following the plasma etch, the mask is removed, rendering the singulated die suitable for assembly/packaging.

Abstract: A method of radiatively scribing a substantially planar semiconductor substrate using a laser scribing apparatus, uses a laser scribing head configured and arranged to produce a two-dimensional array of laser beam spots to effect the scribing. In an embodiment, the spots of the array extend substantially parallel to X and Y directions in the plane of the substrate. In an embodiment, spots at a periphery in one or both directions of the array have a lower intensity than laser beams in a central portion of the array.

Abstract: A method for producing periodic crystalline silicon nanostructures of large surface area by: generating a periodic structure having a lattice constant of between 100 nm and 2 ?m on a substrate, the substrate used being a material which is stable at up to at least 570° C., and the structure being produced with periodically repeating shallow and steep areas/flanks, and, subsequently, depositing silicon by directed deposition onto the periodically structured substrate, with a thickness in the range from 0.2 to 3 times the lattice constant, or 40 nm to 6 ?m, at a substrate temperature of up to 400° C., followed by thermally treating the deposited Si layer to effect solid-phase crystallization, at temperatures between 570° C. and 1400° C., over a few minutes up to several days, and optionally subsequently wet-chemically selective etching to remove resultant porous regions of the Si layer.

Abstract: The present disclosure relates to a nitride electronic device and a method for manufacturing the same, and particularly, to a nitride electronic device and a method for manufacturing the same that can implement various types of nitride integrated structures on the same substrate through a regrowth technology (epitaxially lateral over-growth: ELOG) of a semi-insulating gallium nitride (GaN) layer used in a III-nitride semiconductor electronic device including Group III elements such as gallium (Ga), aluminum (Al) and indium (In) and nitrogen.

Abstract: A method that includes implantation of dopants while a III-nitride body is being grown on a substrate, and an apparatus for the practice of the method.

Abstract: A method of forming an ultra-shallow junction in a semiconductor substrate. The method includes forming an amorphous region in a semiconductor substrate by performing a pre-amorphization implant step and implanting one or more dopants in the amorphous region by performing a monolayer doping step. The semiconductor substrate is then thermally treated to activate the implanted dopant in the amorphous region to thereby form an ultra-shallow junction in the semiconductor substrate. The thermal treatment can be performed without any oxide cap overlying the implanted amorphous region.

Abstract: A FinFET device is fabricated by first receiving a FinFET precursor. The FinFET precursor includes a substrate, fins on the substrate, isolation regions on sides of the fins and dummy gate stacks on the substrate including wrapping a portion of the fin, which is referred to as a gate channel region. The dummy gate stacks is removed to form a gate trench and a gate dielectric layer is deposited in the gate trench. A metal stressor layer (MSL) is conformably deposited on the gate dielectric layer. A capping layer is deposited on the MSL. A thermal treatment is applied to the MSL to achieve a volume expansion. Then the capping layer is removed and a metal gate (MG) is formed on the MSL.

Abstract: A method for processing a carrier accordance with various embodiments may include: forming a structure over the carrier, the structure including at least two adjacent structure elements arranged at a first distance between the same; depositing a spacer layer over the structure, wherein the spacer layer may be deposited having a thickness greater than half of the first distance, wherein the spacer layer may include electrically conductive spacer material; removing a portion of the spacer layer, wherein spacer material of the spacer layer may remain in a region between the at least two adjacent structure elements; and electrically contacting the remaining spacer material.

Abstract: A method for making a semiconductor device comprises forming an electrical interconnect layer, forming a first dielectric layer over the interconnect layer, forming an opening in the first dielectric layer over a first electrical interconnect of the interconnect layer, forming an aluminum layer over the first dielectric layer, etching the aluminum layer to form an aluminum die pad, forming a second dielectric layer over the aluminum die pad and the first dielectric layer, and forming a conductive via through the first and second dielectric layers to contact a second electrical interconnect of the interconnect layer.

Abstract: A device includes a first low-k dielectric layer, and a copper-containing via in the first low-k dielectric layer. The device further includes a second low-k dielectric layer over the first low-k dielectric layer, and an aluminum-containing metal line over and electrically coupled to the copper-containing via. The aluminum-containing metal line is in the second low-k dielectric layer.

Abstract: A system for forming self-aligned contacts includes electroplating a first metal contact onto a Group III-V semiconductor substrate, the first metal contact having a greater height than width and having a straight sidewall profile, etching back the semiconductor substrate down to a base layer to expose an emitter semiconductor layer under the first metal contact, conformally depositing a dielectric layer on a vertical side of the first metal contact, a vertical side of the emitter semiconductor layer and on the base layer, anisotropically etching the dielectric layer off of the semiconductor substrate to form a dielectric sidewall spacer on the vertical side of the first metal contact and providing a second metal contact immediately adjacent the dielectric sidewall spacer.

Abstract: A method of forming a contact on a semiconductor device is disclosed. The method includes: forming a mask on the semiconductor device, the mask exposing at least one contact node disposed within a trench in a substrate of the semiconductor device; performing a first substrate contact etch on the semiconductor device, the first substrate contact etch recessing the exposed contact node within the trench; removing a set of node films disposed above the exposed contact node and on the sides of the trench; and forming a contact region within the trench above the exposed contact node, the contact region contacting the substrate.

Abstract: An exposing method includes irradiating a first light having a first energy to a first exposed region of a photoresist film through a first shot region of a mask, and irradiating a second light having a second energy to the first exposed region of the photoresist film through a second shot region of the mask.

Abstract: A semiconductor manufacturing device includes a stage, a plurality of pins, and a driving unit. The stage includes a mounting surface. The mounting surface has a first region for mounting thereon a substrate, and a second region for mounting thereon a focus ring. The second region is provided to surround the first region. A plurality of holes is formed in the stage. The holes extend in a direction that intersects the mounting surface while passing through the boundary between the first region and the second region. The pins are provided in the respective holes. Each of the pins has a first and a second upper end surface. The second. upper end surface is provided above the first upper end surface, and is offset towards the first region with respect to the first upper end surface. The driving unit moves the pins up and down in the aforementioned direction.

Abstract: A wafer cleaning apparatus includes a polishing unit used in chemical mechanical polishing (CMP) of a wafer and a cleaning dispensing unit arranged to direct cleaning fluids toward a far edge of the wafer after the CMP of the wafer. A wafer cleaning method includes CMP of a wafer by a polishing unit and directing cleaning fluids toward a far edge of the wafer after the CMP of the wafer by a cleaning dispensing unit. Another method can include CMP, applying deionized water, and applying pH adjuster having a pH range from about 2 to about 13.

Abstract: A chemical mechanical polishing (CMP) composition comprising (A) inorganic particles, organic particles, or a mixture or composite thereof, (B) a glycoside of the formulae 1 to 6 wherein R1 is alkyl, aryl, or alkylaryl, R2 is H, X1, X2, X3, X4, X5, X6, alkyl, aryl, or alkylaryl, R3 is H, X1, X2, X3, X4, X5, X6, alkyl, aryl, or alkylaryl, R4 is H, X1, X2, X3, X4, X5, X6, alkyl, aryl, or alkylaryl, R5 is H, X1, X2, X3, X4, X5, X6, alkyl, aryl, or alkylaryl, and the total number of monosaccharide units (X1, X2, X3, X4, X5, or X6) in the glycoside is in the range of from 1 to 20, and (C) an aqueous medium.

Abstract: According one embodiment, a pattern formation method forming a resist layer on a pattern formation surface by pressing a template provided with a concave-convex from above the resist layer to form a resist pattern on the pattern formation surface, includes: forming a resist layer in a first region having an area smaller than an area of the pattern formation surface and in a second region other than the first region of the pattern formation surface; pressing a template against the resist layer; irradiating the resist layer with light via the template to form a first resist layer in the first region, curing of the first resist layer being suppressed, and form the resist pattern including a second resist layer, curing of the second resist layer proceeds in the second region; and removing the first resist layer from the first region, the curing of the first resist layer being suppressed.

Abstract: Boron-doped carbon-based hardmask etch processing is described. In an example, a method of patterning a film includes etching a boron-doped amorphous carbon layer with a plasma based on a combination of CH4/N2/O2 and a flourine-rich source such as, but not limited to, CF4, SF6 or C2F6.

Abstract: Methods of patterning low-k dielectric films are described. In an example, In an embodiment, a method of patterning a low-k dielectric film involves forming and patterning a metal nitride mask layer above a low-k dielectric layer. The low-k dielectric layer is disposed above a substrate. The method also involves passivating the metal nitride mask layer by treating with a plasma based on O2/N2/SixFy. The method also involves etching a portion of the low-k dielectric layer.

Abstract: A method of drilling holes comprises ductile mode drilling the holes in a component of a plasma processing apparatus with a cutting tool wherein the component is made of a nonmetallic hard and brittle material. The method comprises drilling each hole in the component by controlling a depth of cut while drilling such that a portion of the brittle material undergoes high pressure phase transformation and forms amorphous portions of the brittle material during chip formation. The amorphous portions of the brittle material are removed from each hole such that a wall of each hole formed in the component has an as drilled surface roughness (Ra) of about 0.2 to 0.8 ?m.

Abstract: Multilayered stacks having layers of silicon interleaved with layers of a dielectric, such as silicon dioxide, are plasma etched with non-corrosive process gas chemistries. Etching plasmas of fluorine source gases, such as SF6 and/or NF3 typically only suitable for dielectric layers, are energized by pulsed RF to achieve high aspect ratio etching of silicon/silicon dioxide bi-layers stacks without the addition of corrosive gases, such as HBr or Cl2. In embodiments, a mask open etch and the multi-layered stack etch are performed in a same plasma processing chamber enabling a single chamber, single recipe solution for patterning such multi-layered stacks. In embodiments, 3D NAND memory cells are fabricated with memory plug and/or word line separation etches employing a fluorine-based, pulsed-RF plasma etch.

Abstract: A wet chemical processing method and apparatus for use in semiconductor manufacturing and in other applications, is provided. The method and apparatus provide for energizing a processing liquid such as a cleaning or etching liquid using ultrasonic, megasonic or other energy waves or by combining the liquid with a pressurized gas to form a pressurized spray, or using both. The energized, pressurized fluid is directed to a substrate surface using a fluid delivery system and overcomes any surface tensions associated with liquids, solids, or air and enables the processing liquid to completely fill any holes such as contact holes, via holes or trenches, formed on the semiconductor substrate.

Abstract: A semiconductor manufacturing apparatus according to the present embodiment comprises a chamber. A chemical-agent supply part is configured to supply a water-repellent agent or an organic solvent to a surface of a semiconductor substrate having been cleaned with a cleaning liquid in the chamber. A spray part is configured to spray a water-capture agent capturing water into an atmosphere in the chamber.

Abstract: A method for forming a layer constituted by repeated stacked layers includes: forming a first layer and a second layer on a substrate under different deposition conditions to form a stacked layer, wherein the film stresses of the first and second layers are tensile or compressive and opposite to each other, and the wet etch rates of the first and second layers are at least 50 times different from each other; and repeating the above step to form a layer constituted by repeated stacked layers, wherein the deposition conditions for forming at least one stacked layer are different from those for forming another stacked layer.

Abstract: A layout decomposition method and a method for manufacturing a semiconductor device applying the same are provided. According to the layout decomposition method, a design layout is received by the logic processor of a computing system. A design rule for layout decomposition is then identified by the logic processor, including identifying dense areas (areas with densely distributed features) on a substrate, and identifying areas with odd-numbered features on the substrate. Next, a first mask with a first pattern and a second mask with a second pattern are generated corresponding to results of design rule identification by the computing system for fabricating patterns of features in at least two of the areas with odd-numbered features in one of the dense areas.

Abstract: A film forming method for forming a thin film composed of a SiOCN layer containing at least silicon (Si), oxygen (O), carbon (C) and nitrogen (N) on a surface of a workpiece within an evacuable processing vessel optionally using a silane-based gas, a hydrocarbon gas, a nitriding gas or an oxidizing gas includes forming a first film including at least Si, C and N, and forming a second film including at least Si, C and O. The forming a first film and the forming a second film are set as a cycle and the cycle is performed once or more.

Abstract: A film deposition apparatus includes a separation member that extends to cover a rotation center of the turntable and two different points on a circumference of the turntable above the turntable, thereby separating the inside of the chamber into a first area and a second area; a first reaction gas supplying portion that supplies a first reaction gas toward the turntable in the first area; a second reaction gas supplying portion that supplies a second reaction gas toward the turntable in the second area; a first evacuation port that evacuates the first reaction gas and the first separation gas that converges with the first reaction gas; and a second evacuation port that evacuates the second reaction gas and the first separation gas that converges with the second reaction gas. The separation member has a bent portion that substantially fills in a gap between the turntable and the chamber.

Abstract: A substrate processing apparatus includes a process chamber in which a substrate is accommodated; a source gas supply system configured to supply a source gas onto the substrate; first and second reactive gas supply systems configured to supply a reactive gas onto the substrate via first and second interconnected reactive gas supply pipes, wherein a gas storage unit is installed at the second reactive gas supply pipe to store the reactive gas and the reactive gas is supplied onto the substrate via the gas storage unit; and a control unit configured to control the source gas supply system to supply the source gas onto the substrate and to control the first and second reactive gas supply systems to supply the reactive gas onto the substrate via the first and second reactive gas supply pipes.

Abstract: Methods of forming a dielectric layer on a substrate are described, and may include introducing a first precursor into a remote plasma region fluidly coupled with a substrate processing region of a substrate processing chamber A plasma may be formed in the remote plasma region to produce plasma effluents. The plasma effluents may be directed into the substrate processing region. A silicon-containing precursor may be introduced into the substrate processing region, and the silicon-containing precursor may include at least one silicon-silicon bond. The plasma effluents and silicon-containing precursor may be reacted in the processing region to form a silicon-based dielectric layer that is initially flowable when formed on the substrate.

Abstract: A laser annealing method for executing laser annealing by irradiating a semiconductor film formed on a surface of a substrate with a laser beam, the method including the steps of, generating a linearly polarized rectangular laser beam whose cross section perpendicular to an advancing direction is a rectangle with an electric field directed toward a long-side direction of the rectangle or an elliptically polarized rectangular laser beam having a major axis directed toward a long-side direction, causing the rectangular laser beam to be introduced to the surface of the substrate, and setting a wavelength of the rectangular laser beam to a length which is about a desired size of a crystal grain in a standing wave direction.

Abstract: A rotary plug includes a base, a plurality of annular slot structures, a plurality of conductive components, a bridging component and a plurality of terminals. An accommodating space is formed on the base. The annular slot structures are respectively disposed on an inner wall of the accommodating space. Each conductive component is disposed inside the corresponding annular slot structure. A protrusion of the conductive component inserts into a hole formed on the annular slot structure. The bridging component is rotatably disposed inside the accommodating space. A first end of the terminal protrudes from a bottom of the bridging component. A second end of the terminal protrudes from a lateral surface of the bridging component and movably inserts into the annular slot structure to electrically contact the conductive component.

Abstract: Embodiments described herein disclose a conductive hinge that is configured to transfer power across a hinge regardless of the orientation of the faces of the hinge. In embodiments, the conductive hinge may be configured to be a conductive conduit to transfer constant power across the hinge. The conductive hinge may be used in conjunction with a conventional hinge, retrofitted to an existing hinge, and/or disposed within a hinge.

Abstract: A wearable connector includes a housing having a base and a shroud that extends from the base. The shroud includes a tunnel having an open end and an interior surface. The open end of the tunnel is configured to receive a mating connector therein. The base is configured to be mounted to a wearable article. Terminals are held directly by the shroud such that mating segments of the terminals extend at least one of directly on or through the interior surface of the tunnel. The tunnel of the shroud is configured to receive the mating connector into the tunnel through the open end such that the mating segments of the terminals mate with mating terminals of the mating connector within the tunnel.

Abstract: A signal test device includes a metal housing, a circuit board, a protection housing, and a number of fasteners. The circuit board is received in the metal housing. A number of sub-miniature-A (SMA) connectors are mounted to a first side of the circuit board. Each SMA connector includes a base body connected to the circuit board, and a connection head connected to the base body and extending out of the metal housing. An interface is mounted to a second side of the circuit board and extending out of the metal housing. The protection housing is mounted to the second end of the circuit board and is received in the metal housing. The first fasteners extend through and fastened to the base bodies and the circuit board. Opposite ends of each first fastener abut against top and bottom of the inner surface of the metal housing.