Abstract: An integrated die-level camera system and method of making the camera system include a first die-level camera formed at least partially in a die. A second die level camera is also formed at least partially in the die. Baffling is formed to block stray light between the first and second die-level cameras.

Abstract: A silicon solar cell having a silicon substrate includes p-type and n-type emitters on a surface of the substrate, the emitters being doped nano-particles of silicon. To reduce high interface recombination at the substrate surface, the nano-particle emitters are preferably formed over a thin interfacial tunnel oxide layer on the surface of the substrate.

Abstract: A method of making a photovoltaic device is presented. The method includes disposing an absorber layer on a window layer. The method further includes treating at least a portion of the absorber layer with a first solution including a first metal salt to form a first component, wherein the first metal salt comprises a first metal selected from the group consisting of manganese, cobalt, chromium, zinc, indium, tungsten, molybdenum, and combinations thereof. The method further includes treating at least a portion of the first component with cadmium chloride to form a second component. The method further includes treating at least a portion of the second component with a second solution including a second metal salt to form an interfacial layer on the second component, wherein the second metal salt comprises a second metal selected from the group consisting of manganese, cobalt, nickel, zinc, and combinations thereof.

Abstract: Embodiments of the present invention generally include methods for forming semiconductor films having nominal I2-II-IV-VI4 stoichiometry, such as CZTS or CZTSSe, using a solution of including sources of the I, II, IV, and VI elements in a liquid solvent. Precursors may be mixed in the solvent to form the solution. Metal halide salts may be used as precursors in some examples. The solution may be coated onto a substrate and annealed to yield the semiconductor film. In some examples, the source of the ‘I’ and ‘IV’ elements may contain the elements in a +2 oxidation state, while the semiconductor film may contain the ‘I’ element in a +1 oxidation state and the ‘IV’ element in a +4 oxidation state. Examples may be used to provide I2-(II,IV)-IV-VI4 films.

Abstract: A CIGS film production method is provided which ensures that a CIGS film having a higher conversion efficiency can be produced at lower costs at higher reproducibility even for production of a large-area device. A CIGS solar cell production method is also provided for producing a CIGS solar cell including the CIGS film. The CIGS film production method includes: a stacking step of stacking a layer (A) containing indium, gallium and selenium and a layer (B) containing copper and selenium in a solid phase in this order over a substrate; and a heating step of heating a stacked structure including the layer (A) and the layer (B) to melt a compound of copper and selenium of the layer (B) into a liquid phase to thereby diffuse copper from the layer (B) into the layer (A) to permit crystal growth to provide a CIGS film.

Abstract: In a thin film photoelectric conversion device fabricated by addition of a catalyst element with the use of a solid phase growth method, defects such as a short circuit or leakage of current are suppressed. A catalyst material which promotes crystallization of silicon is selectively added to a second silicon semiconductor layer formed over a first silicon semiconductor layer having one conductivity type, the second silicon semiconductor layer is partly crystallized by a heat treatment, a third silicon semiconductor layer having a conductivity type opposite to the one conductivity type is stacked, and element isolation is performed at a region in the second silicon semiconductor layer to which a catalyst material is not added, so that a left catalyst material is prevented from being diffused again, and defects such as a short circuit or leakage of current are suppressed.

Abstract: The present invention provides a binder-free process for preparing a photoanode of flexible dye-sensitized solar cell, comprising: (a) preparing a TiO2 suspension fluid comprising TiO2, acetylacetone and anhydrous ethanol; (b) preparing a charge solution comprising iodine, ketone and deionized water; (c) mixing said TiO2 suspension fluid and said charge solution to obtain an electrophoresis suspension; (d) soaking a substrate and a cathode into the electrophoresis suspension and proceeding electrophoresis to obtain an TiO2 deposited substrate, in which said substrate and said cathode are flexible; (e) heating the TiO2 deposited substrate; and (f) compressing the heated TiO2 substrate to obtain the photoanode.

Abstract: The present invention provides a conductive paste characterized by a crystal-based corrosion binder being combined with a glass frit and mixed with a metallic powder and an organic carrier. Methods for preparing each components of the conductive paste are disclosed including several embodiments of prepare Pb—Te—O-based crystal corrosion binder characterized by melting temperatures in a range of 440° C. to 760° C. and substantially free of any glass softening transition upon increasing temperature. Method for preparing the conductive paste includes mixture of the components and a grinding process to ensure all particle sizes in a range of 0.1 to 5.0 microns. Method of applying the conductive paste for the formation of a front electrode of a semiconductor device is presented to illustrate the effectiveness of the crystal-based corrosion binder in transforming the conductive paste to a metallic electrode with good ohmic contact with semiconductor surface.

Abstract: Antimony, germanium and tellurium precursors useful for CVD/ALD of corresponding metal-containing thin films are described, along with compositions including such precursors, methods of making such precursors, and films and microelectronic device products manufactured using such precursors, as well as corresponding manufacturing methods. The precursors of the invention are useful for forming germanium-antimony-tellurium (GST) films and microelectronic device products, such as phase change memory devices, including such films.

Abstract: A method for controlling the concentration of a donor in a Ga2O3-based single crystal includes: a step in which a Group IV element is implanted as a donor impurity in a Ga2O3-based single crystal by ion implantation process to form, in the Ga2O3-based single crystal, a donor impurity implantation region that has a higher concentration of the Group IV element than the region in which the Group IV element has not been implanted; and a step in which annealing at 800 C or higher is conducted to activate the Group IV element present in the donor impurity implantation region and thereby form a high-donor-concentration region. Thus, the donor concentration in the Ga2O3-based single crystal is controlled.

Abstract: A wafer seal ring may be formed on a wafer having a pattern structure with a pattern density. The wafer seal ring pattern structure may include a plurality of lines having a width and a spacing that may be approximately equal to a width and a spacing of die bond rings on the wafer. The wafer having the wafer seal ring formed thereon may be bonded to a wafer that may not have a wafer seal ring. A pair of wafers may be formed with respective wafer seal rings formed in a corresponding manner. The pair of wafers may be bonded together with the wafer seal rings aligned and bonded together to form a seal ring structure between the bonded wafers.

Abstract: Disclosed herein are a power module package and a method for manufacturing the same. The power module package includes: first and second lead frames arranged to face each other, both or either of the first and second frames being made of aluminum; anodized layers formed on portions of the lead frame(s) made of aluminum in the first and second lead frames; and semiconductor devices mounted on first surfaces of the first and second lead frames.

Abstract: A method of forming a hybridized device comprising forming a first microelectronic component provided, on a surface, with metal balls, and a second microelectronic component provided, on a surface, with connection elements corresponding to said metal balls, and hybridizing the first and second components to attach the metal balls of the first component to the connection elements of the second component. The manufacturing of the second microelectronic component comprises forming a substrate provided with cavities at the locations provided for the connection elements, and forming resistive elements made of fusible metal respectively suspended above the cavities. The hybridizing of the first and second components comprises transferring the first component onto the second component to have the metal balls rest on the suspended resistive elements, and circulating an electric current through the resistive elements to melt said elements.

Abstract: A small form factor near chip scale package is provided that includes input/output contacts not only along the periphery of the package, but also along the package bottom area. Embodiments provide these additional contacts through use of an array lead frame coupled to under die signal contacts through the use of flip chip bonding techniques. The array lead frame contacts are electrically isolated through the use of a partial sawing process performed during package singulation.

Abstract: A semiconductor device includes: a semiconductor substrate; a heat sink mounted on an upper surface of the semiconductor substrate; wirings formed on a lower surface of the semiconductor substrate; and the like. The heat sink is mounted on the upper surface of the semiconductor substrate, and a planar size thereof is approximately the same as that of the semiconductor substrate. Moreover, the heat sink has a thickness of 500 ?m to 2 mm, and may be formed to be thicker than the semiconductor substrate. By using the heat sink to reinforce the substrate, a thickness of the semiconductor substrate can be reduced to, for example, about 50 ?m. As a result, a thickness of the entire semiconductor device can be reduced.

Abstract: Grooves are formed on the front surfaces of first and second semiconductor wafers each including an aggregate of a plurality of semiconductor chips. The grooves each extend on a dicing line set between the semiconductor chips and to have a larger width than the dicing line. Thereafter the first and second semiconductor wafers are arranged so that the front surfaces thereof are opposed to each other, and the space between the first semiconductor wafer and the second semiconductor wafer is sealed with underfill. Thereafter the rear surfaces of the first and second semiconductor wafers are polished until at least the grooves are exposed, and a structure including the first and second semiconductor wafers and the underfill is cut on the dicing line.

Abstract: A stacked structure includes a first die bonded over a second die. The first die has a first die area defined over a first surface. At least one first protective structure is formed over the first surface, around the first die area. At least one side of the first protective structure has at least one first extrusion part extending across a first scribe line around the protective structure. The second die has a second die area defined over a second surface. At least one second protective structure is formed over the second surface, around the second die area. At least one side of the second protective structure has at least one second extrusion part extending across a second scribe line around the protective structure, wherein the first extrusion part is connected with the second extrusion part.

Abstract: A method for forming a thin semiconductor device is disclosed. In one embodiment, a lead frame is provided over a carrier. At least one semiconductor chip is provided on the lead frame and the at least one semiconductor chip is enclosed with an encapsulating material. The thickness of the at least one semiconductor chip and the encapsulating material are reduced. At least one through connection is formed in the encapsulating material and at least one electrical contact element is formed over the at least one semiconductor chip and the at least one through connection.

Abstract: Disclosed herein is a power module package including an external connection terminal, a substrate in which a fastening unit allowing one end of the external connection terminal to be insertedly fastened thereinto is formed to penetrate in a thickness direction thereof, and a semiconductor chip mounted on one surface of the substrate.

Abstract: Microelectronic components and methods forming such microelectronic components are disclosed herein. The microelectronic components may include a plurality of electrically conductive vias in the form of wire bonds extending from a bonding surface of a substrate, such as surfaces of electrically conductive elements at a surface of the substrate.

Abstract: It is an object of the invention to improve the production efficiency in sealing a thin film integrated circuit and to prevent the damage and break. Further, it is another object of the invention to prevent a thin film integrated circuit from being damaged in shipment and to make it easier to handle the thin film integrated circuit. The invention provides a laminating system in which rollers are used for supplying a substrate for sealing, receiving IC chips, separating, and sealing. The separation, sealing, and reception of a plurality of thin film integrated circuits can be carried out continuously by rotating the rollers; thus, the production efficiency can be extremely improved. Further, the thin film integrated circuits can be easily sealed since a pair of rollers opposite to each other is used.

Abstract: A method includes growing an epitaxy semiconductor layer over a semiconductor substrate. The epitaxy semiconductor layer is of a first conductivity type. A Lateral Insulated Gate Bipolar Transistor (LIGBT) is formed at a front surface of the epitaxy semiconductor layer. After the LIGBT is formed, a backside thinning is performed to remove the semiconductor substrate. An implantation is performed from a backside of the epitaxy semiconductor layer to form a heavily doped semiconductor layer. The heavily doped semiconductor layer is of a second conductivity type opposite the first conductivity type.

Abstract: An embodiment of the invention relates to a TFT-LCD array substrate comprising a substrate, a gate line and a data line formed on the substrate, a pixel electrode and a thin film transistor formed in a pixel region defined by the gate line and the data line, wherein the thin film transistor comprises a gate electrode, a source electrode, and a transparent drain electrode, and the transparent drain electrode is electrically connected with the pixel electrode.

Abstract: Disclosed herein is a method for fabricating a complementary tunneling field effect transistor based on a standard CMOS IC process, which belongs to the field of logic devices and circuits of field effect transistors in ultra large scaled integrated (ULSI) circuits. In the method, an intrinsic channel and body region of a TFET are formed by means of complementary P-well and N-well masks in the standard CMOS IC process to form a well doping, a channel doping and a threshold adjustment by implantation. Further, a bipolar effect in the TFET can be inhibited via a distance between a gate and a drain on a layout so that a complementary TFET is formed. In the method according to the invention, the complementary tunneling field effect transistor (TFET) can be fabricated by virtue of existing processes in the standard CMOS IC process without any additional masks and process steps.

Abstract: Consistent with an example embodiment, a method of may be provided to manufacture a vertical capacitor region that comprises a plurality of said trenches, wherein the portions of the semiconductor region in between said trenches comprise an impurity. This allows for the trenches to be placed in closer vicinity to each other, thus improving the capacitance per unit area ratio. The total capacitance of the device is defined by two series components, that is, the capacitance across the dielectric liner, and the depletion capacitance of the silicon next to the trench. An increase of the voltage on the capacitor increases the depletion in the silicon and the depletion capacitance as a result, such that the overall capacitance is reduced. This effect may be countered by minimizing the depletion region which may be achieved by ensuring that the silicon adjacent to the capacitor is as highly doped as possible.

Abstract: Provided are a semiconductor device and a method of fabricating the same. The method may include forming an electrode structure including insulating layers and electrode layers alternatingly stacked on a substrate, forming a channel hole to penetrate the electrode structure, forming a data storage layer on a sidewall of the channel hole, and forming a semiconductor pattern on a sidewall of the data storage layer to be electrically connected to the substrate. The electrode layers may be metal-silicide layers, and the insulating layers and the electrode layers may be formed in an in-situ manner using the same deposition system.

Abstract: A method includes recessing a portion of a semiconductor substrate between opposite isolation regions to form a recess. After the step of recessing, the portion of the semiconductor substrate includes a top surface. The top surface includes a flat surface, and a slant surface having a (111) surface plane. The slant surface has a bottom edge connected to the flat surface, and a top edge connected to one of the isolation regions. The method further includes performing an epitaxy to grow a semiconductor material in the recess, wherein the semiconductor material is grown from the flat surface and the slant surface, and performing an annealing on the semiconductor material.

Abstract: A method of fabricating a semiconductor device is described. The method of fabricating a semiconductor device comprises providing a fin formed to protrude from a substrate and a plurality of gate electrodes formed on the fin to intersect the fin; forming first recesses in the fin on at least one side of the respective gate electrodes; forming an oxide layer on the surfaces of the first recesses; and expanding the first recesses into second recesses by removing the oxide layer. Related devices are also disclosed.

Abstract: A FinFET comprises an isolation region formed in a substrate, a cloak-shaped active region formed over the substrate, wherein the cloak-shaped active region has an upper portion protruding above a top surface of the isolation region. In addition, the FinFET comprises a gate electrode wrapping the channel of the cloak-shaped active region.

Abstract: A method of forming a semiconductor device includes forming first sacrificial patterns on a substrate, the first sacrificial patterns spaced apart from each other, forming a capping layer on the first sacrificial patterns, forming a gap insulating layer spaced apart from a lower portion of the capping layer between the first sacrificial patterns in a vertical direction, planarizing the gap insulating layer and the capping layer to expose the first sacrificial patterns, removing the first sacrificial patterns to form trenches, and forming conductive patterns in the trenches, the conductive patterns having an air gap therebetween and between the lower portion of the capping layer and the gap insulating layer.

Abstract: Semiconductor structures and devices including strained material layers having impurity-free zones, and methods for fabricating same. Certain regions of the strained material layers are kept free of impurities that can interdiffuse from adjacent portions of the semiconductor. When impurities are present in certain regions of the strained material layers, there is degradation in device performance. By employing semiconductor structures and devices (e.g., field effect transistors or “FETs”) that have the features described, or are fabricated in accordance with the steps described, device operation is enhanced.

Abstract: One example of a method disclosed herein for forming a gate electrode in a field effect transistor comprises forming a gate structure above a semiconductor substrate, the gate structure comprising a gate electrode and a gate cap layer positioned above the gate electrode, forming sidewall spacers adjacent the sidewalls of the gate structure, forming a semiconductor layer above portions of the source/drain regions not covered by the gate structure and the sidewall spacers and performing at least one etching process to remove the gate cap layer from above the gate electrode and to remove at least a portion of the semiconductor layer.

Abstract: A method of manufacturing a semiconductor device includes providing a substrate having a gate stack, and performing a pre-amorphous implantation (PAI) process to form an amorphized region on the substrate. The method also includes performing an annealing process to recrystallize the amorphized region after the stress film is formed. The annealing process includes a preheat at a temperature in a range from about 400° C. to about 550° C. and an annealing temperature equal to or greater than about 900° C., and the annealing process recrystallizes the amorphized region.

Abstract: A method for producing a semiconductor device is disclosed. The method includes providing a semiconductor body having a first surface, and a second surface opposite the first surface, producing a first trench having a bottom and sidewalls and extending from the first surface into the semiconductor body, forming a dielectric layer along at least one sidewall of the trench, and filling the trench with a filling material. Forming the dielectric layer includes forming a protection layer on the least one sidewall such that the protection layer leaves a section of the at least one sidewall uncovered, oxidizing the semiconductor body in the region of the uncovered sidewall section to form a first section of the dielectric layer, removing the protection layer, and forming a second section of the dielectric layer on the at least one sidewall.

Abstract: Methods are provided for fabricating an integrated circuit that includes gate to active contacts. One method includes forming a dummy gate structure including a dummy gate electrode having sidewalls and overlying a semiconductor substrate and first and second sidewall spacers on the sidewalls of the dummy gate electrode. The method includes removing the dummy gate electrode to form a trench bounded by the first and second sidewall spacers. The method removes an upper portion of the first sidewall spacer and deposits a layer of metal in the trench and over a remaining portion of the first sidewall spacer to form a gate electrode and an interconnect.

Abstract: A method of manufacturing an IC, comprising providing a substrate having a first side and a second opposite side, forming a STI opening in the first side of the substrate and forming a partial TSV opening in the first side of the substrate and extending the partial TSV opening. The extended partial TSV opening is deeper into the substrate than the STI opening. The method also comprises filling the STI opening with a first solid material and filling the extended partial TSV opening with a second solid material. Neither the STI opening, the partial TSV opening, nor the extended partial TSV opening penetrate an outer surface of the second side of the substrate. At least either: the STI opening and the partial TSV opening are formed simultaneously, or, the STI opening and the extended partial TSV opening are filled simultaneously.

Abstract: A method of fabricating a semiconductor device includes forming at least one trench from a top side of a semiconductor layer, wherein the trench is lined with a trench dielectric liner and filled by a first polysilicon layer. The surface of the trench dielectric liner is etched, wherein dips in the trench dielectric liner are formed relative to a top surface of the first polysilicon layer which results in forming a protrusion including the first polysilicon layer. The first polysilicon layer is etched to remove at least a portion of the protrusion. A second dielectric layer is formed over at least the trench after etching the first polysilicon layer. A second polysilicon layer is deposited. The second polysilicon layer is etched to remove it over the trench and provide a patterned second polysilicon layer on the top side of the semiconductor layer.

Abstract: A method of manufacturing an isolation structure includes forming a laminate structure on a substrate. A plurality trenches is formed in the laminate structure. Subsequently a pre-processing is effected to form a hydrophilic thin film having oxygen ions on the inner wall of the trenches. Spin-on-dielectric (SOD) materials are filled into the trenches. The hydrophilic think film having oxygen ions changes the surface tension of the inner wall of the trenches and increases SOD material fluidity.

Abstract: A method includes forming an electrical insulator material over an integrated circuit having a metal-containing conductive interconnect and activating a dopant in a semiconductor material of a substrate to provide a doped region. The doped region provides a junction of opposite conductivity types. After activating the dopant, the substrate is bonded to the insulator material and at least some of the substrate is removed where bonded to the insulator material. After the removing, a memory cell is formed having a word line, an access diode, a state-changeable memory element containing chalcogenide phase change material, and a bit line all electrically connected in series, the access diode containing the junction as a p-n junction. A memory device includes an adhesion material over the insulator material and bonding the word line to the insulator material.

Abstract: A method for wafer transfer includes forming a spreading layer, including graphene, on a single crystalline SiC substrate. A semiconductor layer including one or more layers is formed on and is lattice matched to the crystalline SiC layer. The semiconductor layer is transferred to a handle substrate, and the spreading layer is split to remove the single crystalline SiC substrate.

Abstract: A method is disclosed for separating a support substrate from a solid-phase bonded wafer which includes a Si wafer and support substrate solid-phase bonded to back surface of the Si wafer. The method includes a step of irradiating the Si wafer with laser light with a wavelength which passes through the Si wafer and is focused on a solid-phase bonding interface between the Si wafer and support substrate to form a breaking layer in at least part of an outer circumferential portion of the solid-phase bonding interface, a step of separating the breaking layer; and a step of separating the solid-phase bonding interface. The method is capable of using a Si thin wafer without substantial wafer cracking at an initial stage where the wafer is inputted to a wafer process, capable of separating a support substrate from the Si thin wafer easily, and capable of reducing the wafer cost.

Abstract: A semiconductor structure includes a III-V monocrystalline layer and a germanium surface layer. An interlayer is formed directly between the III-V monocrystalline layer and the germanium surface layer from a material selected to provide stronger nucleation bonding between the interlayer and the germanium surface layer than nucleation bonding that would be achievable directly between the III-V monocrystalline layer and the germanium surface layer such that a continuous, relatively defect-free germanium surface layer is provided.

Abstract: Fabricating of one or more semiconductor devices with critical gate dimension control is facilitated by: providing a multilayer stack structure over a substrate; etching through the multilayer stack structure, with critical gate dimension control, to define multiple gate lines; providing a protective layer over the multiple gate lines; and patterning and cutting one or more gate lines of the multiple gate lines to facilitate defining multiple gate structures of the one or more semiconductor devices. Etching through the multilayer stack structure is facilitated by lithographically patterning the multilayer stack structure, and critical dimension feedback control is provided to at least one of the lithographically patterning or the etching through the multilayer stack structure.

Abstract: If an optical path length of an optical system is reduced and a length of a laser light on an irradiation surface is increased, there occurs curvature of field which is a phenomenon that a convergent position deviates depending on an incident angle or incident position of a laser light with respect to a lens. To avoid this phenomenon, an optical element having a negative power such as a concave lens or a concave cylindrical lens is inserted to regulate the optical path length of the laser light and a convergent position is made coincident with a irradiation surface to form an image on the irradiation surface.

Abstract: A method of forming an integrated circuit comprises forming a gate of a transistor over a substrate. The method further comprises forming a connecting line over the substrate, the connecting line being coupled with an active area of the transistor. The method also comprises forming a dielectric layer surrounding the gate and the connecting line. The method additionally comprises forming an etch stop layer over the dielectric layer and covering a portion of a top surface of the connecting line. The method further comprises forming a via structure comprising a via in physical contact with a top surface of the gate and another portion of the top surface of the connecting line. The method also comprises forming a metallic line structure being coupled with the via structure.

Abstract: Methods of fabricating semiconductor devices and structures thereof are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming a gate material stack over a substrate having a first region and a second region. The gate material stack includes a semiconductive gate material. A thickness is altered or a substance is introduced to the semiconductive gate material in the first region or the second region of the substrate. The gate material stack is patterned in the first region and the second region resulting in a first transistor in the first region of the substrate comprising an NMOS FET of a CMOS device and a second transistor in the second region of the substrate comprising an NMOS FET of the CMOS device. The first transistor has a first threshold voltage and the second transistor has a second threshold voltage different than the first threshold voltage.

Abstract: A process of manufacturing a Write-Once-Read-Many-times memory, at least includes the following steps: (A) providing a substrate as a lower electrode; (B) depositing a first oxide layer on the substrate; (C) depositing at least one or more silicon/germanium (Si/Ge) layers on the first oxide layer; (D) depositing a second oxide layer on the at least one or more Si/Ge layers; (E) carrying out a rapid thermal annealing to form SiGe nanocrystals embedded in the first dioxide layer and the second oxide layer; and (F) depositing a conductive layer on the second oxide layer as an upper electrode. The SiGe nanocrystals embedded in the Al2O3 bilayer as the active layer of the WORM memory offers high thermal stability, so that low operating voltage, fast writing, ideal reading durability, persistence at high temperature, and the highly reliable memory performance for effectively reading data at high temperature can be achieved.

Abstract: Described are methods for controlling the doping of metal nitride films such as TaN, TiN and MnN. The temperature during deposition of the metal nitride film may be controlled to provide a film density that permits a desired amount of doping. Dopants may include Ru, Cu, Co, Mn, Mo, Al, Mg, Cr, Nb, Ta, Ti and V. The metal nitride film may optionally be exposed to plasma treatment after doping.

Abstract: In some embodiments, the present disclosure pertains to methods of preparing graphene nanoribbons from a graphene film associated with a meniscus, where the method comprises patterning the graphene film while the meniscus acts as a mask above a region of the graphene film, and where the patterning results in formation of graphene nanoribbons from the meniscus-masked region of the graphene film. Additional embodiments of the present disclosure pertain to methods of preparing wires from a film associated with a meniscus, where the method comprises patterning the film while the meniscus acts as a mask above a region of the film, and where the patterning results in formation of a wire from the meniscus-masked region of the film. Additional embodiments of the present disclosure pertain to chemical methods of preparing wires from water-reactive materials.

Abstract: A method of forming external terminals of a package is provided in which a package substrate may be fixed, an edge portion of the package substrate may be supported to prevent the edge portion of the package substrate from being upwardly bent, a mask having openings may be arranged on the package substrate, and the external terminals may be supplied to the package substrate through the openings of the mask. The supporting portion may downwardly press the edge portion of the package substrate so that the edge portion of the package substrate may not be upwardly bent. As a result, the external terminals on the package substrate may have a uniform thickness.