Patents Issued in August 28, 2014
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Publication number: 20140239996Abstract: A test apparatus for testing a semiconductor device includes a circuit board having a contact pattern on one side and an opening therethrough, and a probe card supporting a probe needle array. The probe needle array is insertable into the opening of the circuit board and is configured to probe a device under test. The probe needle array is in electrical contact with the contact pattern of the circuit board, to allow signals through the probe card and circuit board to a test equipment. A holder supports the probe card and other probe cards. The holder has multiple sides, each of which is supportable of a probe card having a probe needle array. The holder is rotatable to manipulate and position the probe needle arrays of the probe cards relative to a device under test. The holder allows disconnection and replacement of the probe needle arrays from the holder.Type: ApplicationFiled: July 6, 2012Publication date: August 28, 2014Applicants: INTEL CORPORATION, CELADON SYSTEMS, INC.Inventors: Bryan J. Root, William A. Funk, Michael Palumbo, John L. Dunklee
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Publication number: 20140239997Abstract: Electrical characteristics are measured accurately, even for solar battery cells having a busbarless structure. This invention, which has a plurality of probe pins which are brought into contact with a linear electrode formed on the surface of a solar battery cell, and a holder for holding the probe pins, is provided with: a current measuring terminal that is formed by a plurality of probe pins arranged thereon, and disposed on the linear electrode so as to measure current characteristics of the solar battery cell; and a voltage measuring terminal that is formed by a plurality of probe pins arranged thereon, and disposed on the linear electrode so as to measure voltage characteristics of the solar battery cell, and in this structure, the current measuring terminal and the voltage measuring terminal are disposed in parallel with each other.Type: ApplicationFiled: October 11, 2012Publication date: August 28, 2014Applicant: Dexerials CorporationInventors: Akifumi Higuchi, Hideaki Okumiya
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Publication number: 20140239998Abstract: In one embodiment, a method of testing a semiconductor component includes loading a plurality of semiconductor components into a main turret of a turret handler, transporting the plurality of semiconductor components using the main turret to a test area, and splitting the plurality of semiconductor components into a first set and a second set. The method further includes testing a first semiconductor component in the first set at a first test pad using a tester while transporting a second semiconductor component in the second set to a second test pad and testing the second semiconductor component using the tester while transporting the first semiconductor component out of the first test pad. The first set and the second set are merged into the plurality of semiconductor components and the plurality of semiconductor components are transported away from the test area using the main turret.Type: ApplicationFiled: February 27, 2013Publication date: August 28, 2014Applicant: INFINEON TECHNOLOGIES AGInventors: Theng Chao Long, Nee Wan Khoo
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Publication number: 20140239999Abstract: Innovative Non-Volatile Look-Up-Table (NV-LUT) has been constructed by Single Gate Logic Non-Volatile Memory (SGLNVM) devices processed with the standard CMOS logic process. One of a pair of complementary SGLNVM devices is always programmed to the high threshold voltage state and the other remains in the low threshold voltage state. By applying digital voltage rail (VDD and VSS) to the input nodes of the pair of complementary SGLNVM devices, the output node of the pair of complementary SGLNVM devices outputs digital signals according to its configuration. The NV-LUT outputs digital signals from a plurality of pairs of complementary SGLNVM devices through a digital switching multiplexer. The NV-LUT is a good substitution for SRAM based LUT commonly used in Field Programmable Gate Array (FPGA).Type: ApplicationFiled: February 27, 2013Publication date: August 28, 2014Applicant: FLASHSILICON INCORPORATIONInventor: Lee WANG
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Publication number: 20140240000Abstract: Techniques and mechanisms dynamically configure shift registers among registers composing data registers in a circuit such as a Programmable Logic Device (PLD). A configuration bit stream used to configure the PLD may have a reduced size if “phantom bits” not corresponding to configuration elements are removed. Shift registers may be dynamically configured such that registers which do not correspond to physical configuration elements may be skipped. Thus, a PLD may be programmed with a configuration bit stream without phantom bits.Type: ApplicationFiled: February 28, 2013Publication date: August 28, 2014Inventors: Jun Pin Tan, Kiun Kiet Jong
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Publication number: 20140240001Abstract: Some embodiments provide a reconfigurable integrated circuit (“IC”). This IC has several reconfigurable circuits, each having several configurations for several configuration cycles. The reconfigurable circuits include several time-extending reconfigurable circuits. During the operation of the IC, each particular time-extending reconfigurable circuit maintains at least one of its configurations over at least two contiguous cycles, in order to allow a signal to propagate through a signal path, which contains the particular time-extending circuit, within a desired amount of time. Some embodiments provide a method of designing a reconfigurable IC that has several reconfigurable circuits, each having several configurations and operating in several reconfiguration cycles. The method identifies a signal path through the IC that does not meet a timing constraint. The signal path includes several circuits, one of which is a particular reconfigurable circuit.Type: ApplicationFiled: January 28, 2014Publication date: August 28, 2014Applicant: Tabula, Inc.Inventors: Andre Rohe, Steven Teig, Herman Schmit, Jason Redgrave, Andrew Caldwell
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Publication number: 20140240002Abstract: Disclosed is a voltage level converter that includes: a first conversion unit which receives at least one input signal of a logic 1 signal and a logic 0 signal from a signal input terminal and converts the signal; a second conversion unit and a third conversion unit which alternately output a logic ?1 signal and the logic 1 signal respectively in accordance with the input signal; a fourth conversion unit and a fifth conversion unit which alternately output the logic ?1 signal and the logic 0 signal respectively in accordance with the input signal; and a latch which has a complementary characteristic in which if a first transistor becomes an on-state, then a second transistor becomes an off-state in accordance with the input signal, and performs a positive feedback operation. A drain output of the first transistor is input to the fourth conversion unit. A drain output of the second transistor is input to the fifth conversion unit.Type: ApplicationFiled: February 20, 2014Publication date: August 28, 2014Applicant: HiDeep IncInventors: Donggu IM, Seunghyun Park, Bonkee Kim, Youngho Cho
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Publication number: 20140240003Abstract: A lock-on detection circuit for a phase-locked loop includes circuitry configured to receive first up and down outputs and second up and down outputs from one or more phase detectors and to determine from the first up and down outputs and the second up and down outputs how well the phase-locked loop is locked on to a reference clock.Type: ApplicationFiled: February 21, 2014Publication date: August 28, 2014Inventors: Fredrik Buch, Cristian Albina, Yong Yuenyongsgool
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Publication number: 20140240004Abstract: A phase coherent signal generator apparatus is disclosed that has fast frequency shifting and numerous phase memory points, outputting a coherent continuous phase signal that includes fast switched multiple different frequency bursts.Type: ApplicationFiled: February 25, 2013Publication date: August 28, 2014Inventors: RICHARD JAMES FAWLEY, HUSEIN MASOUM, ALEX SCARBRO, ANTHONY DAVID WILLIAMS
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Publication number: 20140240005Abstract: A pre-charging circuit, such as can be used to pre-charge a data bus, is presented that is largely process independent. A push-pull type of arrangement is used, where the output of the pre-charge circuit is initially connected to a supply level through one transistor, then connect to ground by another transistor. These transistors can be controlled by one or more comparators that have as inputs a reference level and feedback from the output. The reference level is generated by a circuit that tracks the threshold voltage of the other devices in the circuit in order to reduce process dependency of the output level. The circuit can also include a device to provide an extra VDD assist to the output.Type: ApplicationFiled: February 28, 2013Publication date: August 28, 2014Applicant: SanDisk Technologies Inc.Inventors: Sung-En Wang, Feng Pan
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Publication number: 20140240006Abstract: The invention concerns energy delivery system and method for a gate drive unit controlling a thyristor-based valve (19). The system comprises at least one current transformer (22) located in the main current path of the valve.Type: ApplicationFiled: February 28, 2013Publication date: August 28, 2014Applicant: ALSTOM TECHNOLOGY LTDInventors: Marek Furyk, Roman Raubo, John Schwartzenberg
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Publication number: 20140240007Abstract: A turn-on drive circuit for a power transistor comprising a first circuit comprising a resistor and capacitor in parallel and a second circuit comprising a resistor, the second circuit being in series in the drive path with the first circuit. A turn-off drive circuit for a power transistor comprising a first circuit comprising a first resistor and a second resistor in series in the drive path of the power resistor and a second circuit comprising a capacitor in parallel with one of the resistors of the first circuit.Type: ApplicationFiled: February 27, 2014Publication date: August 28, 2014Applicant: Control Techniques LimitedInventor: Richard Samuel Gibson
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Publication number: 20140240008Abstract: A system for recovering energy from a sensor couples a battery to an inductive device in the sensor for a period of time, such that a current flows through the inductive device from the battery during the time period. The connections of the inductive device are then reversed for a second period of time. During the second time period, a current flow resulting from energy stored in the inductor is allowed to flow back to the battery, such that a portion of the energy from the inductor recharges the battery during the second period of time.Type: ApplicationFiled: February 28, 2013Publication date: August 28, 2014Applicant: TEXAS INSTRUMENTS DEUTSCLAND GMBHInventors: Frank Dornseifer, Bernard Wolfgang Ruck, Erich Bayer
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Publication number: 20140240009Abstract: Methods, apparatus, and fabrication techniques relating to management of noise arising from capacitance in a clock tree of an integrated circuit. In some embodiments, the methods comprise receiving a signal to adjust a clock having a first rate to a second rate; and ramping, in response to receiving the signal, the clock from the first rate to the second rate, wherein the ramping comprises changing the frequency of the clock to at least one third rate between the first and second rates.Type: ApplicationFiled: February 25, 2013Publication date: August 28, 2014Applicant: ADVANCED MICRO DEVICES, INC.Inventors: Steven J. Kommrusch, Zihno Jusufovic
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Publication number: 20140240010Abstract: A mobile communication device includes an analog clock and a digital clock circuit. The analog clock circuit is configured to generate an oscillating output. The digital clock circuit is configured to generate a digital clock output having a frequency that is substantially equal to the frequency of the oscillating output.Type: ApplicationFiled: May 7, 2014Publication date: August 28, 2014Applicant: BlackBerry LimitedInventors: Mark A.J. CARRAGHER, John William WYNEN
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Publication number: 20140240011Abstract: A method and an arrangement for generating a clock signal by a phase locked loop in which the time for adjusting to a prescribed frequency and phase of a clock signal is reduced by virtue of the fact that a plurality of selection signals respectively shifted by a time difference delta t are generated from the divided clock signal. A comparison signal (capture) is generated under control by an edge of the reference clock and a comparison is started in the case of which what is selected is that selection signal shifted by delta t which exhibits with its edge the least possible time deviation from the edge of the comparison signal, and the selected selection signal is output.Type: ApplicationFiled: February 25, 2014Publication date: August 28, 2014Applicant: TECHNISCHE UNIVERSITAET DRESDENInventors: Sebastian HOEPPNER, Stefan HAENZSCHE
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Publication number: 20140240012Abstract: In one embodiment, a method includes determining a phase difference between a reference clock and a feedback clock in even and odd cycles for a phase lock loop (PLL). The even and odd cycles are alternating clock periods. A delta value based on the phase difference is determined. The method then adjusts a division value used by a divider to generate the feedback clock during the even cycle based on the delta value where the delta value is of a first polarity. Also, the method adjusts the division value used by the divider to generate the feedback clock during the odd cycle based on the delta value where the delta value is of a second polarity.Type: ApplicationFiled: May 1, 2014Publication date: August 28, 2014Applicant: MARVELL WORLD TRADE LTD.Inventor: Chih-Wei Yao
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Apparatuses and Methods for Compensating for Power Supply Sensitivities of a Circuit in a Clock Path
Publication number: 20140240013Abstract: Apparatuses and methods for compensating for differing power supply sensitivities of a circuit in a clock path. One such method includes altering signal timing of at least one of reference and feedback clock signals differently according to variations in power supply voltage to compensate for differences in delay power supply sensitivities of delays of a forward clock path and of a feedback clock path. Another example method includes providing an output clock signal in phase with an input clock signal and compensating for delay error between delays used in providing at least some of the delay of the output clock signal relative to the input clock signal by providing delays having power supply sensitivities resulting in a combined power supply sensitivity that is inverse to the delay error.Type: ApplicationFiled: May 5, 2014Publication date: August 28, 2014Applicant: MICRON TECHNOLOGY, INCInventors: Yantao Ma, Tyler Gomm -
Publication number: 20140240014Abstract: In a system in which the phases of a data clock signal and a data signal differ between at an input and at an output, a semiconductor integrated circuit performs a simple BER test without using external equipment and, at the same time, performs a jitter evaluation required for a margin evaluation.Type: ApplicationFiled: August 9, 2013Publication date: August 28, 2014Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Yasushi YAMAKAWA
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Publication number: 20140240015Abstract: A semiconductor device includes: a voltage-control-type clock generation circuit having a plurality of stages of first delay elements and whose oscillation frequency is controlled according to a control voltage applied to the first delay elements; a delay circuit having a plurality of stages of second delay elements connected serially; and a selection circuit selecting one from pulse signals output by the plurality of stages of respective second delay elements. The first delay elements and the second delay elements have a same structure formed on a same semiconductor substrate, and a delay amount of the second delay elements is adjusted according to the control voltage.Type: ApplicationFiled: May 7, 2014Publication date: August 28, 2014Applicant: Kabushiki Kaisha ToshibaInventors: Kazutoshi NAKAMURA, Toru TAKAYAMA, Yuki KAMATA, Akio NAKAGAWA, Yoshinobu SANO, Toshiyuki NAKA
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Publication number: 20140240016Abstract: A double-edge-triggered flip-flop circuit and a method for operating the double-edge-trigger flip-flop circuit are provided. Sub-circuits of a flip-flop circuit are coupled to a ground supply and decoupled the sub-circuits from a power supply when a clock signal is asserted. The sub-circuits generate trigger signals including a first pair of signals and a second pair of signals. The first pair of signals is evaluated, levels of the second pair of signals are maintained when the clock signal is asserted, and an output signal is transitioned to equal an input signal based on the trigger signals when the clock signal is asserted.Type: ApplicationFiled: February 22, 2013Publication date: August 28, 2014Applicant: NVIDIA CORPORATIONInventor: William J. Dally
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Publication number: 20140240017Abstract: In a master-slave flip-flop, the master latch has first and second three-state stages, and a first feedback stage. The slave latch has third and fourth three-state stages, and a second feedback stage. First and second clock switches having opposite phases are provided. The first clock switch is configured in one of the first and fourth three-state stages, and the other stage shares the first clock switch. The second clock switch is configured in one of the second and third three-state stages, and the other stage shares the second clock switch. The second three-state stage has an additional pair of complementary devices having signal paths connected in series with each other with both being gated by a data output of the slave latch. The flip-flop reduces the number of clock switches and clock switch power consumption.Type: ApplicationFiled: August 6, 2013Publication date: August 28, 2014Inventor: Zhihong Cheng
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Publication number: 20140240018Abstract: A current mode logic latch may include a sample stage and a hold stage, the hold stage comprising first and second stage transistors, first and second hold stage current sources, and a hold stage switch. The first hold stage transistor may be coupled at its drain terminal to the drain terminal of a first sample stage transistor. The second hold stage transistor may be coupled at its drain terminal to the drain terminal of a second sample stage transistor, coupled at its gate terminal to the drain terminal of the first hold stage transistor, and coupled at its drain terminal to a gate terminal of the first hold stage transistor. The first hold stage current source may be coupled to a source terminal of the first hold stage transistor. The second hold stage current source may be coupled to a source terminal of the second hold stage transistor. The hold stage switch may be coupled between the source terminal of the first hold stage transistor and the source terminal of the second hold stage transistor.Type: ApplicationFiled: May 2, 2014Publication date: August 28, 2014Applicant: Fujitsu LimitedInventors: SHUO-CHUN KAO, NIKOLA NEDOVIC
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Publication number: 20140240019Abstract: A current mode logic latch may include a sample stage and a hold stage, the hold stage comprising first and second stage transistors, first and second hold stage current sources, and a hold stage switch. The first hold stage transistor may be coupled at its drain terminal to the drain terminal of a first sample stage transistor. The second hold stage transistor may be coupled at its drain terminal to the drain terminal of a second sample stage transistor, coupled at its gate terminal to the drain terminal of the first hold stage transistor, and coupled at its drain terminal to a gate terminal of the first hold stage transistor. The first hold stage current source may be coupled to a source terminal of the first hold stage transistor. The second hold stage current source may be coupled to a source terminal of the second hold stage transistor. The hold stage switch may be coupled between the source terminal of the first hold stage transistor and the source terminal of the second hold stage transistor.Type: ApplicationFiled: May 2, 2014Publication date: August 28, 2014Applicant: Fujitsu LimitedInventors: SHUO-CHUN KAO, NIKOLA NEDOVIC
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Publication number: 20140240020Abstract: A plurality of PWM generators have user configurable time delay circuits for each PWM control signal generated therefrom. The time delay circuits are adjusted so that each of the PWM control signals arrive at their associated power transistors at the same time. This may be accomplished by determining a maximum delay time of the PWM control signal that has to traverse the longest propagation time and then setting the delay for that PWM control signal to substantially zero delay. Thereafter, all other delay time settings for the other PWM control signals may be determined by subtracting the propagation time for each of the other PWM control signals from the longest propagation time. Thereby insuring that all of the PWM control signals arrive at their respective power transistor control nodes with substantially the same time relationships as when they left their respective PWM generators.Type: ApplicationFiled: February 27, 2013Publication date: August 28, 2014Applicant: MICROCHIP TECHNOLOGY INCORPORATEDInventors: Bryan Kris, John Day, Alex Dumais, Stephen Bowling
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Publication number: 20140240021Abstract: Recycling energy in a clock distribution network is provided. A method includes creating a resonant clocking circuit including a clock grid. The method further includes providing resonant structures distributed in the clock grid. The method further includes providing switches that control the resonant structures to switch between a non-resonant mode and a resonant mode. The method further includes determining a switch size that minimizes power consumption of the resonant clocking circuit by iteratively increasing sizes of the switches and, for each iterative increase in size, determining power consumed by the resonant clocking circuit.Type: ApplicationFiled: December 20, 2013Publication date: August 28, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jason D. HIBBELER, William R. REOHR, Phillip J. RESTLE
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Publication number: 20140240022Abstract: An apparatus comprises a comparator that includes a first input, a second input and an output. The comparator is configured for measuring a difference in voltage between a source coupled to the first input and another source coupled to the second input, and providing information associated with the measured difference at the output. The apparatus also comprises a controllable current source coupled to the first input of the comparator and configured for supplying or drawing current. The apparatus also comprises a digital logic circuit that is configured for controlling an amount of current supplied or drawn by the controllable current source. The apparatus is configured for measuring a charge associated with an external source that is coupled to the first input of the comparator.Type: ApplicationFiled: May 8, 2014Publication date: August 28, 2014Applicant: Atmel CorporationInventor: Fredrik Larsen
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Publication number: 20140240023Abstract: An improved approach to direction finding using a super delta monopulse beamformer is disclosed. A super delta channel signal that includes direction finding information from two circular delta channels is formed and output by the super delta monopulse beamformer. This super delta channel signal uses only two channels, but is able to realize the accuracy of conventional three channel systems.Type: ApplicationFiled: February 27, 2013Publication date: August 28, 2014Applicant: THE AEROSPACE CORPORATIONInventor: Thomas Justin Shaw
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Publication number: 20140240024Abstract: A method and apparatus for predictive switching an output have been disclosed.Type: ApplicationFiled: February 27, 2013Publication date: August 28, 2014Inventor: Ingolf Frank
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Publication number: 20140240025Abstract: A lateral insulated gate turn-off (IGTO) device includes an n-type layer, a p-well formed in the n-type layer, a shallow n+ type region formed in the well, a shallow p+ type region formed in the well, a cathode electrode shorting the n+ type region to the p+ type region, at least one trenched gate extending through the n+ type region and into the well, a p+ type anode region laterally spaced from the well, and an anode electrode electrically contacting the p+ type anode region. The structure forms a lateral structure of NPN and PNP transistors, where the well forms the base of the NPN transistor. When a turn-on voltage is applied to the gate, the p-base has a reduced width, resulting in the beta of the NPN transistor increasing beyond a threshold to turn on the IGTO device by current feedback.Type: ApplicationFiled: February 27, 2014Publication date: August 28, 2014Applicant: PAKAL TECHNOLOGIES, LLCInventors: Richard A. Blanchard, Hidenori Akiyama, Woytek Tworzydlo
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Publication number: 20140240026Abstract: According to example embodiments, a method for controlling a gate voltage applied to a gate electrode of a high electron mobility transistor (HEMT) may include measuring a voltage between a drain electrode and a source electrode of the HEMT, and adjusting a level of the gate voltage applied to the gate electrode of the HEMT according to the measured voltage. The level of the gate electrode may be adjusted if the voltage between the drain electrode and the source electrode is different than a set value.Type: ApplicationFiled: December 16, 2013Publication date: August 28, 2014Applicant: Samsung Electronics Co., Ltd.Inventors: Sun-kyu HWANG, Woo-chul JEON, Joon-yong KIM, Ki-yeol PARK, Young-hwan PARK, Jai-kwang SHIN, Jae-joon OH, Jong-bong HA
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Publication number: 20140240027Abstract: An insulated gate turn-off (IGTO) device has a layered structure including a p+ layer (e.g., a substrate), an n-type layer, a p-type layer (which may be a p-well), n+ regions formed in the surface of the p-type layer, and insulated planar gates over the p-type layer between the n+ regions. The layered structure forms vertical NPN and PNP transistors. The p-type layer forms the base of the NPN transistor. When the gates are sufficiently positively biased, the underlying p-type layer inverts to reduce the width of the base to increase the beta of the NPN transistor. This causes the product of the betas of the NPN and PNP transistors to exceed one, and the device becomes fully conductive. When the gate voltage is removed, the base width increases such that the product of the betas is less than one, and the device shuts off. No latch-up occurs in normal operation.Type: ApplicationFiled: February 27, 2014Publication date: August 28, 2014Applicant: Pakal Technologies, LLCInventors: Richard A. Blanchard, Hidenori Akiyama, Woytek Tworzydlo, Vladimir Rodov
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Publication number: 20140240028Abstract: The preferred embodiments of the present invention use low voltage transistors to support high voltage switching circuits by connecting low voltage circuits in a stacking configuration. High voltage switching signals are divided into a plurality of small amplitude switching signals before sending into transformers, filters or other circuits. The resulting circuits can support high voltage applications while achieving cost and performance advantages of low voltage circuits.Type: ApplicationFiled: February 28, 2013Publication date: August 28, 2014Inventor: Jeng-Jye Shau
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Publication number: 20140240029Abstract: A method of operating a bridge switch control circuit is disclosed for controlling at least one pair of complementary switches. First, a first driving signal, a second driving signal, a first latching signal, and a second latching signal are provided. The first driving signal and the second driving signal drive the complementary switches. Afterward, it is to judge whether the first driving signal triggers one of the complementary switches by a rising-edge manner. If YES, the first latching signal is controlled at a high-level status and the second latching signal is simultaneously controlled at a low-level status. Afterward, it is to judge whether the second driving signal triggers the other of the complementary switches by a rising-edge manner. If YES, the second latching signal is controlled at a high-level status and the first latching signal is simultaneously controlled at a low-level status.Type: ApplicationFiled: October 21, 2013Publication date: August 28, 2014Applicant: DELTA ELECTRONICS, INC.Inventors: Te-Chih PENG, Hsin-Chung NIU
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Publication number: 20140240030Abstract: A semiconductor switch circuit includes first semiconductor switch units and second semiconductor switch units. The first semiconductor switch units each have a first threshold and two first ends. One first end is connected to a common terminal. The second semiconductor switch units each have a second threshold and two second ends. One second end is connected to the other first end of the first semiconductor switch units. The second threshold is lower than the first threshold.Type: ApplicationFiled: July 15, 2013Publication date: August 28, 2014Inventor: Takayuki Teraguchi
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Publication number: 20140240031Abstract: Various embodiments of methods and systems for tuning a thermal strategy of a portable computing device (“PCD”) based on PCD location information. In an exemplary embodiment, it may be recognized that the PCD is in an active state and producing thermal energy, or that one or more thermally aggressive components of the PCD are operating near temperature thresholds for efficient operation. The PCD location information is used to estimate the environmental ambient temperature to which the PCD is exposed. Certain embodiments may simply render the estimated ambient temperature for the benefit of the user or may use the estimated ambient temperature as an input to a program, application, or algorithm running on the PCD. It is envisioned that certain embodiments of the systems and methods may use the estimated ambient temperature to adjust temperature thresholds in the PCD against which thermal management policies govern thermally aggressive PCD components.Type: ApplicationFiled: February 27, 2013Publication date: August 28, 2014Applicant: QUALCOMM IncorporatedInventors: Unnikrishnan Vadakkanmaruveedu, Paras S. Doshi, Ankur Jain, Priyank Kumar, Vinay Mitter, Richard A. Stewart
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Publication number: 20140240032Abstract: Embodiments of the present invention provide an adaptive voltage scaling method, chip, and device. An aging effect-related state parameter in a chip is obtained at a first voltage adjustment time point. The first voltage adjustment time point is one of multiple voltage adjustment time points set for the chip. An aging compensation voltage corresponding to the first voltage adjustment time point is determined according to the state parameter. A minimum operating voltage of the chip is compensated for according to the aging compensation voltage, so as to adjust an operating voltage of the chip.Type: ApplicationFiled: February 27, 2014Publication date: August 28, 2014Applicant: HUAWEI TECHNOLOGIES CO., LTD.Inventors: Jianping Guo, Xinru Wang, Yiwei Fu
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Publication number: 20140240033Abstract: SoC and SiP designs are configured with an antifuse link within the die to allow on-die programming of bond wires connecting package lead fingers to the bond pads on the die. This permits alteration of the bond pad connections for the die, particularly for the ground voltage ground signal (VSS) connections on the bond pad, at the testing stage after the die package and the power supply have been installed on the PCB. On-die programming of antifuse link allows the VSS bond pad connections to be reconfigured, typically to eliminate long bond wire runs to reduce ground bounce and simultaneous switching output (SSO) noise, after assembly and field testing of the integrated circuit. Antifuse programming is completed by applying the programming voltage to the programming pad of the antifuse.Type: ApplicationFiled: February 26, 2013Publication date: August 28, 2014Applicant: LSI CORPORATIONInventors: Akhilesh Rathi, Arvind Shrivastava
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Publication number: 20140240034Abstract: The present disclosure relates to methods and circuits to achieve ground centered charge-pumps generating output voltages of +/?VDD/2 or +/?VDD/3 while achieving high efficiency of power conversion and minimized output impedances. Key points of the disclosure are minimizing number of switching states, reducing the time required for transition through all switching states, maintain constant flying capacitor voltages in all switching states, and, ideally, configuring the size of the flying capacitors large enough to provide the required load charge of each switching state without voltage change of the flying capacitors.Type: ApplicationFiled: March 1, 2013Publication date: August 28, 2014Applicant: DIALOG SEMICONDUCTOR GMBHInventor: Andrew Myles
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Publication number: 20140240035Abstract: An integrated circuit includes (a) an analog-to-digital converter operated according to a first clock signal; and (b) a charge pump circuit providing a negative power supply voltage to the integrated circuit, the charge pump circuit being operated according to a second clock signal having a frequency that is different from a frequency of the first clock signal, such that a noise level introduced by the charge pump into the analog-to-digital converter is less than the average noise level over a predetermined range of frequencies for the second clock signal. The integrated circuit may further include a clock divider circuit (e.g., a programmable clock divider) that generates both the first clock signal and the second clock signal.Type: ApplicationFiled: January 30, 2014Publication date: August 28, 2014Applicant: Linear Technology CorporationInventors: Michael Keith Mayes, Todd Stuart Kaplan, David Edward Bliss
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Publication number: 20140240036Abstract: Disclosed is a semiconductor device that includes an N-channel MOS transistor and a control voltage generation circuit. The N-channel MOS transistor controls the supply of a power supply voltage obtained by stepping down a DC voltage. The control voltage generation circuit clips the gate voltage of the N-channel MOS transistor at a control voltage not higher than a predetermined voltage in accordance with the DC voltage.Type: ApplicationFiled: December 5, 2013Publication date: August 28, 2014Applicant: Renesas Electronics CorporationInventor: Tatsufumi KUROKAWA
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Publication number: 20140240037Abstract: A buffer circuit includes a first current mirror circuit, a second current mirror circuit, a first transistor, and a second transistor. The first current mirror circuit passes a first mirror current through a second node, corresponding to a first current passed through a first node, and is activated based on a first activating signal. The second current mirror circuit is connected to the first node and the second node, passes a second mirror current through the second node, corresponding to a second current passed through the first node, and is activated based on a second activating signal. The first transistor has a gate to which a reference voltage is applied and has a drain connected to the first node. The second transistor has a gate to which an input voltage is applied and has a drain connected to the second node.Type: ApplicationFiled: August 6, 2013Publication date: August 28, 2014Applicant: Kabushiki Kaisha ToshibaInventor: Kosuke YANAGIDAIRA
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Publication number: 20140240038Abstract: Provided is a reference voltage generation circuit that has a flat temperature characteristic even when there are fluctuations in manufacturing step. After a semiconductor manufacturing process is finished, electrical characteristics of a semiconductor device are evaluated. Temperature characteristic of each reference voltage (VREF) of three unit reference voltage generation circuits (10) is evaluated. Then only a unit reference voltage generation circuit (10) having the most flat temperature characteristics is selected from among the three unit reference voltage generation circuits (10). Only fuses (13, 14) of the selected unit reference voltage generation circuit (10) are not cut, but other fuses (13, 14) are cut. Accordingly only the selected unit reference voltage generation circuit (10) operates, and the other unit reference voltage generation circuits (10) do not operate.Type: ApplicationFiled: February 19, 2014Publication date: August 28, 2014Applicant: SEIKO INSTRUMENTS INC.Inventor: Hideo YOSHINO
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Publication number: 20140240039Abstract: The disclosure relates to an enhanced Doherty amplifier that provides significant performance improvements over conventional Doherty amplifiers. The enhanced Doherty amplifier includes a power splitter, combining node, a carrier path, and a peaking path. The power splitter is configured to receive an input signal and split the input signal into a carrier signal provided at a carrier splitter output and a peaking signal provided at a peaking splitter output. The carrier path includes carrier power amplifier circuitry, a carrier input network coupled between the carrier splitter output and the carrier power amplifier circuitry, and a carrier output network coupled between the carrier power amplifier circuitry and the Doherty combining node.Type: ApplicationFiled: May 2, 2014Publication date: August 28, 2014Applicant: Cree, Inc.Inventor: Raymond Sydney Pengelly
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Publication number: 20140240040Abstract: A multi-mode amplifier system includes a supply converter and a multi-stage amplifier. The supply converter is configured to generate a plurality of varied supply signals according to an output power mode. The multi-stage amplifier is configured to generate an RF output signal from an RF input signal according to the varied supply signals.Type: ApplicationFiled: February 25, 2013Publication date: August 28, 2014Inventor: Andreas Langer
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Publication number: 20140240041Abstract: Provided is an operational amplifier circuit capable of operating with lower current consumption. An amplifier stage, a FIR filter, and a sample and hold circuit are connected in series, thus enabling reduction of an input offset voltage and amplification of an input signal voltage without using an integral circuit. Current consumption of the operational amplifier circuit is reduced because the integral circuit is not used.Type: ApplicationFiled: February 25, 2014Publication date: August 28, 2014Applicant: Seiko Instruments Inc.Inventor: Tsutomu TOMIOKA
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Publication number: 20140240042Abstract: There is provided an operational amplifier capable of detecting that an input terminal has been open circuited without restricting the voltage range of an input signal. The operational amplifier includes a first comparator which detects that an inverting input terminal of an operational amplifier has been open circuited, a second comparator which detects that a non-inverting input terminal of the operational amplifier has been open circuited, a first resistor and a first switch which are controlled by output signals of the first comparator and the second comparator and which are connected in series between the non-inverting input terminal and a ground terminal of the operational amplifier, and a second resistor and a second switch which are connected in series between the inverting input terminal and a supply terminal of the operational amplifier.Type: ApplicationFiled: February 26, 2014Publication date: August 28, 2014Applicant: Seiko Instruments Inc.Inventor: Toshiyuki TSUZAKI
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Publication number: 20140240043Abstract: An amplifier circuit for improved slew rate consists of three main sections, which are the common mode rejection stage, primary gain stage and the output stage. The main circuit is a modified version of the fully differential operational amplifier circuit. The modifications done to this said circuit, enhances impedance which results in improved slew rate. In addition to the modifications in the primary gain stage, there's a cascade configuration to prevent systematic offset. The common mode rejection stage is primarily used due to the narrow common mode input range resulting from the cascade configuration. Additionally, another primary gain stage is included in the design prior to the output, since the output from the primary gain stage is narrow. This structure results in producing an improved slew rate.Type: ApplicationFiled: February 27, 2014Publication date: August 28, 2014Inventor: Takashi NARITA
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Publication number: 20140240044Abstract: An operational amplifier has two paths, a high frequency path and a low frequency path. In addition, it has three main sections of stages. A stage converts input voltage to an amplified output voltage, a stage converting an input voltage in to an output current and a final stage where the outputs of the two previous sections are supplied as inputs. Among them, the final stage acts as a voltage follower to a signal applied to its plus (+) input and as a transimpedance amplifier for a signal applied to its minus input (?). In this configuration, a path for low frequencies and a path for high frequencies are created in a single operational amplifier.Type: ApplicationFiled: February 27, 2014Publication date: August 28, 2014Inventor: Takashi NARITA
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Publication number: 20140240045Abstract: A differential amplifier stage may include: a first transistor having a gate terminal; a second transistor having a gate terminal; and a voltage limiting circuit coupled to the gate terminals of the first and second transistors, wherein the voltage limiting circuit limits a gate voltage supplied to at least one of the gate terminals of the first and second transistors.Type: ApplicationFiled: February 22, 2013Publication date: August 28, 2014Applicant: Intel Mobile Communications GmbHInventors: José Moreira, Stephan Leuschner