Abstract: A semiconductor device includes a virtual power supplier, a driving signal generator and a load driver. The virtual power supplier boosts a driving voltage to generate a virtual voltage. The driving signal generator generates a driving signal based on the virtual voltage, such that the driving signal has a voltage level that is reinforced as compared with a voltage level of the driving voltage. The load driver drives a load based on the driving voltage and the driving signal.

Abstract: A STT-MRAM comprises apparatus and a method of manufacturing a spin-torque magnetoresistive memory and a plurality of a three-terminal magnetoresistive memory element having a voltage-gated recording. A bit line is coupled to the memory element through an upper electrode provided on the top surface of a reference layer, a select CMOS is coupled to the recording layer of the memory element through a middle second electrode and a VIA and a digital line is coupled to a voltage gate which is insulated from the recording layer by a dielectric layer and is used to adjust the switching write current. The fabrication includes formation of bottom digital line, formation of memory cell & VIA connection, formation of top bit line. Dual photolithography patterning and hard mask etch are used to form a small memory pillar. Ion implantation is used to convert a buried dielectric VIA into an electrical conducting path between middle memory cell and underneath CMOS device.

Abstract: A three dimensional (3D) stack of phase change memory (PCM) devices which includes PCM devices stacked in a 3D array, the PCM devices having memory regions; a memory management unit on at least one of the PCM devices; a stack controller in the memory management unit to monitor an ambient device temperature (Tambient) with respect to a neighborhood of memory regions in the PCM devices and to adjust a programming current with respect to at least one of the memory regions in the neighborhood of memory regions in accordance with the Tambient. Also disclosed is a method of programming a PCM device.

Abstract: Apparatuses, sense circuits, and methods for compensating for a voltage increase on a wordline in a memory is described. An example apparatus includes a bitline, a memory cell coupled to the bitline, a bipolar selector device coupled to the memory cell, a wordline coupled to the bipolar selector device, and a wordline driver coupled to the wordline. The apparatus further includes a model wordline circuit configured to model an impedance of the wordline and an impedance of the wordline driver, and a sense circuit coupled to the bitline and to the model wordline circuit. The sense circuit is configured to sense a state of the memory cell based on a cell current and provide a sense signal indicating a state of the memory cell. The sense circuit is further configured to adjust a bitline voltage responsive to an increase in wordline voltage as modeled by the model wordline circuit.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell which stores data with two or more levels. The memory cell includes a structure includes a first electrode layer, a first semiconductor layer, a phase change film, an electrical insulating layer, a second semiconductor layer, and a second electrode layer arranged in order thereof, and the first semiconductor layer and the second semiconductor layer have carrier polarities different from each other.

Abstract: In a semiconductor device including a memory cell array formed of memory cells using a storage element by a variable resistor and a select transistor, a buffer cell is arranged between a sense amplifier and the memory cell array and between a word driver and the memory cell array. The resistive storage element in the memory cell is connected to a bit-line via a contact formed above the resistive storage element. Meanwhile, in the buffer cell, the contact is not formed above the resistive storage element, and a state of being covered with an insulator is kept upon processing the contact in the memory cell. By such a processing method, exposure and sublimation of a chalcogenide film used in the resistive storage element can be avoided.

Abstract: A desired current through a carbon nano tube (CNT) element of a CNT memory device can be controlled by a wordline voltage, and a voltage on the CNT common node can be held constant.

Abstract: Embodiments of the disclosure include a shallow trench isolation structure having a dielectric material with energetic species implanted to a predetermined depth of the dielectric material. Embodiments further include methods of fabricating the trench structures with the implant of energetic species to the predetermined depth. In various embodiments the implant of energetic species is used to densify the dielectric material to provide a uniform wet etch rate across the surface of the dielectric material. Embodiments also include memory devices, integrated circuits, and electronic systems that include shallow trench isolation structures having the dielectric material with the high flux of energetic species implanted to the predetermined depth of the dielectric material.

Abstract: To provide a semiconductor device with such a new structure that the effect of variation in transistor characteristics can be reduced to achieve less variation in the output voltage of a memory cell. A memory cell includes a source follower (common drain) transistor for reading data held in a gate. A voltage applied to a transistor generating a reference current flowing through the memory cell is determined so that a gate-source voltage is approximately equal to the threshold voltage of the transistor. With such a structure, data stored in the memory cell can be read as a voltage that is less influenced by variation of transistors such as the field-effect mobility and the size.

Abstract: Embodiments relate to memory devices and methods for firmly programming at least a portion of a plurality of electronically programmable and erasable nonvolatile memory cells in a processing of the nonvolatile memory devices.

Abstract: Methods and apparatus are provided for computing reliability values, such as log likelihood ratios (LLRs), with reduced complexity for flash memory devices. Data from a flash memory device that stores M bits per cell using 2?M possible states is processed by obtaining at least two soft read voltage values corresponding to two reference voltages V0 and V1, wherein the two reference voltages V0 and V1 are between two adjacent states of the 2?M possible states; and converting the at least two soft read voltage values to a log likelihood ratio for a region between the two reference voltages V0 and V1 using probability density functions only for the two adjacent states. The soft read voltage values comprise, for example, hard decision read values obtained by a plurality of read retries of a given cell at a plurality of reference voltages and/or soft values obtained from the flash memory device.

Abstract: A nonvolatile semiconductor memory device according to an embodiment includes a memory cell array having a plurality of memory cell transistors connected in series therein; a plurality of bit lines; and a control circuit for executing a read operation. The control circuit is configured capable of executing the read operation, the read operation charging the bit line and applying a read voltage to the control gate electrode of the memory cell transistor to determine whether the memory cell transistor is conductive and the bit line discharges or not. The control circuit is configured to, in the read operation, be capable of executing the read operation targeting the memory cell transistors connected to a portion of the plurality of bit lines, and not execute a charging operation in those other of the bit lines where the connected memory cell transistors are not targeted by the read operation.

Abstract: According to an embodiment, a semiconductor memory device includes a memory cell array and a control circuit. The memory cell array comprises a plurality of memory cells that each include a control gate and a charge accumulation layer and that each are configured to have a threshold set to be included in any of a plurality of threshold distributions, the memory cell being connected between a bit line and a source line. The control circuit, in at least one of a write verify operation and a read operation on a selected memory cell, applies to the control gate a control gate voltage to determine the threshold of the selected memory cell, the control gate voltage having a plurality of values respectively corresponded to the plurality of threshold distributions, and sets a voltage between the bit line and the source line based on the control gate voltage.

Abstract: A method (and device) includes producing first data in a page region of a memory, the first data including a first number of memory sets, each of the memory sets having a second number of bits, where the first number is a positive number more than one and the second number is a positive number more than three. After the producing the first data in the page region of the memory, second data is produced in response to the produced first data, the second data having the first number of bits, each of the bits of the second data having a logic value that is determined by a majority of the bits included in a corresponding one of the memory sets.

Abstract: Some embodiments relate to apparatuses and methods associated with blocks of memory cells. The blocks of memory cells may include two or more sub-blocks of memory cells. Sub-blocks may comprise a vertical string of memory cells including a source select transistor and a drain select transistor. An apparatus may include two or more drain select lines, of which a first drain select line is coupled to a drain select transistor in a first sub-block of a first block and to a drain select transistor in a first sub-block of a second block. A second drain select line in the apparatus may be coupled to a drain select transistor in a second sub-block of the first block and to a drain select transistor in a second sub-block of the second block. Other apparatuses and methods are described.

Abstract: A Read Only Memory (ROM) and method for providing a high operational speed with reduced leakage, no core cell standby leakage, and low power consumption. The source of the ROM cell (NMOS) is connected to a virtual ground line (VNGD) instead of VSS. Thus, the ROM cell can be operatively coupled to the bit-line, the word-line, and the virtual ground, which also acts as a column select signal. The arrangement of the ROM is such that the virtual ground of the selected column is pulled down to a ground voltage. Non-selected columns virtual ground can be maintained at a supply voltage to ensure that unwanted columns will not have any sub-threshold current (as Vds=0). Since no pre-charging of bit-line comes in the access time path, the ROM achieves a high operational speed with reduced leakage and low power consumption.

Abstract: A memory card in a computer system includes a plurality of memory elements on a NAND flash board. The NAND flash board is connected to a controller board by a flexible connector. The flexible connector allows the memory elements and NAND flash controller to be physically separated so that waste heat from one does not impact the other. The flexible connector also allows elements to be organized to create an airflow channel. The airflow channel directs air in such a way as to enhance cooling.

Abstract: A semiconductor memory device comprises a memory string including first and second selection transistors, and first and second groups of memory cell transistors connected in series between the first and second selection transistors; a bit line and a source line respectively connected to the first and second selection transistors; first word lines respectively connected to gates of the memory cell transistors in the first group; second word lines respectively connected to gates of the memory cell transistors in the second group; first transfer transistors respectively connected to the first word lines; second transfer transistors respectively connected to the second word lines; and a control unit configured to apply a first control voltage to gates of the first transfer transistors and a second control voltage lower than the first control voltage to gates of the second transfer transistors when data is being written to memory cell transistors in the first group.

Abstract: An operating method of a nonvolatile memory is provided which includes adjusting a threshold voltage of at least one first memory cell adjacent to a substrate in each cell string to be higher than a threshold voltage distribution of an erase state; and reading a second memory cell located above the at least one first memory cell in each cell string, wherein the at least one first memory cell in each cell string is a dummy memory cell.

Abstract: Nonvolatile memory devices utilize vertically-stacked strings of nonvolatile memory cells (e.g., NAND-type strings) that can be selectively coupled to common source lines within a substrate. This selective coupling may be provided by lateral ground select transistors having different threshold voltages that account for different lateral spacings between the vertically-stacked strings of nonvolatile memory cells and the common source lines.

Abstract: A non-volatile memory, such as a one-time programmable memory, with a dual purpose read/write cache. The read/write cache is used as a write cache during programming, and stores the data to be written for a full row of the memory array. The programming operation simultaneously programs all cells in the selected row based on the contents of the write cache. In subsequent read operations, the read/write cache is used as a read cache. A full row of the array is simultaneously read in a read access, and the contents of that row are stored in the read cache. Subsequent access to that same row causes the data to be read from the read cache rather than requiring access of the array.

Abstract: A method for reading data stored in a flash memory includes at least the following steps: controlling the flash memory to perform a plurality of read operations upon a plurality of memory cells included in the flash memory; obtaining a plurality of bit sequences read from the memory cells, respectively, wherein the read operations read bits of a predetermined bit order from the memory cells by utilizing different control gate voltage settings; and determining readout information of the memory cells according to binary digit distribution characteristics of the bit sequences.

Abstract: In one embodiment, a non-volatile semiconductor storage device includes a memory cell array in which a plurality of non-volatile memory cells is aligned, and a control unit which repeats a write operation of applying a write voltage to a selected memory cell, a verify operation of checking whether or not data write is completed, and a step-up operation of stepping up the write voltage by an amount of a predetermined step-up voltage when the data write is not completed. Upon the write operation, the control unit applies a first transfer voltage, a voltage value of which is lower than the write voltage, to a first unselected memory cell which is adjacent to the selected memory cell, and applies a second transfer voltage, a voltage value of which is lower than the first transfer voltage, to a second unselected memory cell which is not adjacent to the selected memory cell.

Abstract: Systems and methods of sequentially accessing memory cells in a nonvolatile memory device (NVM) are provided. The NVM has a plurality of strings and a common signal line coupled to the plurality of strings. Each string includes a plurality of memory cells and a selection transistor coupled between the plurality of memory cells and the common signal line. A command that accesses multiple memory cells is received, a voltage is applied to a first selection transistor of a first string to electrically connect the common signal line to the first string, a pulse is applied for a predetermined time period to selection transistors of other strings, and memory cells of the first string are accessed. Advantages such as removal of boosting charges from unselected strings prior to sequentially accessing memory cells from selected strings can improve performance and reliability of NVM-based systems.

Abstract: A sensing method for a memory is provided. The memory includes: a memory cell; a reference circuit generating a reference voltage and a clamp voltage; and a current supplying circuit receiving the clamp voltage to develop a cell current passing through the memory cell to form a cell voltage, wherein the cell voltage is used for incorporating with the reference voltage to determine the information stored in the memory.

Abstract: Method and apparatus for managing data in a memory. In accordance with some embodiments, a recovery data set representing a current state of a storage device is stored in a rewritable non-volatile memory responsive to detection of a potentially imminent deactivation of the device. The recovery data set is swapped with a boot data set in said memory responsive to subsequent deactivation of the device. The boot data set is subsequently used to transition the device from a deactivated mode to an operationally ready mode during device reinitialization. The boot data set is thereafter swapped with the recovery data set to return the device to the current state.

Abstract: A semiconductor memory device includes a memory cell array including memory cells arranged therein. A first latch circuit temporarily holds data to perform a read operation and a write operation on the memory cell array. The second latch circuit temporarily holds a control signal. A control circuit controls the memory cell array, the first latch circuit and the second latch circuit. The control circuit limits an operation of the first latch circuit in a state after an operation on the memory cell array has been finished, and limits an operation of the second latch circuit based on a command supplied from external.

Abstract: Disclosed herein is an apparatus that includes: a first terminal configured to receive a serial write data signal that includes at least four bits transferred in series with each other; a second terminal configured to receive a data strobe signal; a control circuit configured to produce a plurality of internal data strobe signals in response to the data strobe signal; and a serial-to-parallel conversion circuit configured to respond to the data strobe and internal data strobe signals to convert the serial write data signal into a parallel write data signal that includes at least four bits produced in parallel to each other.

Abstract: A reference frequency setting method of a memory storage apparatus including the following steps is provided. A setting code is read from a memory module or a storage unit by a first signal transmission path and stored into a register circuit. The setting code includes a first setting information. Whether the data having a specific frequency is inputted is detected. If not, the setting code stored in the register circuit is read, such that an oscillator circuit module of the memory storage apparatus generates a first reference frequency based on the first setting information. If yes, the setting code stored in the register circuit is updated by a second signal transmission path, and the updated setting code is read, such that the oscillator circuit module generates a second reference frequency based on a second setting information. The updated setting code includes the second setting information.

Abstract: A memory element includes a nonvolatile switch to be set to a first low resistance state by applying a voltage higher than a positive threshold voltage and to a second high resistance state by applying another voltage more negative than a negative threshold voltage. The memory element further includes a volatile switch in series with the nonvolatile switch, the nonvolatile switch to be set to a third low resistance state by applying a current higher than a threshold current and to fourth high resistance state by applying a current lower than the threshold current. A method for operating a memory array with memory elements with series volatile and nonvolatile switches is also provided.

Abstract: A method of testing a semiconductor memory device is provided. Data is written to a plurality of memory cells disposed in a memory cell block of the semiconductor memory device. A first driving voltage is applied to a first group of word lines. A second driving voltage is applied to a second group of word lines. Each word line of the first group of the word lines is interposed between two neighboring word lines of the second group of the word lines. The first driving voltage has a voltage level different from that of the second driving voltage. The data is read from first memory cells coupled to the first group to determine whether each of the first memory cells is defective.

Abstract: A current flowing through a voltage line and/or a data line in a column of a tracking circuit is determined. A threshold tracking time delay of the tracking circuit is determined. Based on the determined current handled by the voltage line and/or the data line and the determined threshold tracking time delay, a plurality of columns in the tracking circuit, a number of first cells in each column of the plurality of columns, and a number of second cells in the each column of the plurality of columns are determined.

Abstract: A sense amplifier circuit is divided into a plurality of sense amplifier groups. The plurality of sense amplifier groups are each further divided into a plurality of sense units. A sense amplifier control circuit is configured to sequentially select the plurality of sense amplifier groups according to a physical address, and to sequentially select the plurality of sense units included in a selected sense amplifier group. The sense amplifier control circuit is configured to, when there is a defect related to a selected sense unit in a selected first sense amplifier group, select, in place of the first sense amplifier group, a sense unit included in a second sense amplifier group selected following after the first sense amplifier group.

Abstract: A chip die including a first input/output (I/O) pad configured to transmit/receive an I/O signal of a memory cell array included in the chip die; a second I/O pad configured to, if a stacked chip die exists on the chip die, transmit/receive a via I/O signal of the stacked chip die, and configured to, if the stacked chip die does not exist on the chip die, transmit/receive a differential I/O signal of the chip die; and an I/O driver configured to receive an operation mode signal including information as to whether the stacked chip die exists on the chip die in such a manner that the second I/O pad is configured to transmit/receive the via I/O signal or the differential I/O signal.

Abstract: A composite memory device including discrete memory devices and a bridge device for controlling the discrete memory devices in response to global memory control signals having a format or protocol that is incompatible with the memory devices. The discrete memory devices can be commercial off-the-shelf memory devices or custom memory devices which respond to native, or local memory control signals. The global and local memory control signals include commands and command signals each having different formats. The composite memory device includes a system in package including the semiconductor dies of the discrete memory devices and the bridge device, or can include a printed circuit board having packaged discrete memory devices and a packaged bridge device mounted thereto.

Abstract: A method of performing a read operation on nonvolatile memory device comprises receiving a read command, receiving addresses, detecting a transition of a read enable signal, generating a strobe signal based on the transition of the read enable signal, reading data corresponding to the received addresses, and outputting the read data after the strobe signal is toggled a predetermined number of times.

Abstract: A delay and calibration circuit for an input/output determines an appropriate delay by trying a range of different delays, and for each delay, determining the number of times that a given data sequence is accurately received. The data sequence may be a command, address, host data, or other data. Appropriate delays may be found for different temperatures.

Abstract: A memory circuit includes a bit cell that receives a word line, complementary bit lines and an array supply voltage; a word line driver coupled to the word line, the word line driver receiving one of the array supply voltage and a periphery supply voltage; and a word line suppression circuit coupled to the word line. The word line suppression circuit includes a diode and a switch coupled in series. The switch is responsive to the array supply voltage. The word line suppression circuit limits a word line voltage to a value lower than the array supply voltage such that the static noise margin (SNM) of the bit cell is increased.

Abstract: A method for repairing defective memory cells includes receiving an access command having an access address and an access operation. The access address includes a row address and a column address. The method further includes determining whether the row address and the column address are the same as a pre-recorded row address and column address of a defective memory cell. If the row and column addresses of the access address are the same as the respective row and column addresses of the defective memory cell, the method includes replacing the defective memory cell with a redundant memory cell, and executing the access operation using the redundant memory cell.

Abstract: A semiconductor memory device for performing a disable operation using an anti-fuse, and method thereof are provided. The semiconductor memory device according to an example embodiment includes a fuse circuit including at least one anti-fuse configured to store fuse data, a memory circuit configured to at least one of read data stored in a memory cell and write data to the memory cell and a fuse controller configured to disable a read/write operation of the memory circuit based on the fuse data.

Abstract: A memory structure includes a memory row of a memory array, a plurality of first bits, a first redundancy row, and a plurality of second bits. The memory row includes a plurality of memory words. The plurality of first bits is configured to indicate whether an individual memory word of the plurality of memory words of the memory row has an error. The first redundancy row includes a plurality of first redundancy words. The plurality of second bits is configured to indicate whether an individual first redundancy word of the plurality of first redundancy words of the first redundancy row has an error.

Abstract: A sense amplifier comprises a cross coupled pair of inverters, a first transistor, a second transistor, and a capacitive device. The cross coupled pair of inverters includes a first end, a second end, and a third end. The first end is configured to receive a first supply voltage. The second end is coupled with a first terminal of the capacitive device and a first terminal of the first transistor. The third end is coupled with a second terminal of the capacitive device and a first terminal of the second transistor. A second terminal of the first transistor and a second terminal of the second transistor are coupled together and are configured to receive a first control signal. A third terminal of the first transistor and a third terminal of the second transistor are coupled together and are configured to receive a second supply voltage different from the first supply voltage.

Abstract: Disclosed herein is a semiconductor device comprising complementary pair of bit lines, memory cells connected to the bit lines, dummy cells having the same structure as the memory cells, a differential sense amplifier, an equalizing circuit equalizing potentials of the bit lines, and a control circuit. The memory cells are disconnected from the bit lines and the dummy cells are connected to the bit lines, and subsequently the bit lines are equalized by the equalizing circuit. When accessing a selected memory cell, the equalizing circuit is inactivated, a corresponding dummy cell is disconnected from the bit line, and subsequently the selected memory cell is connected to the bit line. Thereafter, the sense amplifier is activated so that potentials of the bit lines are amplified respectively.

Abstract: A memory circuit includes a bit cell that receives a word line, complementary bit lines and an array supply voltage; a word line driver coupled to the word line, the word line driver receiving one of the array supply voltage and a periphery supply voltage; and a word line suppression circuit coupled to the word line. The word line suppression circuit includes a diode and a switch coupled in series. The switch is responsive to the array supply voltage. The word line suppression circuit limits a word line voltage to a value lower than the array supply voltage such that the static noise margin (SNM) of the bit cell is increased.

Abstract: Methods for reducing variability in bias voltages applied to a plurality of memory cells during a sensing operation caused by IR drops along a word line shared by the plurality of memory cells are described. In some embodiments, IR drops along a shared word line may be reduced by reducing sensing currents associated with memory cells whose state has already been determined during a sensing operation. In one example, once a sense amplifier detects that a memory cell being sensed is in a particular state, then the sense amplifier may disable sensing of the memory cell and discharge a corresponding bit line associated with the memory cell. In some cases, a bit line voltage associated with a memory cell whose state has not already been determined during a first phase of a sensing operation may be increased during a second phase of the sensing operation.

Abstract: A memory is disclosed that includes a plurality of memory cells, a plurality of sense amplifiers for reading data of the memory cells, and a voltage regulator coupled to the plurality of sense amplifiers. The voltage regulator includes a reference sense amplifier, a current injector, and a current injector control circuit. The current injector control circuit controls an amount of current provided by the current injector to an output node of the voltage regulator based on a voltage of the reference sense amplifier.

Abstract: Some embodiments relate to apparatuses and methods associated with blocks of memory cells. The blocks of memory cells may include two or more sub-blocks of memory cells. One such sub-block may comprise a vertical string of memory cells including a select transistor. An apparatus may include a sub-block disabling circuit. The sub-block disabling circuit may include a content-addressable memory. The content-addressable memory may receive an address, including a block address and a sub-block address. The content addressable memory may output a signal to disable a tagged sub-block if the received address includes the block address and the sub-block address associated with the tagged sub-block. The sub-block disabling circuit may further include a plurality of drivers to drive one or more of the select transistors based on the signal. Other apparatus and methods are described.

Abstract: A refresh address generator may include a lookup table including a first portion storing a first group of addresses associated with a first data retention time, and a second portion storing a second group of addresses associated with a second data retention time different from the first data retention time, wherein the addresses of the first portion are more frequently accessed than the addresses of the second portion to refresh the memory cells corresponding to the addresses. Systems and methods may also implement such refresh address generation.

Abstract: On the fly switching from one memory device refresh rate to another is provided. Control logic associated with the memory device detects a condition to switch from a currently-applied refresh rate to a different refresh rate. In response to the condition, the refresh rate is dynamically switched. The switching does not require a change of a mode register. Thus, a refresh rate for the memory device can be dynamically changed on the fly.

Abstract: To provide a semiconductor system including a plurality of core chips and an interface chip that controls the core chips. Each of the core chips includes an internal voltage generating circuit. The interface chip includes an unused chip information holding circuit that stores therein unused chip information of the core chips. The core chips respectively receive the unused chip information from the unused chip information holding circuit. When the unused chip information indicates an unused state, the internal voltage generating circuits are inactivated, and when the unused chip information indicates a used state, the internal voltage generating circuits are activated. With this configuration, unnecessary power consumption by the unused chips is reduced.