Abstract: There is provided a luminaire arrangement (30) comprising a luminaire holder (10) and a luminaire module (20). The luminaire holder (10) is arranged to be attached to a ground plane (32) and comprises electrical circuitry connectors (12), grommet seals (14) provided on said electrical circuitry connectors (12), and a shield (18). The luminaire module (20) comprises a covering (24) and is arranged to be received in the luminaire holder (10). The shield (18) and the covering (24) are arranged to form a sealing arrangement between the luminaire holder (10) and the luminaire module (20), when the luminaire module (20) is received in the luminaire holder (10).

Abstract: An illuminated vehicle signaling glazing unit, including: a first transparent sheet made of mineral glass including a first main face configured to be directed toward outside the vehicle, a second main face configured to be directed toward inside the vehicle, and an edge face; one or more light sources, or light-emitting diodes, each including a light-emission face opposite the edge face, light emitted by the light sources being guided into the first sheet between the first and the second main faces thereof; a mechanism extracting light in at least one region of the first or second main faces of the first sheet or within a thickness of the first sheet; and an opaque layer formed from ink or from enamel, situated toward the inside of the vehicle with respect to the extraction mechanism and totally masking the extraction mechanism of the light to render it invisible from inside the vehicle.

Abstract: A luminous glazing unit for a vehicle, includes a first pane of mineral or organic glass having a first main face, a second main face and a side face, a diode support, diodes facing an edge of the second face of the first pane, referred to as the injection face, a device for extracting the guided light, a cap covering the diodes, which is leaktight against one or more fluids, in particular liquid water or water vapor, the cap is facial, facing the second face, and is associated with an interfacial element for interfacial sealing against the one or more fluids, and/or the diode support at least is provided with at least one moisture protection layer and/or an encapsulation such as a varnish of the silicone, epoxy or acrylic type.

Abstract: An illuminated emblem assembly is provided that includes a power source, a backing member, and a light-producing assembly coupled to the power source and supported by the backing member. The light-producing assembly includes a plurality of light-emitting diode sources. The light-producing assembly may also include a plurality of micro-sized, dispersed light-emitting diode sources. The illuminated emblem assembly further includes a translucent base region over the light sources, a chromatic layer over the translucent base region and a UV-stable translucent sealing structure over the chromatic layer that seals the backing member, the light producing assembly, and the chromatic layer. The sealing structure may be UV-stable and/or include a design feature. The illuminated emblem assembly exhibits a chrome- or mirror-like finish when viewed under ambient lighting conditions. Further, the illuminated emblem assembly possesses a glowing appearance when activated under low light or nighttime conditions.

Abstract: A vehicular lamp including at least three or more optical systems (10 to 50) that form respective illumination areas (15 to 55) in front of the lamp, thus forming a light distribution pattern in front of the lamp with the bombined illumination areas (15 to 55). The optical axes of the optical systems (10 to 50) are offset from one another in a horizontal direction in the order from the optical system (10) provided at the uppermost position to the optical system (50) provided at the lowermost position such that the illumination area (15) formed by the optical system (10) at the uppermost position is located at one end of the light distribution pattern in the horizontal direction, and the illumination area (55) formed by the optical system (50) at the lowermost position is located at the other end of the light distribution pattern in the horizontal direction.

Abstract: A vehicular lamp includes a light source, a cooling fan configured to cool the light source, a light source power supply module configured to drive the light source for emission of light, and a control module configured to execute an abnormal rotation detection of the cooling fan and to control the light source power supply module so that the quantity of light emitted from the light source is reduced in response to a detection of abnormal rotation.

Abstract: A linear light source emits light beams for illuminating a target. The linear light source includes a light guide, and a light-emitting unit. The light guide has a bottom surface, first and second reflecting surfaces extending from opposite side edges of the bottom surface, and a light converging convex surface extending between the first and second reflecting surfaces, curved outward, and having multiple radii of curvature. The light-emitting unit emits light beams that exit through the light converging convex surface to converge at multiple points distributed at distinct positions in a direction perpendicular to a surface of the target, such that the target to be disposed within a range defined by the multiple points is evenly illuminated.

Abstract: A mounting device (26) for a sanitary element comprises a mounting frame (30) to hold the sanitary element and a lighting unit (B) connected to the mounting frame, which comprises a first optical means (1) having at least one light source (3) for providing a first glow of light (5) and at least one second optical means (2) having at least one light source (4) for providing a second glow of light (6), wherein the said glows of light (5, 6) can be output from the mounting device (26).

Abstract: A LED candle lamp by controlling the coil to generate a magnetic attractive force to attract the magnet set, the translucent flame-shaped blade is vibrated when the emitted light of the LED lamp is guided by the light guide tube toward the blame-shaped blade body of the translucent flame-shaped blade, causing flame lighting effects. Subject to the arrangement that two magnets of a magnet set are bonded together by an adhesive with the same magnet poles thereof abutted against each other, magnetic field lines can be compressed into a dish, enhancing the effects of magnetic attraction and oscillation of a translucent flame-shaped blade.

Abstract: There is disclosed mount arrangement for supporting a tapered light pipe (5) of a type having a relatively wide end (8), a relatively narrow end (7), and an outer surface (9). The mount arrangement includes: a support assembly (25) provided within a housing (13) and having a central bore (28) for receipt of a said light pipe (5) through the support assembly (25), the support assembly (25) being arranged for movement within the housing (13) along the axis of the bore (28), and having within said central bore (28) an array of inwardly directed convex bearing surfaces (33) arranged in spaced relation to one another around the central bore (28). The support assembly (25) is biased towards the relatively wide end (8) of the light pipe (5) so as to urge the convex bearing surfaces (33) into contact with the outer surface (9) of the light pipe (5).

Abstract: A light plate assembly having minimal light leakage and uniform luminosity. The light plate assembly has a housing, a trough within the housing and a cover. The cover has a transparent window with an opaque side edge that prevents undesired light leakage between an outer surface of the transparent window and a base frame of the cover. The transparent window also has a length and a width, and a length-to-width ratio of greater than 10:1. In addition, luminosity variation along a length of the transparent window is less than 20%, and in some instances less than 10%.

Abstract: A reflector, a light source module, and a display device are disclosed. The reflector includes a substrate and slant reflecting surfaces disposed on the substrate and arranged from a first side to an opposite second side of the reflector. Each slant reflecting surface has an arc-shaped orthogonal projection on the substrate and is not parallel to the substrate. The light source module includes a light guide plate, a light emitting device, and the reflector, and the display device further includes a display panel. The light guide plate has a first surface, at least one opposite second surface, and a light incident surface connecting therebetween. The reflector is disposed at one side of the second surface. The slant reflecting surfaces are parallel to the second surface but not parallel to the first surface. The reflector offers improved luminous efficiency, and the light source module and the display device offer improved brightness.

Abstract: A lighting module includes: a case having a main base a first and a second extension parts extending from both sides of the main base in perpendicular direction to the surface of the main base, and a first and a second auxiliary bases extending from the first and the second extension parts respectively toward the center of the main base; a substrate seated in a cavity formed by structurally connecting the main base, the first and the second extension parts and the first and the second auxiliary bases; a plurality of light emitting devices disposed on one side of the substrate in the longitudinal direction of the substrate; and a driving driver disposed on the other side of the substrate, wherein at least one of the first and the second extension parts has an opening such that the driving driver is inserted into the first and the second extension parts.

Abstract: A spread illumination apparatus includes: a light source; and a light guide plate having a light entrance surface on which the light source is disposed, and a light exit surface through which light introduced from the light entrance surface is emitted, wherein the light guide plate includes a light entrance wedge portion which has an inclined surface and of which thickness is thinner from the light entrance surface side toward the light exit surface side, the inclined surface includes a first, a second, and a third inclined surface portions, and an average inclination angle of the second inclined surface portion at an arbitrary cross section perpendicular to the light entrance surface and the light exit surface along the light entrance surface in a longitudinal direction is configured to be larger than average inclination angles of the first inclined surface portion and the third inclined surface portion.

Abstract: A display device includes: a first chassis including a bottom surface, and a side wall which extends from an edge of the bottom surface; a light guide plate in the first chassis; a first fixing member which overlaps the side wall of the first chassis and contacts an upper surface of the light guide plate; and a first fastening member which fastens the first fixing member to the side wall of the first chassis. The first chassis includes a groove which extends through the side wall of the first chassis, the light guide plate includes a first protrusion which protrudes from an edge of the light guide plate and extends into the groove, and the first fixing member contacts an upper surface of the first protrusion of the light guide plate.

Abstract: A reactor of the present invention includes a coil 2, a magnetic core 3 in which the coil 2 is disposed, and a case that stores a combined product 10 made up of the coil 2 and the magnetic core 3. The case includes a bottom plate portion 40 made of a metal material, and a sidewall portion that is attached to the bottom plate portion 40 to surround the combined product 10. A joining layer 42 that fixes the coil 2 is provided at the inner face of the bottom plate portion 40. The region provided with the joining layer 42 has been subjected to surface roughening treatment. When anodic oxidation treatment is carried out as the surface roughening treatment, the bottom plate portion 40 includes an anodic oxide layer 43. The surface roughening treatment increases the contact area between the bottom plate portion 40 and the joining layer 42, whereby the joining strength between the bottom plate portion 40 and the coil 2 can be enhanced.

Abstract: An isolated boost power converter comprises a magnetically permeable multi-legged core (102) comprising first and second outer legs (132; 136) and a center leg (134) having an air gap (138) arranged therein. A boost inductor (Lboost) is wound around the center leg (134) or the first and second outer legs (132; 136) of the magnetically permeable multi-legged core (102). The boost inductor (Lboost) is electrically coupled between an input terminal (104) of the boost converter and a transistor driver (106) to be alternatingly charged and discharged with magnetic energy. A first and second series connected secondary transformer windings (SW1; SW2) with a center-tap (116) arranged in-between are wound around the first and second outer legs (132; 136), respectively, of the magnetically permeable multi-legged core (102).

Abstract: A load driver includes: a rectifying unit configured to rectify an AC voltage from a power source to generate a first voltage; a first converter configured to convert the first voltage outputted from the rectifying unit into a second voltage; a second converter configured to drive a load with a constant current, based on the second voltage converted by the first converter; and a feedback unit configured to generate feedback information, based on information obtained from the second converter and indicating an output voltage when the second converter drives the load with the constant current, wherein the first converter converts the first voltage into the second voltage having a magnitude based on the feedback information obtained from the feedback unit.

Abstract: System and method for regulating a power conversion system. An example system controller includes a signal processing component and a driving component. The signal processing component is configured to receive a feedback signal associated with an output signal of a power conversion system and generate a processed signal based on at least information associated with the feedback signal. The driving component is configured to generate a drive signal based on at least information associated with the processed signal and output the drive signal to a switch in order to affect a primary current flowing through a primary winding, the drive signal being associated with a demagnetization period corresponding to a demagnetization process of the power conversion system. The signal processing component is further configured to, sample and hold the feedback signal a plurality of times during the demagnetization period to generate a plurality of sampled and held signals.

Abstract: The invention relates to a control device (1) employed in a switched electrical power supply system to control a DC/DC converter of said switched electrical power supply system, said control device comprising a first input terminal (A) and a second input terminal (B), a first transistor (T1) connected via its source to the second input terminal (B) and a second transistor (T2) furnished with a gate (G) and connected via its drain (D) to the first input terminal (A), and via its source (S) to the first transistor (T1), the control device comprising a control assembly connected to the gate (G) of the second transistor (T2) and to the second input terminal (B) and comprising a capacitor (Ca) and a first Zener diode (Dz1) connected in series to said capacitor (Ca) and a second Zener diode (Dz2) connected between the gate (G) and the source (S) of the second transistor (T2).

Abstract: Exemplary embodiments are directed to methods and systems for producing a three-phase current to a three-phase output. Switching converters are used to generate a positive current, a negative current, and an intermediate current. The system is configured such that the produced positive current follows a path of a highest phase of a sinusoidal three-phase signal at a given time, the produced negative current follows a path of a lowest phase of the three-phase signal at the given time, and the produced intermediate current follows a path of a phase of the three-phase signal between the highest and the lowest phase at the given time. The produced currents are switched to each phase conductor of the three-phase output in sequence so that phase currents of the three-phase current are formed in the output conductors.

Abstract: An input circuit connected to a semiconductor circuit is configured to receive a voltage indicating an on/off operation state of a power supply and to output a voltage that is lower than a breakdown voltage of the semiconductor circuit. The input circuit includes a first nMOS transistor and a resistor element. The first nMOS transistor has a drain receiving an outside voltage, a gate receiving a bias voltage higher than a power supply voltage inputted to a semiconductor circuit, and a source connected to the semiconductor circuit. The first nMOS transistor has a breakdown voltage higher than the power supply voltage inputted to the semiconductor circuit. One end of the resistor element connects with the source of the first nMOS transistor, while the other end connects with a reference potential of the semiconductor circuit.

Abstract: A switching power supply comprises one or more power supply stages configured to receive power from an input power source and to generate an output voltage for powering a load by alternately opening and closing a set of switches. An output current sensor is configured to monitor a level of an output current of the switching power supply. The opening and closing of the set of switches is controlled so as to maintain the output voltage at a desired level when the level of the output current is below the threshold and so as to limit the output current when the level of the output current exceeds the threshold.

Abstract: Multi-level rectifiers are provided. A multi-level rectifier may convert a medium AC voltage to a medium DC voltage. A multi-level rectifier may comprise an input inductor, a set of diodes, a set of switches, and a DC link comprising a set of capacitors. One end of the input inductor is coupled to the input AC voltage and the other end of the input inductor is coupled to a pair of diodes that are series connected. The set of switches may be regulated such that the inductor may be coupled to a DC voltage point of the DC link. A multi-level rectifier may operate under a set of operation modes. Each operation mode may be determined from the input voltage and the inductor current. Accordingly, a sinusoidal voltage at the fundamental frequency of the input voltage may be synthesized by selectively switching between adjacent operation modes of the set of operation modes.

Abstract: A rectifier assembly and method are provided. The rectifier assembly includes an annular bus bar including an electrically conductive material, and an insulator ring receiving the annular bus bar. The insulator ring defines radially-extending resistor pockets and diode pockets therein. The rectifier assembly also includes resistors disposed in the resistor pockets and electrically connected with the annular bus bar, and diodes disposed in the diode pockets and electrically connected with the annular bus bar. The rectifier assembly also includes an outer housing receiving the annular bus bar and the insulator ring, such that the insulator ring is positioned radially between the annular bus bar and the outer housing.

Abstract: An inverter control circuit has a quantizer configured to generate a switching signal which changes over switches of a main circuit converting a DC voltage into an AC voltage, and a filter circuit configured to generate a signal having specific transfer characteristic by using a signal correlated with an output voltage of an LC filter which smooths the AC voltage and an instruction signal corresponding to a target value of an output voltage of the main circuit, wherein the quantizer generates the switching signal by quantizing an output signal of the filter circuit.

Abstract: Memory die, stacks of memory dies, memory devices and methods, such as those to construct and operate such die, stacks and/or memory devices are provided. One such memory die includes an identification configured to be selectively coupled to an external select connection node depending on how the die is arranged in a stack. The identification circuit can determine an identification of its respective memory die responsive to how, if coupled, the identification circuit is coupled to the external select connection node.

Abstract: Under one aspect, a covered nanotube switch includes: (a) a nanotube element including an unaligned plurality of nanotubes, the nanotube element having a top surface, a bottom surface, and side surfaces; (b) first and second terminals in contact with the nanotube element, wherein the first terminal is disposed on and substantially covers the entire top surface of the nanotube element, and wherein the second terminal contacts at least a portion of the bottom surface of the nanotube element; and (c) control circuitry capable of applying electrical stimulus to the first and second terminals. The nanotube element can switch between a plurality of electronic states in response to a corresponding plurality of electrical stimuli applied by the control circuitry to the first and second terminals. For each different electronic state, the nanotube element provides an electrical pathway of different resistance between the first and second terminals.

Abstract: Disclosed is a semiconductor memory device that includes a plurality of channel memories mounted within a package and is capable of minimizing or reducing the number of through-silicon vias. With the semiconductor memory device, a row command or a row address on two or more channels is applied through a shared bus. The semiconductor memory device is capable of reducing an overhead of a die size by reducing the number of through-silicon vias. A method of driving a multi-channel semiconductor memory device including a plurality of memories, using a shared bus, is also provided.

Abstract: The present invention is generally directed to a DRAM cell design with folded digitline sense amplifier. In one illustrative embodiment, a memory array having a plurality of memory cells having an effective size of 6F2 is disclosed which has a plurality of dual bit active areas, each of the active areas having a substantially longitudinal axis, and a plurality of digitlines arranged in a folded digitline architecture, wherein the active areas are positioned such that the longitudinal axis of the active areas is oriented at an angle with respect to a centerline of the digitlines.

Abstract: Apparatuses and methods for interconnections for 3D memory are provided. One example apparatus can include a stack of materials including a plurality of pairs of materials, each pair of materials including a conductive line formed over an insulation material. The stack of materials has a stair step structure formed at one edge extending in a first direction. Each stair step includes one of the pairs of materials. A first interconnection is coupled to the conductive line of a stair step, the first interconnection extending in a second direction substantially perpendicular to a first surface of the stair step.

Abstract: A static random access memory unit cell layout structure is disclosed, in which a slot contact is disposed on one active area and another one across from the one. A static random access memory unit cell structure and a method of fabricating the same are also disclosed, in which, a slot contact is disposed on drains of a pull-up transistor and a pull-down transistor, and a metal-zero interconnect is disposed on the slot contact and a gate line of another pull-up transistor. Accordingly, there is not an intersection of vertical and horizontal metal-zero interconnects, and there is no place suffering from twice etching. Leakage junction due to stitch recess can be avoided.

Abstract: A read-only memory (ROM) cell has first and second transistors connected in series between a true bit line and a voltage reference (e.g., ground), and third and fourth transistors connected in series between a complement bit line and the voltage reference. The gates of the first and third transistors are connected to a first word line, and the gates of the second and fourth transistors are connected to a second word line. The ROM cell is programmed to store any possible combination of two bits of information by appropriately (i) connecting the node between the first and second transistors to either the true bit line, the complement bit line, or the voltage reference and (ii) connecting the node between the third and fourth transistors to either the true bit line, the complement bit line, or the voltage reference.

Abstract: A memory cell array comprises first wiring lines, second wiring lines, and memory cells disposed at intersections thereof. A control circuit comprises a first power-supply line supplying a first voltage to selected ones of the first or second wiring lines, and first selection circuits connected between the first or second wiring lines and the first power-supply line, each first selection circuit comprising first and second transistors connected in series. The first selection circuits arranged along a first direction are connected to a first selection line. The first selection circuits arranged along a second direction perpendicular to the first direction are commonly connected to a second selection line. The first and second transistors each comprise a columnar semiconductor portion extending in a direction perpendicular to a semiconductor substrate, a gate-insulating film in contact with a side surface of the columnar semiconductor, and a gate electrode in contact with the gate-insulating film.

Abstract: A shift register according to an embodiment includes: a magnetic nanowire; a first control electrode group and a second control electrode group arranged with the magnetic nanowire being sandwiched therebetween, the first control electrode group including a plurality of first control electrodes arranged to be spaced apart from each other along a direction in which the magnetic nanowire extends, the second control electrode group including a plurality of second control electrodes arranged to be spaced apart from each other to correspond to the plurality of first control electrodes along the direction in which the magnetic nanowire extends, and the second control electrodes corresponding to the first control electrodes being shifted in the direction in which the magnetic nanowire extends; a first driving unit for driving the first control electrode group; and a second driving unit for driving the second control electrode group.

Abstract: In some aspects, a memory cell is provided that includes a steering element and a memory element. The memory element includes a first conductive material layer, a first dielectric material layer disposed above the first conductive material layer, a second conductive material layer disposed above the first dielectric material layer, a second dielectric material layer disposed above the second conductive material layer, and a third conductive material layer disposed above the second dielectric material layer. One or both of the first conductive material layer and the second conductive material layer comprise a stack of a metal material layer and a highly doped semiconductor material layer. Numerous other aspects are provided.

Abstract: Two or more workload indicators affecting a memory cell of a resistance-based, non-volatile memory are measured. The two or more workload indicators are applied to a transfer function that predicts a resistance shift and/or resistance noise variance in response to the two or more workload indicators. A result of the transfer function is applied to shift and/or determine a threshold resistance used for at least one of a program operation and a read operation affecting the memory cell. An error rate of the memory cell is reduced as a result.

Abstract: Various embodiments may generally be directed to a variable resistance data storage device and a method of managing the device. A data storage device may have at least a controller configured to re-characterize at least one variable resistance memory cell in response to an identified variance from a predetermined resistance threshold.

Abstract: The present disclosure provides one embodiment of a method for operating a resistive random access memory (RRAM) cell. The method includes performing a forming operation to the RRAM cell with a forming voltage; performing a number of set/reset operation cycles to the RRAM cell; and performing a recreating process to the RRAM cell to recover RRAM resistance by applying a recreating voltage. Each of the number of set/reset operation cycles includes a set operation with a set voltage. The recreating voltage is greater than the set voltage.

Abstract: FORMING reversible resistivity-switching elements is described herein. The FORMING voltage may be halted if the current through the memory cell reaches some reference current. The reference current may depend on how many groups of memory cells have been FORMED. This can help to increase the accuracy of determining when to halt the FORMING voltage. After the FORMING voltage is applied, a RESET voltage may be applied to those memory cells that have a resistance that is lower than a reference resistance to raise the resistance of those memory cells. By raising the resistance, the leakage current of these memory cells when other groups are programmed may be less. This, in turn, helps to prevent FORMING of the other groups from slowing down. A reason why this helps to prevent the slowdown is that the FORMING voltage may be kept near a desired level.

Abstract: A memory system according to the embodiment comprises a cell array of unit cell arrays each including memory cells; and an access circuit, wherein the memory cell changes from a first resistance state to a second resistance state on application of a first polarity voltage, and changes from the second resistance state to the first resistance state on application of a second polarity voltage, the access circuit provides the first and second lines connected to an access-targeted memory cell with access potentials, and brings at least one of the first and second lines connected to an access-untargeted memory cell into a floating state to make access to the access-targeted memory cell, the unit cell array includes first spare lines to provide redundancy for the first lines, and an alignment of the first lines includes a certain number of the first spare lines arranged in a certain cycle.

Abstract: A memory cell array includes first wiring lines, and second wiring lines, the first and second wiring lines intersecting, and memory cells disposed in the intersections of the first and second wiring lines, the memory cells including a variable resistance element. A control circuit controls voltages of selected first and second wiring lines. The first wiring lines are arranged at a first pitch in a first direction perpendicular to a substrate and extend in a second direction parallel to the substrate. The second wiring lines are arranged at a second pitch in the second direction and extend in the first direction. The control circuit is configured to change voltages applied to a selected first wiring line according to the positions of the selected first wiring lines in the first direction.

Abstract: A memory cell is included which has a selection transistor and a variable resistance device connected to a bit line through the selection transistor. The variable resistance device includes a first electrode which has a first metal material and is connected to the selection transistor, a second electrode which has a second metal material different from the first metal material, and an insulating film which is provided between the first electrode and the second electrode, has a third metal material different from the first metal material and the second metal material, and has oxygen. The second metal material has a greater normalized oxide formation energy than the first metal material.

Abstract: An electronic device including a semiconductor memory. The semiconductor memory includes a plurality of variable resistance elements; a plurality of read voltage application terminals configured to supply different levels of read voltages to respective one ends of the plurality of variable resistance elements; and an analog-to-digital conversion unit configured to generate multi-bit digital data corresponding to a total current which is acquired by summing currents flowing through the plurality of variable resistance elements.

Abstract: An electronic device comprising a semiconductor memory unit that may include a variable resistance element configured to be changed in a resistance value thereof in response to current flowing through both ends thereof, a toggle data generation unit configured to generate toggle data of which logic value toggles with a predetermined cycle, in a first mode for testing reliability of the variable resistance element, a data transfer line configured to transfer data inputted from an outside, and a driving unit configured to flow current which is changed in its direction with the predetermined cycle, through the variable resistance element in response to the toggle data in the first mode, and flow current through the variable resistance element in a direction determined in response to the data of the data transfer line, in a second mode in writing date into or reading data from the variable resistance element.

Abstract: A reference column of a semiconductor memory includes a reference bit line; a reference source line; and first to Nth resistive memory cells disposed between the reference bit line and the reference source line. Data of a first state is stored in the first resistive memory cell and data of a second state is stored in the Nth resistive memory cell before a read operation, and the first and Nth resistive memory cells form current paths between the reference bit line and the reference source line in the read operation.

Abstract: An electronic device including a semiconductor memory. The semiconductor memory includes a cell array divided into at least two regions each of which includes a plurality of memory cells each including a transistor and a resistance variable element; a write driver circuit configured to supply write current to a memory cell selected among memory cells in the cell array; and a back bias voltage supply unit configured to supply back bias voltages with different levels to the regions in the cell array.

Abstract: An electronic device comprising a semiconductor memory unit that may include a plurality of data transfer lines; a plurality of columns including a plurality of memory cells; at least one redundancy column including a plurality of redundancy memory cells and configured to replace at least one column among the plurality of columns; a repair select information generation unit configured to store a column address of the at least one column to be replaced among the plurality of columns and generate a plurality of repair select information in response to the stored column address; and a plurality of repair selection units connected with data transfer lines corresponding to them among the plurality of data transfer lines, columns corresponding to them among the plurality of columns and the at least one redundancy column, and each configured to electrically connect a column selected among a column corresponding to it and the at least one redundancy column, to a data transfer line corresponding to it, in response to

Abstract: A switching device has a bottom conductor, a top conductor, and a device body formed between the top and bottom conductors. The device body has a switching layer that is switchable by means of current passed through the device body and between the top and bottom conductors. A lower via connects the bottom conductor to the device body. The width of the lower via is smaller than a width of the device body.

Abstract: A semi-conductor storing apparatus is provided, which comprises plural storing units, each having a line buffer including plural flip-flop circuits and a clock supplying circuit for supplying a clock to the plural flip-flop circuits, a clock-controlling unit, which controls on/off operation of the clock supplying circuit to decide whether to output a clock, a selecting unit, which selects one from among outputs from the plural storing units, and an unit-controlling unit, which controls the operations of the clock-controlling unit and the selecting unit.