Abstract: A semiconductor device of an embodiment includes a p-type SiC impurity region containing a p-type impurity and an n-type impurity. Where the p-type impurity is an element A and the n-type impurity is an element D, the element A and the element D form a combination of Al (aluminum), Ga (gallium), or In (indium) and N (nitrogen), and/or a combination of B (boron) and P (phosphorus). The ratio of the concentration of the element D to the concentration of the element A in the above combination is higher than 0.33 but lower than 0.995, and the concentration of the element A forming part of the above combination is not lower than 1×1018 cm?3 and not higher than 1×1022 cm?3.

Abstract: A semiconductor device of an embodiment includes, an n-type SiC substrate that has first and second faces, and contains a p-type impurity and an n-type impurity, the p-type impurity being an element A, the n-type impurity being an element D, the element A and the element D being a combination of Al (aluminum), Ga (gallium), or In (indium) and N (nitrogen), and/or a combination of B (boron) and P (phosphorus), the ratio of the concentration of the element A to the concentration of the element D in the combination(s) being higher than 0.40 but lower than 0.95, the concentration of the element D forming the combination(s) being not lower than 1×1018 cm?3 and not higher than 1×1022 cm?3, an SiC layer formed on the first face, a first electrode formed on the first face side, and a second electrode formed on the second face.

Abstract: A semiconductor component includes a semiconductor body having a top side and a bottom side opposite the top side. A top metallization is applied to the top side and a bottom metallization is applied to the bottom side. A moisture barrier completely seals the semiconductor body in cooperation with the top metallization and the bottom metallization.

Abstract: A manufacturing method of a junction field effect transistor includes the steps of: (a) forming an n+-type source layer on a surface of an n?-type drift layer formed on an n+-type SiC substrate; (b) forming a plurality of shallow trenches disposed at predetermined intervals by etching the surface of the n?-type drift layer with a silicon oxide film formed on the n?-type drift layer used as a mask; (c) forming an n-type counter dope layer by doping the n?-type drift layer below each of the shallow trenches with nitrogen by using a vertical ion implantation method; (d) forming a sidewall spacer on each sidewall of the silicon oxide film and the shallow trenches; and (e) forming a p-type gate layer by doping the n?-type drift layer below each of shallow trenches with aluminum by using the vertical ion implantation method.

Abstract: A device is provided. The device includes a transistor formed on a semiconductor substrate, the transistor having a conduction channel. The device includes at least one edge dislocation formed adjacent to the conduction channel on the semiconductor substrate. The device also includes at least one free surface introduced above the conduction channel and the at least one edge dislocation.

Abstract: Disclosed is a method of manufacturing a thin film, the method including: growing an epitaxial layer on a surface of a wafer at a growth temperature, wherein the growing of the epitaxial layer comprises controlling a defect present on a surface of the wafer. Also, disclosed is a wafer including: a substrate; and an epitaxial layer located on the substrate, wherein a basal dislocation density of the epitaxial layer is equal to or less than 1/cm2.

Abstract: Disclosed is a method of manufacturing a thin film, the method including: growing an epitaxial layer on a surface of a wafer at a growth pressure, wherein the growing of the epitaxial layer comprises controlling a defect present on a surface of the wafer. Also, disclosed is a wafer including: a substrate; and a buffer layer and an epitaxial layer located on the substrate, wherein a surface dislocation density of the epitaxial layer is equal to or less than 1/cm2.

Abstract: According to one embodiment, a photocoupler includes a light emitting element, a light receiving element, a bonding layer, input terminals, output terminals and a molded resin body. A light emitting element includes a transparent support substrate, a semiconductor stacked body, and first and second electrodes. A light receiving element includes a light reception surface, a first electrode, and a second electrode. A bonding layer is configured to bond the first surface of the support substrate to the light reception surface side of the light receiving element. The bonding layer is transparent and insulative. Input terminals are connected to the first and second electrodes of the light emitting element. Output terminals are connected to the first and second electrodes of the light receiving element. The light reception surface is included in the light emitting surface. An input electrical signal is converted into an output electrical signal.

Abstract: According to one embodiment, an optical coupling device includes a light emitting element configured to convert an electric signal into an optical signal, a photo transistor circuit configured to convert the optical signal into a current, the photo transistor circuit including a first transistor having a collector connected to a power source and an emitter through which the current is output, and a current mirror circuit including a second transistor having a collector connected to the emitter of the first transistor, a base connected to the emitter of the first transistor, and an emitter connected to a ground, and a third transistor having a collector connected to an output terminal, a base connected to the base of the second transistor, and a emitter connected to the ground.

Abstract: Devices incorporating a single to a few-layer MoS2 channels in combination with optimized substrate, dielectric, contact and electrode materials and configurations thereof, exhibit light emission, photoelectric effect, and superconductivity, respectively.

Abstract: A display device having a MEMS transmissive light valve and a method for forming the same are provided. The method includes: providing a multilayer semiconductor substrate comprising a bottom semiconductor layer, a middle buried layer and a top semiconductor layer; forming a light guide opening in the top semiconductor layer; forming at least one MOS device in a remaining part of the top semiconductor layer; forming an interconnection layer and an interlayer dielectric layer on the at least one MOS; forming a MEMS transmissive light valve, which is electrically connected to the interconnection layer, on the light guide opening, where the MEMS transmissive light valve is surrounded by the interlayer dielectric layer; forming a transparent backplane on a top surface of the interlayer dielectric layer; and removing the bottom semiconductor layer.

Abstract: The present invention provides a stacked LED array structure, comprising a substrate and a plurality of LED dies stacked on the substrate in turn. Each LED die comprises a first semiconductor layer and a second semiconductor layer. The first semiconductor layer is provided thereon with a first electrode and stacked with the second semiconductor layer, while the second semiconductor layer is provided thereon with a second electrode and stacked with the first semiconductor layer of another LED die. The second electrode of each LED die is connected to the first electrode of another LED die in series via a metal layer to from an LED array. A plurality of LED dies may be stacked to be an LED array in a stacked manner, resulting in not only easy manufacturing, but also an effectively reduced volume for arranging the whole LED array.

Abstract: A light-emission element assembly includes: a light-emission element; a mold section in which the light-emission element is molded; a pad section protruding from an undersurface of the mold section, and electrically connected to the light-emission element; and a reinforcement section provided in the pad section, and projecting towards a side on which the mold section is provided.

Abstract: An integrated circuit including a die of the integrated circuit, the die including an insulating layer, light emitting diodes, a semiconductor layer, and a control module. The insulating layer includes a first side and a second side. The second side is opposite to the first side. The light emitting diodes are arranged on the first side of the insulating layer. The semiconductor layer is arranged adjacent to the second side of the insulating layer. The light emitting diodes are connected to the semiconductor layer using connections from the first side of the insulating layer to the second side of the insulating layer. The control module is arranged on the semiconductor layer. The control module is configured to output pulse width modulated pulses to the light emitting diodes via the connections.

Abstract: The present invention provides a white light source comprising: a light emitting diode (LED) having a light emission peak wavelength in a range of 350 or more and 420 nm or less; and a phosphor layer including four or more types of phosphors and resin, wherein the white light source satisfies a relational equation of: ?0.2?[(P(?)×V(?))/(P(?max1)×V(?max1))?(B(?)×V(?))/(B(?max2)×V(?max2))]?+0.2, assuming that: a light emission spectrum of the white light source is P(?); a light emission spectrum of black-body radiation having a same color temperature as that of the white light source is B(?); a spectrum of a spectral luminous efficiency is V(?); a wavelength at which P(?)×V(?) becomes largest is ?max1; and a wavelength at which B(?)×V(?) becomes largest is ?max2, and wherein an amount (difference) of chromaticity change on CIE chromaticity diagram from a time of initial lighting up of the white light source to a time after the white light source is continuously lighted up for 6000 hours is less than 0.010.

Abstract: According to one embodiment, a method for manufacturing a semiconductor light emitting device includes performing plasma processing of a stacked body. The stacked body has a first semiconductor layer and a second semiconductor layer provided on the first semiconductor layer. The plasma processing is performed on a surface of the stacked body where the second semiconductor layer is exposed such that the second semiconductor layer remains. The first semiconductor layer includes gallium and nitrogen. The second semiconductor layer includes aluminum and nitrogen. The method includes forming a plurality of protrusions by performing wet etching of the surface after the plasma processing is performed. At least a lower portion of the plurality of protrusions is made of the first semiconductor layer.

Abstract: A nitride semiconductor light emitting device includes a laminate, first and second electrodes, a conductive layer, and a phosphor layer. The laminate includes a first layer including a first electroconductive-type layer, a second layer including a second electroconductive-type layer, a light emitting layer between the first and second layers, and a nitride semiconductor. The laminate has a recessed portion extending from the first layer to the second layer in a central portion or an outer peripheral portion. The first electrode arranged on the first layer reflects light emitted from the light emitting layer. The second electrode is surrounded by the light emitting layer or on the periphery thereof and connected to a bottom surface of the recessed portion. The conductive layer is arranged on a surface of the second layer at a side opposite to the light emitting layer. The phosphor layer overlies the second layer and the conductive layer.

Abstract: A light emitting diode (LED) package includes a substrate, a first electrode and a second electrode embedded in the substrate and spaced from each other, an LED die mounted on a top surface of the substrate and electrically connected to the first and the second electrodes. Both the first and the second electrodes include a top face and a bottom face, with the top face and the bottom face of each of the first and the second electrodes being exposed at the top surface and a bottom surface of the substrate, respectively. The top face of the first electrode defines a first groove corresponding to a positive bonding pad (p-pad) of the LED die. The p-pad is partially inserted into the first groove. An oxidation-resistant metal coating layer is filled between an insertion portion of the p-pad and an inner surface of the first groove.

Abstract: A light emitting diode (LED) package includes a substrate, a first electrode, a second electrode, an LED die mounted on the substrate and electrically connected to the first and the second electrodes, and an encapsulation layer encapsulating the LED die. Both the first and the second electrodes are embedded in the substrate and spaced from each other. Each of the first and the second electrodes includes a top face and a bottom face, with the top face and the bottom face thereof being exposed at a top surface and a bottom surface of the substrate, respectively. The top face of the first electrode defines a first groove therein. An oxidation-resistant metal coating layer is filled in the first groove. A positive bonding pad of the LED die directly contacts with a top face of the first oxidation-resistant metal coating layer.

Abstract: A method of manufacturing LED packages includes the steps of: forming a conductive circuit layer on a substrate; screen printing a wall layer on the conductive circuit layer to form a trellis with a plurality of wall units, so that regions of the conductive circuit layer surrounded by the wall units are exposed; mounting and electrically connecting at least one LED die on the conductive circuit layer within each of the wall units; molding a transparent layer to cover the LED dies; and cutting along the wall units to form a plurality of LED packages.

Abstract: A light-emitting module which efficiently extracts light emitted from a light-emitting element is provided. Alternatively, a light-emitting module having lower power consumption or improved reliability is provided. A light-emitting module includes a window material having a light-transmitting property, a light-emitting element that emits light transmitted from a light-transmitting layer to the window material, and an optical bonding layer between the window material and the light-transmitting layer. The optical bonding layer includes a thick part overlapping the light-emitting element and a thin part surrounding the thick part. The light-transmitting layer, the optical bonding layer, and the window material are provided in decreasing order of refractive index.

Abstract: A light emitting die package is provided which includes a metal substrate having a first surface and a first conductive lead on the first surface. The first conductive lead is insulated from the substrate by an insulating film. The first conductive lead forms a mounting pad for mounting a light emitting device. The package includes a metal lead electrically connected to the first conductive lead and extending away from the first surface.

Abstract: The present invention is directed to reduction of angle dependence of chromaticity in a phosphor layer, without using a light scattering agent, the phosphor layer being made up of phosphor particles adhered tightly to one another via a binder according to the spray coating method. The phosphor layer contains phosphor particles laid along the top surface of the light emitting element and the binder embedded into a gap between the phosphor particles, and the phosphor layer does not contain the light scattering agent. The area of a region on the upper surface of the phosphor layer is between or equal to 3% and 10% with respect to the area of the top surface of the light emitting element, the region being positioned at the gap between the phosphor particles and allowing the light being outputted to pass through the binder and directly reach the upper surface of the phosphor layer.

Abstract: An optoelectronic semiconductor component includes an optoelectronic semiconductor chip having side areas covered by a shaped body, at least one plated-through hole including an electrically conductive material, and an electrically conductive connection electrically conductively connected to the semiconductor chip and the plated-through hole, wherein, the plated-through hole is arranged in a manner laterally spaced apart from the semiconductor chip, the plated-through hole completely penetrates through the shaped body, and the plated-through hole extends from a top side of the shaped body to an underside of the shaped body, the electrically conductive connection extends at the top side of the shaped body.

Abstract: A light generating device and a method of manufacturing the light generating device are disclosed. The light generating device includes a p-type semiconductor layer, an n-type semiconductor layer, an active layer, a p-type electrode and an n-type electrode. The active layer is disposed between the p-type semiconductor layer and the n-type semiconductor layer. The p-type electrode provides the p-type semiconductor layer with holes. The n-type electrode provides the n-type semiconductor layer with electrons. At least one of the p-type electrode and n-type electrode has a protrusion protruding toward p-type semiconductor layer and the n-type semiconductor layer, respectively. Therefore, light efficiency is enhanced.

Abstract: A semiconductor light emitting device has a light emitting element, a first electrode layer, a second electrode layer, a seed electrode layer and a plated layer. The light emitting element has a nitride-based III-V compound semiconductor on a substrate. The light emitting element having a light extraction surface. The first electrode layer on the light extraction surface. The second electrode layer is provided on a surface opposite to the light extraction surface of the light emitting element. The seed electrode layer is configured to cover the entire surface of the second electrode layer. The plated layer is provided on the seed electrode layer. The light emitting element has a light emitting layer, a first conductive type semiconductor layer, and a second conductive type semiconductor layer.

Abstract: A flexible film comprising a wavelength converting material is positioned over a light source. The flexible film is conformed to a predetermined shape. In some embodiments, the light source is a light emitting diode mounted on a support substrate. The diode is aligned with an indentation in a mold such that the flexible film is disposed between the support substrate and the mold. Transparent molding material is disposed between the support substrate and the mold. The support substrate and the mold are pressed together to cause the molding material to fill the indentation. The flexible film conforms to the shape of the light source or the mold.

Abstract: An optoelectronic component includes a layer sequence having an active region that emits primary electromagnetic radiation, wherein the primary electromagnetic radiation has a wavelength of 430 nm to 470 nm, a conversion material arranged in a beam path of the primary electromagnetic radiation and at least partly converts the primary electromagnetic radiation into a secondary electromagnetic radiation, wherein the conversion material includes a first phosphor having general composition A3B5O12, wherein A is a combination of Lu and Ce, and wherein B is a combination of Al and Ga.

Abstract: Disclosed are a light-emitting diode package and a method for manufacturing same. The method for manufacturing a light-emitting diode package comprises: preparing a package main body having a cavity and an air vent passageway which extends from the cavity; installing a light-emitting diode inside the cavity of the package main body; attaching a transparent member by means of an adhesive so as to cover the upper part of the cavity; and blocking the air vent passageway by forming a sealing member. As the air vent passageway is blocked after the transparent member is attached, the transparent member may be prevented from peeling off from the air pressure inside the cavity.

Abstract: A light-emitting device includes a thermally conductive substrate, a wiring electrode formed on the thermally conductive substrate, a resist formed on the wiring electrode except a terminal thereof, and a light-emitting element that is disposed in an element mounting region of the thermally conductive substrate and electrically connected to the terminal of the wiring electrode. A heat dissipation hole is formed in a region of the resist outside the element mounting region so as to expose a surface of the thermally conductive substrate.

Abstract: A method for manufacturing a light emitting device comprises a package preparation step of preparing a package having a recess in which a light emitting element is locatable, wherein the package includes a projection extending from an upper surface of the package, the projection at least partially surrounding the recess, a sealing resin forming step of filling said recess in which said light emitting element is located with a sealing resin, and providing said sealing resin higher than the height of said package, and a sealing resin cutting step of cutting the sealing resin such that an upper surface of the sealing resin is at a height that is substantially the same as a height of the upper surface of the package.

Abstract: A method of manufacturing a light generating device and a light generating device manufactured through the method are disclosed. The method of manufacturing a light generating device according to an exemplary embodiment of the present invention, includes preparing a semiconductor stacking structure including a p-type semiconductor layer, an n-type semiconductor layer and an active layer disposed between the p-type semiconductor layer and the n-type semiconductor layer; forming a metal thin film on the n-type semiconductor layer or on the p-type semiconductor layer; annealing the metal thin film to form a grain boundary at the metal thin film; applying liquid with graphite powder to the metal thin film with the grain boundary; thermally treating the semiconductor stacking structure to which the liquid with graphite power is applied; and removing the metal thin film with the grain boundary.

Abstract: According to one embodiment, a semiconductor light emitting device includes a semiconductor film, an electrode, a passivation film, a sealing resin body, and an intermediate film. The semiconductor film contains a Group III nitride semiconductor. The electrode is connected to a first surface of the semiconductor film. The passivation film covers an end surface of the semiconductor film and the first surface. The sealing resin body covers the first surface and a side surface of the electrode to leave a second surface of the semiconductor film exposed. The intermediate film is provided between the passivation film and the sealing resin body. The absolute value of the difference between an internal stress of the intermediate film and that of the sealing resin body is less than the absolute value of the difference between an internal stress of the passivation film and that of the sealing resin body.

Abstract: A semiconductor device of an embodiment is provided with a normally-off transistor having a first source connected to a source terminal, a first drain, and a first gate connected to a gate terminal and a normally-on transistor having a second source connected to the first drain, a second drain connected to a drain terminal, and a second gate connected to the source terminal. A withstand voltage between the first source and the first drain when the normally-off transistor is turned off is lower than a withstand voltage between the second source and the second gate of the normally-on transistor.

Abstract: An MOS semiconductor device including an MOS gate structure is disclosed. The MOS semiconductor device includes a p-type well region selectively disposed on the surface layer of an n-type drift layer formed on a semiconductor substrate forming an n-type drain region; an n-type source region selectively disposed on the surface layer of the p-type well region; and a gate electrode placed, via an insulating film, on the surface of a channel formation region on the surface layer of the p-type well region sandwiched between the n-type source region and the surface layer of the n-type drain region, wherein a surface in the channel formation region has a level difference formed in the direction of the peripheral length, and all over the length, of the channel formation region.

Abstract: A p anode layer (2) is formed on one main surface of an n? drift layer (1). An n+ cathode layer (3) having an impurity concentration more than that of the n? drift layer (1) is formed on the other main surface of the n? drift layer (1). An anode electrode (4) is formed on the surface of the p anode layer (2). A cathode electrode (5) is formed on the surface of the n+ cathode layer (3). An n-type broad buffer region (6) that has a net doping concentration more than the bulk impurity concentration of a wafer and less than that of the n+ cathode layer (3) and the p anode layer (2) is formed in the n? drift layer (1). The resistivity ?0 of the n? drift layer (1) satisfies 0.12V0??0?0.25V0 with respect to a rated voltage V0. The total amount of the net doping concentration of the broad buffer region (6) is equal to or more than 4.8×1011 atoms/cm2 and equal to or less than 1.0×1012 atoms/cm2.

Abstract: According to one embodiment, a semiconductor device includes a first and second electrode, a first, second, third and fourth semiconductor region, and a first intermediate metal film. The first region is provided above the first electrode and has a first impurity concentration. The second region is provided above the first region and has a second impurity concentration lower than the first impurity concentration. The third region is provided above the second region and has a third impurity concentration. The fourth region is provided above the second region and has a fourth impurity concentration lower than the third impurity concentration. The second electrode is provided above the third region and the fourth region and is in ohmic contact with the third region. The intermediate metal film is provided between the second electrode and the fourth region. The intermediate metal film forms Schottky junction with the fourth region.

Abstract: A transient voltage suppressor (TVS) device design compatible with normal IC wafer process is provided. Instead of a thick base that requires double-sided wafer processing, a much thinner base with a modulated doping profile is used. In this base, a high doping layer is sandwiched by two lower layers of the same or different doping. The base is then sandwiched by two electrodes having opposite doping relative to the base center layer. In the base, the two lower doping layers will determine the breakdown voltage. The middle layer is used to reduce the transistor gain and thus produce an acceptable snapback characteristic. The presence of the higher doped middle layer allows the total base width to be as low as 5 ?m for a breakdown voltage of about 30 V.

Abstract: A method for manufacturing a semiconductor wafer includes the steps of forming, on a first principal surface of a substrate, a compound semiconductor layer different in kind from the substrate, and removing, by etching, a part of the compound semiconductor layer. The part of the compound semiconductor layer is formed on an outer peripheral portion of the first principal surface of the substrate.

Abstract: A method for forming a semiconductor structure having a transistor device with a control electrode for controlling a flow of carriers between a first electrode and a second electrode. A passivation layer is deposited over the first electrode, the second electrode and the control electrode. An etch stop layer is deposited on the passivation layer over the control electrode. A dielectric layer is formed over the etch stop layer. A window is etched through a selected region in the dielectric layer over the control electrode, to expose a portion of the etch stop layer disposed over the control electrode. A metal layer is formed on a portion of the etch stop layer and the dielectric layer is also formed on the metal layer. A second metal layer is deposited on the portion of the dielectric layer formed on the first mentioned metal layer.

Abstract: A semiconductor device of an embodiment includes a normally-off transistor having a first source electrically connected to a source terminal, a first drain, and a first gate electrically connected to a gate terminal, a normally-on transistor having a second source electrically connected to the first drain, a second drain electrically connected to a drain terminal, and a second gate, a capacitor having one end electrically connected to the gate terminal and the other end electrically connected to the second gate; and a first diode having a first anode electrically connected to the capacitor and the second gate and a first cathode electrically connected to the first source.

Abstract: Embodiments related to a method of manufacturing of an imager and an imager device are shown and depicted.

Abstract: Image sensors are provided. The image sensors may include first and second stacked impurity regions having different conductivity types. The image sensors may also include a floating diffusion region in the first impurity region. The image sensors may further include a transfer gate electrode surrounding the floating diffusion region in the first impurity region. Also, the transfer gate electrode and the floating diffusion region may overlap the second impurity region.

Abstract: There is provided a solid-state imaging device including a pixel array unit in which pixels are arrayed in a two-dimensional manner, each of the pixels including a plurality of photoelectric conversion elements and a floating diffusion configured to accumulate an electric charge from the plurality of photoelectric conversion elements, wherein the floating diffusion is shared by at least two or more of the photoelectric conversion elements, and wherein one or more of the plurality of photoelectric conversion elements include a transfer gate configured to transfer an electric charge between the photoelectric conversion elements that are adjacent.

Abstract: A transistor having at least one passivated Schottky barrier to a channel includes an insulated gate structure on a p-type substrate in which the channel is located beneath the insulated gate structure. The channel and the insulated gate structure define a first and second undercut void regions that extend underneath the insulated gate structure toward the channel from a first and a second side of the insulated gate structure, respectively. A passivation layer is included on at least one exposed sidewall surface of the channel and metal source and drain terminals are located on respective first and second sides of the channel, including on the passivation layer and within the undercut void regions beneath the insulated gate structure. At least one of the metal source and drain terminals comprises a metal that has a work function near a valence band of the p-type substrate.

Abstract: An improved finFET structure, and method forming the same, including a plurality of fins etched from a semiconductor substrate, a plurality of gates above and perpendicular to the plurality of fins, each comprising a pair of spacers on opposing sides of the gates, and a gap fill material above the semiconductor substrate, below the gate, and between the plurality of fins, wherein the gate separates the gap fill material from each of the plurality of fins.

Abstract: An object of the present invention is to provide a semiconductor device having a conductive film, which sufficiently serves as an antenna, and a method for manufacturing thereof. The semiconductor device has an element formation layer including a transistor, which is provided over a substrate, an insulating film provided on the element formation layer, and a conductive film serving as an antenna, which is provided on the insulating film. The insulating film has a groove. The conductive film is provided along the surface of the insulating film and the groove. The groove of the insulating film may be provided to pass through the insulating film. Alternatively, a concave portion may be provided in the insulating film so as not to pass through the insulating film. A structure of the groove is not particularly limited, and for example, the groove can be provided to have a tapered shape, etc.

Abstract: An optoelectronic integrated device includes a body made of semiconductor material, which is delimited by a front surface and includes a substrate having a first type of conductivity, an epitaxial region, which has the first type of conductivity and forms the front surface, and a ring region having a second type of conductivity, which extends into the epitaxial region from the front surface, and delimiting an internal region. The optoelectronic integrated device moreover includes a MOSFET including at least one body region having the second type of conductivity, which contacts the ring region and extends at least in part into the internal region from the front surface. A photodetector includes a photodetector region having the second type of conductivity, and extends into the semiconductor body starting from the front surface, contacting the ring region.

Abstract: A solid-state imaging device includes a semiconductor substrate configured to include a solid-state imaging element that is provided with a photoelectric conversion region, and a scribe line region that is provided along a periphery of the solid-state imaging element, a wiring layer that is formed to be layered on the semiconductor substrate, a support substrate that is formed to be layered on the wiring layer, and a groove that is provided between a blade region in the scribe line region and the solid-state imaging element, in the semiconductor substrate and penetrates through the semiconductor substrate.

Abstract: A semiconductor structure includes a metal gate, a second dielectric layer and a contact plug. The metal gate is located on a substrate and in a first dielectric layer, wherein the metal gate includes a work function metal layer having a U-shaped cross- sectional profile and a low resistivity material located on the work function metal layer. The second dielectric layer is located on the metal gate and the first dielectric layer. The contact plug is located on the second dielectric layer and in a third dielectric layer, thereby a capacitor is formed. Moreover, the present invention also provides a semiconductor process forming said semiconductor structure.