Abstract: A structure and method of fabrication thereof relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced ?VT compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having dopants in the channel region to be set much more precisely. A novel dopant profile indicative of a distinctive notch enables tuning of the VT setting within a precise range. This VT set range may be extended by appropriate selection of metals so that a very wide range of VT settings is accommodated on the die. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. The result is the ability to independently control VT (with a low ?VT) and VDD, so that the body bias can be tuned separately from VT for a given device.

Abstract: An integrated circuit structure includes a first semiconductor strip, first isolation regions on opposite sides of the first semiconductor strip, and a first epitaxy strip overlapping the first semiconductor strip. A top portion of the first epitaxy strip is over a first top surface of the first isolation regions. The structure further includes a second semiconductor strip, wherein the first and the second semiconductor strips are formed of the same semiconductor material. Second isolation regions are on opposite sides of the second semiconductor strip. A second epitaxy strip overlaps the second semiconductor strip. A top portion of the second epitaxy strip is over a second top surface of the second isolation regions. The first epitaxy strip and the second epitaxy strip are formed of different semiconductor materials. A bottom surface of the first epitaxy strip is lower than a bottom surface of the second epitaxy strip.

Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes receiving a semiconductor device, patterning a first hard mask to form a first recess in a high-resistor (Hi-R) stack, removing the first hard mask, forming a second recess in the Hi-R stack, forming a second hard mask in the second recess in the Hi-R stack. A HR can then be formed in the semiconductor substrate by the second hard mask and a gate trench etch.

Abstract: Elongated metal contacts with longitudinal axes that lie in a first direction are formed to make electrical connections to elongated source and drain regions with longitudinal axes that lie in the first direction, and elongated metal contacts with longitudinal axes that lie a second direction are formed to make electrical connections to elongated source and drain regions with longitudinal axes that lie the second direction, where the second direction lies orthogonal to the first direction.

Abstract: A FinFET device comprises an isolation region in a substrate, wherein the isolation region comprises a plurality of non-vertical sidewalls, a first V-shaped groove, a second V-shaped groove and a third V-shaped groove formed in the substrate, a first cloak-shaped active region over the first V-shaped groove, wherein a top surface of the first cloak-shaped active region comprises a first slope, a second cloak-shaped active region over the second V-shaped groove, wherein a top surface of the second cloak-shaped active region is triangular in shape and a third cloak-shaped active region over the third V-shaped groove, wherein a top surface of the third cloak-shaped active region comprises a second slope.

Abstract: By forming MOSFETs on a substrate having pre-existing ridges of semiconductor material (i.e., a “corrugated substrate”), the resolution limitations associated with conventional semiconductor manufacturing processes can be overcome, and high-performance, low-power transistors can be reliably and repeatably produced. Forming a corrugated substrate prior to actual device formation allows the ridges on the corrugated substrate to be created using high precision techniques that are not ordinarily suitable for device production. MOSFETs that subsequently incorporate the high-precision ridges into their channel regions will typically exhibit much more precise and less variable performance than similar MOSFETs formed using optical lithography-based techniques that cannot provide the same degree of patterning accuracy. Additional performance enhancement techniques such as pulse-shaped doping and “wrapped” gates can be used in conjunction with the segmented channel regions to further enhance device performance.

Abstract: A metal silicide thin film and ultra-shallow junctions and methods of making are disclosed. In the present disclosure, by using a metal and semiconductor dopant mixture as a target, a mixture film is formed on a semiconductor substrate using a physical vapor deposition (PVD) process. The mixture film is removed afterwards by wet etching, which is followed by annealing to form metal silicide thin film and ultra-shallow junctions. Because the metal and semiconductor dopant mixture is used as a target to deposit the mixture film, and the mixture film is removed by wet etching before annealing, self-limiting, ultra-thin, and uniform metal silicide film and ultra-shallow junctions are formed concurrently in semiconductor field-effect transistor fabrication processes, which are suitable for field-effect transistors at the 14 nm, 11 nm, or even further technology node.

Abstract: According to one embodiment, an electrical component comprises a substrate, a functional element formed on the substrate, a first layer which includes through holes, and forms a cavity that stores the functional element on the substrate, and a second layer which is formed on the first layer, and closes the through holes. The first layer includes a first film, a second film on the first film, and a third film on the second film. A Young's modulus of the second film is higher than a Young's modulus of the first film and the third film.

Abstract: According to one embodiment, a MEMS device comprises a first electrode provided on a support substrate, a burying insulating film formed at the sides of the first electrode, and a second electrode opposed to the first electrode, having ends extending outside the ends of the first electrode and able to move in the direction it is opposed to the first electrode.

Abstract: A semiconductor device includes a substrate that is made of a semiconductor material and has a main surface formed with a recess. The semiconductor device also includes a wiring layer formed on the substrate, an electronic element housed in the recess, and a sealing resin covering at least a part of the electronic element.

Abstract: According to one embodiment, a magnetoresistive effect element includes a first ferromagnetic layer, a tunnel barrier formed on the first ferromagnetic layer, and a second ferromagnetic layer formed on the tunnel barrier layer. The tunnel barrier includes a nonmagnetic oxide having a spinel structure. Oxides forming the spinel structure are combined such that a single phase is formed by a solid phase in a component ratio region including a component ratio corresponding to the spinel structure and having a width of not less than 2%.

Abstract: According to one embodiment, a magnetoresistive element comprises a storage layer as a ferromagnetic layer which has magnetic anisotropy perpendicular to film planes, and in which a magnetization direction is variable, a reference layer as a ferromagnetic layer which has magnetic anisotropy perpendicular to film planes, and in which a magnetization direction is invariable, a tunnel barrier layer as a nonmagnetic layer formed between the storage layer and the reference layer, and a first underlayer formed on a side of the storage layer, which is opposite to a side facing the tunnel barrier layer, and containing amorphous W.

Abstract: According to one embodiment, a magnetic random access memory includes a magnetoresistive element, a contact arranged under the magnetoresistive element and connected to the magnetoresistive element, and an insulating film continuously formed from a periphery of the contact to a side surface of the magnetoresistive element and including a protective portion covering the side surface of the magnetoresistive element.

Abstract: According to one embodiment, a magnetoresistance effect element includes a reference layer, a shift canceling layer, a storage layer provided between the reference layer and the shift canceling layer, a tunnel barrier layer provided between the reference layer and the storage layer, and a spacer layer provided between the shift canceling layer and the storage layer, wherein a pattern of the storage layer is provided inside a pattern of the shift canceling layer when the patterns of the storage layer and the shift canceling layer are viewed from a direction perpendicular to the patterns of the storage layer and the shift canceling layer.

Abstract: A magnetoresistive effect element includes first and second conductive layers, a first magnetic layer between the first and second conductive layers having a magnetization direction that is unchangeable, a second magnetic layer between the first and second conductive layers having a magnetization direction that is changeable, a tunnel barrier layer between the first and second magnetic layers, a nonmagnetic layer between the second magnetic layer and the second conductive layer, and a conductive sidewall film that provides a current path between the second magnetic layer and the second conductive layer that has a lower resistance than a current path through the nonmagnetic layer.

Abstract: According to one embodiment, a magnetic memory is disclosed. The magnetic memory includes a substrate, and a contact plug provided on the substrate. The contact plug includes a first contact plug, and a second contact plug provided on the first contact plug and having a smaller diameter than that of the first contact plug. The magnetic memory further includes a magnetoresistive element provided on the second contact plug. The diameter of the second contact plug is smaller than that of the magnetoresistive element.

Abstract: According to one embodiment, a magnetic memory including an isolation region with an insulator in a trench is disclosed. The isolation region defines active areas extending in a 1st direction and having 1st and 2nd active areas, an isolation region extending in a 2nd direction perpendicular to the 1st direction exists between the 1st and 2nd active areas. 1st and 2nd word lines extending in the 2nd direction are buried in a surface of semiconductor substrate. 1st and 2nd select transistors connected to the word lines are on the 1st active area. 1st and 2nd variable resistance elements connected to drain regions of the 1st and 2nd select transistors are on the 1st active area.

Abstract: Disclosed is a memory circuit and method of forming the same. The memory circuit comprises a lower metallization layer defining first conducting lines. A continuous magnetic storage element stack is atop the lower metallization layer wherein a bottom electrode of the stack is in direct contact with the first conducting lines. An upper metallization layer is atop the continuous magnetic storage element stack, the upper metallization layer defining second conducting lines, which are in direct contact with said continuous magnetic storage element stack. Localized areas of the continuous magnetic storage element stack define discrete magnetic bits, each energizable through a selected pair of the first and second conducting lines. In a second aspect and a third aspect, the continuous magnetic storage element stack is respectively partially and fully etched through a single mask, to define the discrete magnetic bits.

Abstract: Disclosed is a memory circuit and method of forming the same. The memory circuit comprises a lower metallization layer defining first conducting lines. A continuous magnetic storage element stack is atop the lower metallization layer wherein a bottom electrode of the stack is in direct contact with the first conducting lines. An upper metallization layer is atop the continuous magnetic storage element stack, the upper metallization layer defining second conducting lines, which are in direct contact with said continuous magnetic storage element stack. Localized areas of the continuous magnetic storage element stack define discrete magnetic bits, each energizable through a selected pair of the first and second conducting lines. In a second aspect and a third aspect, the continuous magnetic storage element stack is respectively partially and fully etched through a single mask, to define the discrete magnetic bits.

Abstract: [Object] To provide a storage element and a storage apparatus capable of performing writing operation in a short time without generating write errors. [Solving Means] A storage element includes a layer structure including a storage layer having a direction of magnetization which changes according to information, a magnetization fixed layer having a fixed direction of magnetization, and an intermediate layer disposed therebetween, which intermediate layer contains a nonmagnetic material. The magnetization fixed layer has at least two ferromagnetic layers having a direction of magnetization tilted from a direction perpendicular to a film surface, which are laminated and magnetically coupled interposing a coupling layer therebetween.

Abstract: According to one embodiment, a magnetoresistive element includes first, second and third magnetic layers, and first and second nonmagnetic layers. The third magnetic layer has stack layers including a first stack layer close to the second magnetic layer, and a second stack layer far from the second magnetic layer. Each of the first and second stack layers includes a first layer made of a ferromagnetic material and a second layer made of a nonmagnetic material, and a first ratio of a film thickness of the first layer to that of the second layer in the first stack layer is higher than a second ratio of a film thickness of the first layer to that of the second layer in the second stack layer.

Abstract: According to one embodiment, a magnetic storage device includes an insulating region, a lower electrode including a first portion formed in a hole provided in the insulating region and a second portion protruded from the insulating region, a spacer insulating film formed on a side surface of at least the second portion of the lower electrode, a magnetic tunneling junction portion formed on a top surface of the lower electrode, and an upper electrode formed on the magnetic tunneling junction portion.

Abstract: A semiconductor device includes a first substrate having an attaching surface on which first electrodes and a first insulating film are exposed, an insulating thin film that covers the attaching surface of the first substrate, and a second substrate which has an attaching surface on which second electrodes and a second insulating film are exposed and is attached to the first substrate in a state in which the attaching surface of the second substrate and the attaching surface of the first substrate are attached together sandwiching the insulating thin film therebetween, and the first electrodes and the second electrodes deform and break a part of the insulating thin film so as to be directly electrically connected to each other.

Abstract: A solid-state imaging device includes a pixel chip, a logic chip and one or more shielding layers. The one or more shielding layers are arranged between or within the pixel chip and/or the logic chip to shield or reduce the effect of electromagnetic interference, radiation generated noise, or electromagnetic waves generated in one portion of the solid-state imaging device from affecting another portion of the solid-state imaging device.

Abstract: A solid state imaging device according to an embodiment includes: an imaging element including a plurality of pixels; a bonding layer formed to be in contact with the imaging element; a first microlens array formed to be in contact with the bonding layer, and including a plurality of first microlenses with a refractive index higher than a refractive index of the bonding layer; and a main lens located above the first microlens array.

Abstract: An optical member set which has a first optical member formed by curing a curable resin composition, and a second optical member which is covered by the first optical member, in which the first optical member has a refractive index of 1.25 to 1.45 and the second optical member has a refractive index of 1.65 to 1.95.

Abstract: A light sensor is described that includes a glass substrate having a diffuser formed therein and at least one color filter integrated on-chip (i.e., integrated on the die of the light sensor). In one or more implementations, the light sensor comprises a semiconductor device (e.g., a die) that includes a semiconductor substrate. At least one photodetector (e.g., photodiode, phototransistor, etc.) is formed in the substrate proximate to the surface of the substrate. The color filter is configured to filter light received by the light sensor to pass light in a limited spectrum of wavelengths (e.g., light having wavelengths between a first wavelength and a second wavelength) to the photodetector. A glass substrate is positioned over the substrate and includes a diffuser. The diffuser is configured to diffuse light incident on the diffuser and to pass the diffused light to the at least one color filter for further filtering.

Abstract: Disclosed herein is a semiconductor device including: a first semiconductor chip having an electronic circuit section and a first connecting section formed on one surface thereof; a second semiconductor chip having a second connecting section formed on one surface thereof, the second semiconductor chip being mounted on the first semiconductor chip with the first and the second connecting sections connected to each other by a bump; a dam formed to fill a gap between the first and the second semiconductor chips on a part of an outer edge of the second semiconductor chip, the part of the outer edge being on a side of a region of formation of the electronic circuit section; and an underfill resin layer filled into the gap, protrusion of the resin layer from the outer edge of the second semiconductor chip to a side of the electronic circuit section being prevented by the dam.

Abstract: A photovoltaic device includes a substrate, a transparent conductive oxide, an n-type window layer, a p-type absorber layer and an electron reflector layer. The electron reflector layer may include zinc telluride doped with copper telluride, zinc telluride alloyed with copper telluride, or a bilayer of multiple layers containing zinc, copper, cadmium and tellurium in various compositions. A process for manufacturing a photovoltaic device includes forming a layer over a substrate by at least one of sputtering, evaporation deposition, CVD, chemical bath deposition process, and vapor transport deposition process. The process includes forming an electron reflector layer over a p-type absorber layer.

Abstract: To provide a connection structure of a wiring cable and a connection method of a wiring cable which enable the downsizing of a head part. The connection structure includes: a semiconductor chip having a plurality of imaging elements formed on a front surface and a plurality of connection pads formed on a rear surface; and a wiring cable in which a plurality of wires are integrally formed and from whose end surface the plural wires are exposed, wherein the plural connection pads of the semiconductor chip and the plural wires exposed from the end surface are connected.

Abstract: A hybrid pixel detector structure including a plurality of detector entities, each detector entity including at least one read-out element, such as a read-out ASIC, and an overlapping substantially edgeless radiation sensitive detector volume, these two being electrically coupled utilizing a number of conductive elements in between, further including a substrate, such as a circuit board, or multiple substrates such as one per detector entity, for accommodating the plurality of detector entities, wherein the substantially edgeless detector volume of at least one detector entity of the plurality includes an overhang portion outside the overlap between the detector volume and the read-out element, and the read-out element of at least one other detector entity of the plurality includes an extension portion, also outside the overlap, with a number of electrical coupling elements to electrically couple to the substrate, such as conductors and/or electronics thereof.

Abstract: A thermal air flow sensor that produces less measurement error is provided. The thermal air flow sensor includes: a semiconductor substrate; a heating resistor, resistance temperature detectors, and an electrical insulator that includes a silicon oxide film, wherein the heating resistor, the resistance temperature detectors, and the electrical insulator are formed on the semiconductor substrate; and a diaphragm portion formed by removing a portion of the semiconductor substrate. The heating resistor and the resistance temperature detectors are formed on the diaphragm portion. The thermal air flow sensor further includes a silicon nitride film formed as the electrical insulator above the heating resistor and the resistance temperature detectors. The silicon nitride film has steps conforming to the patterns of the heating resistor and the resistance temperature detectors. The silicon nitride film has a multilayer structure.

Abstract: [Theme] To provide a chip diode, with which a p-n junction formed on a semiconductor layer can be prevented from being destroyed and fluctuations in characteristics can be suppressed even when a large stress is applied to a pad for electrical connection with the exterior, and a diode package that includes the chip diode. [Solution] A chip diode 15 includes an epitaxial layer 21 with a p-n junction 28, constituting a diode element 29, formed therein, an anode electrode 34 disposed along a top surface 22 of the epitaxial layer 21, electrically connected to a diode impurity region 23, which is the p-side pole of the p-n junction 28, and having a pad 37 for electrical connection with the exterior, and a cathode electrode 41 electrically connected to the epitaxial layer 21, which is the n-side pole of the p-n junction 28, and the pad 37 is provided at a position separated from a position directly above the p-n junction 28.

Abstract: The semiconductor device includes a first semiconductor layer of the first conductive type, a second semiconductor layer having the cubic crystalline structure formed on the first semiconductor layer, an electrode formed on the second semiconductor layer, and a reactive region formed between the second semiconductor layer and the electrode. The second semiconductor layer includes an upper surface that is tilted from the (100) plane. The reactive region includes at least one element constituting the second semiconductor layer, at least one element constituting the electrode, and forming a protuberance extending toward the second semiconductor layer.

Abstract: A semiconductor device includes a superjunction structure. The influence of external charge on device performance is suppressed using a shield electrode, field plate electrodes, and cover electrodes in various configurations. Optional embodiments include placing an interconnection film between certain electrodes and the upper surface of the superjunction structure. Cover electrodes may also be connected to various potentials to limit the effects of external charge on device performance.

Abstract: A semiconductor device includes a semiconductor substrate, a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, a first electrode, and a second electrode. The semiconductor substrate is of a first conductivity type. The first semiconductor layer is of a second conductivity type, provided on the semiconductor substrate. The second semiconductor layer is of a first conductivity type, reaches the semiconductor substrate from a surface of the first semiconductor layer, and surrounds the first semiconductor layer. The third semiconductor layer is of a second conductivity type, separated from the second semiconductor layer, surrounded by the second semiconductor layer, and has a higher concentration of second-conductivity-type impurities than the first semiconductor layer.

Abstract: Device structures, fabrication methods, and design structures for a bipolar junction transistor. An intrinsic base is formed on the substrate, a terminal is formed on the intrinsic base, and an extrinsic base is formed that is arranged in juxtaposition with the intrinsic base on the substrate. The intrinsic base and terminal are respectively comprised of first and second semiconductor materials.

Abstract: An aspect of the present embodiment, there is provided a method of manufacturing a semiconductor device, the method includes providing trenches in an end terminal area of a substrate, the end terminal area surrounding an element area of the a substrate, the trenches surrounding the element area, filling a fluent material mixed with carbonate, oxide and solvent in the each of the trenches, burning the fluent material in the trench to embed an insulator in the trench, and providing an element unit in the element area.

Abstract: Integrated passive devices for silicon on insulator (SOI) FinFET technologies and methods of manufacture are disclosed. The method includes forming a passive device on a substrate on insulator material. The method further includes removing a portion of the insulator material to expose an underside surface of the substrate on insulator material. The method further includes forming material on the underside surface of the substrate on insulator material, thereby locally thickening the substrate on insulator material under the passive device.

Abstract: The present invention provides an integrated inductor and an integrated inductor fabricating method. The integrated inductor comprises: a semiconductor substrate, a plurality of through silicon vias (TSVs), and an inductor. The TSVs are formed in the semiconductor substrate and arranged in a specific pattern, and the TSVs are filled with a metal material to form a patterned ground shield (PGS). The inductor is formed above the semiconductor substrate. The integrated inductor fabricating method comprises: forming a semiconductor substrate; forming a plurality of TSVs in the semiconductor substrate and arranging the TSVs in a specific pattern; filling the TSVs with a metal material to form a PGS. forming an inductor above the semiconductor substrate.

Abstract: The present invention provides an integrated inductor and an integrated inductor fabricating method. The integrated inductor comprises: a semiconductor substrate, a plurality of deep trenches, and an inductor. The deep trenches are formed in the semiconductor substrate and arranged in a specific pattern, and the deep trenches are filled with a metal material to form a patterned ground shield (PGS). The inductor is formed above the semiconductor substrate. The integrated inductor fabricating method comprises: forming a semiconductor substrate; forming a plurality of deep trenches in the semiconductor substrate and arranging the deep trenches in a specific pattern; filling the deep trenches with a metal material to form a patterned ground shield (PGS); and forming an inductor above the semiconductor substrate.

Abstract: The present invention provides an integrated inductor and an integrated inductor fabricating method. The integrated inductor comprises: a semiconductor substrate, an inductor, and a redistribution layer (RDL). The inductor is formed above the semiconductor substrate. The RDL is formed above the inductor and has a specific pattern to form a patterned ground shield (PGS). The integrated inductor fabricating method comprises: forming a semiconductor substrate; forming an inductor above the semiconductor substrate; and forming redistribution layer (RDL) having a specific pattern above the inductor to form a patterned ground shield (PGS).

Abstract: Provided is a semiconductor package including a substrate, a semiconductor chip and a passive device disposed on the substrate, and a heat slug configured to cover the semiconductor chip and the passive device. The substrate and a first electrode of the passive device are electrically connected to each other, and the heat slug and a second electrode of the passive device are electrically connected to each other. The semiconductor package may include multiple passive devices in which a vertical height of each passive device is greater than a horizontal width thereof. Also disclosed is an electronic system, which may include a power supply unit, a microprocessor unit, a function unit, and a display controller unit to receive one or more power supply voltages from the power supply unit. At least one of the microprocessor unit, the function unit, or the display controller unit may further include the described semiconductor package.

Abstract: An electric power conversion apparatus includes a stacked body, a capacitor, a metal frame and a case. The stacked body is formed by stacking semiconductor modules with coolant passages formed therebetween. The frame has both the stacked body and the capacitor fixed therein. The case has all of the stacked body, the capacitor and the frame received therein. Further, the frame has a separation wall that separates the stacked body and the capacitor from each other, a stacked body-surrounding wall that surrounds the stacked body with the help of the separation wall, and a capacitor-surrounding that surrounds the capacitor with the help of the separation wall. The capacitor has a pair of end portions that are opposite to each other in a predetermined direction, in which control terminals of the semiconductor modules of the stacked body protrude, and each at least partially exposed from the capacitor-surrounding wall of the frame.

Abstract: A ferroelectric capacitor includes a ferroelectric film, a lower electrode in contact with one surface of the ferroelectric film, and an upper electrode in contact with the other surface of the ferroelectric film. At least one of the upper electrode and the lower electrode has a stacked electrode structure in which one or more oxide conductive layers and one or more metal layers are stacked alternately, and the stacked electrode structure includes at least one of two or more oxide conductive layers and two or more metal layers.

Abstract: According to one embodiment, there is disclosed a MEMS element. The MEMS element includes a lower electrode having a surface on which a plurality of minute convex portions are formed. A plurality of dielectric bumps are provided on the upper surface of the lower electrode and are thicker than heights of the convex portions. A dielectric layer is provided on the dielectric bumps and the lower electrode. An upper electrode is provided above the dielectric layer. The upper electrode is movable so as to vary capacitance between the upper electrode and the lower electrode.

Abstract: A semiconductor structure comprising a first semiconductor layer, a bulk semiconductor layer, an insulation layer between the first semiconductor layer and the bulk semiconductor layer, a first implanted region that is at least partially within the insulation layer; and a second doped region that is at least partially within the bulk semiconductor layer, wherein the first implanted region has an implant profile that shows a maximum within the insulation layer and a tail extending within the bulk semiconductor layer so as to inhibit the diffusion of a second doping material of the second doped region within the insulation layer.

Abstract: The present disclosure concerns a method involving: forming a strained silicon germanium layer by epitaxial growth over a silicon layer disposed on a substrate; implanting atoms to amorphize the silicon layer and a lower portion of the silicon germanium layer, without amorphizing a surface portion of the silicon germanium layer; and annealing, to at least partially relax the silicon germanium layer and to re-crystallize the lower portion of the silicon germanium layer and the silicon layer, so that the silicon layer becomes a strained silicon layer.

Abstract: The method of manufacturing a semiconductor device according to the present invention includes: a step of forming a semiconductor laminate on a growth substrate with a lift-off layer therebetween; a step of providing grooves in a grid pattern in the semiconductor laminate, thereby forming a plurality of semiconductor structures each having a nearly quadrangular transverse cross-sectional shape; a step of forming a conductive support body; and a step of removing the lift-off layer using a chemical lift-off process, in which step, in supplying an etchant to the grooves via through-holes provided in a portion above the grooves, the lift-off layer is etched from only one side surface of each semiconductor structure.

Abstract: A method for manufacturing a plurality of chips comprises the step of providing a wafer comprising a plurality of chip areas separated by one or more dicing lines, wherein the chip areas are arranged on a first main surface, the step of providing a laser absorption layer on a second main surface opposite to the first main surface and the step of providing a backside metal stack on the laser absorption layer. After that a laser light is applied to the laser absorption layer along the dicing lines before the chips are singulated along the dicing lines by using stealth dicing.