Patents Issued in September 30, 2014
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Patent number: 8850071Abstract: A map intuition system and method that involves machine learning techniques to analyze data sets and identify mappings and transformation rules as well as machine-human interactions to leverage human intuition and intelligence to rapidly complete a map.Type: GrantFiled: May 10, 2011Date of Patent: September 30, 2014Assignee: Liaison Technologies, Inc.Inventors: Walter Hughes Lindsay, Joel Timothy Shellman
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Patent number: 8850072Abstract: The present invention is directed to a secure communication network that enables multi-point to multi-point proxy communication over the network. The network employs a smart server that establishes a secure communication link with each of a plurality of smart client devices installed on local client networks. Each smart client device is in communication with a plurality of agent devices. A plurality of remote devices can access the smart server directly and communicate with agent devices via the secure communication link between the smart server and one of the smart client devices. This communication is enabled without complex configuration of firewall or network parameters by the user.Type: GrantFiled: July 25, 2013Date of Patent: September 30, 2014Assignee: KE2 Therm Solutions, Inc.Inventors: Steve Roberts, Cetin Sert
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Patent number: 8850073Abstract: Provided are, among other things, systems, methods and techniques for controlling data synchronization. Local data-writing operations, made across a number of logical storage units on different data-storage devices, are divided into batches, the batches corresponding to different time segments. The data-writing operations, together with an indication of boundaries between the batches, are transmitted to a remote data-storage location. The boundaries between the batches are determined by at least one of: (1) identifying a period of time of sufficient duration during which no data-writing operations were performed and declaring a point during said period of time as one of the boundaries, (2) obtaining agreement from a plurality of entities, and (3) declaring the boundaries at pre-scheduled points in time.Type: GrantFiled: April 30, 2007Date of Patent: September 30, 2014Assignee: Hewlett-Packard Development Company, L. P.Inventor: John Wilkes
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Patent number: 8850074Abstract: The present invention provides a data synchronization method applied to a host and at least a client. First, the host transmits a request for synchronization operation to the client. The client replies at least a piece of connection information to the host. The host judges if the connection information contains operation flags. If not, the host transmits a request for data transmission to the client for driving the client to transmit the corresponding data of the connection information to the host. When the host completes receiving the data, the host stores an operation flag to the connection information and transmits it to the client for overwriting the connection information in the client.Type: GrantFiled: January 17, 2012Date of Patent: September 30, 2014Assignee: Dimerco Express (Taiwan) CorporationInventor: Li Jen Chen
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Patent number: 8850075Abstract: Predictive, multi-layer caching architectures may be used to predict which elements a user is most likely to navigate to within a collection of elements associated with a predefined layout and, in response, to increase the accessibility of these elements to a client device of the user. For instance, the techniques may utilize a predictive, multi-layer caching architecture for storing these predicted elements to decrease the latency to render these images if the user navigates within the collection of elements in the predicted manner. The collection of elements may comprise images (e.g., a 3D model, a map, etc.), video files, audio files, text files, or any other type of file that is consumable on a client device.Type: GrantFiled: July 6, 2011Date of Patent: September 30, 2014Assignee: Microsoft CorporationInventors: Wenwu Zhu, Zheng Li, Roberto R. Molinari, Hongzhi Li
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Patent number: 8850076Abstract: A component of an electronic device comprises a network connection processor, which comprises a physical network connection block to receive data from and transmit data to a network and a first data processor configured to process data arriving at the network connection processor, and a second data processor configured to process data received from the network connection processor.Type: GrantFiled: March 27, 2008Date of Patent: September 30, 2014Assignee: Nokia CorporationInventors: Kimmo Kalervo Kuusilinna, Jari Antero Nikara, Petri Mikko Johannes Liuha
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Patent number: 8850077Abstract: A method and system for providing a portable document services environment on a computer system is disclosed. An installation application may automatically be loaded from a portable device onto a computer system when the portable device is connected to the computer system. The computer system may automatically access a document service application on the portable device based on information contained in the installation application. One or more document service preferences may automatically be received from the portable device onto the computer system, and an electronic document may be selected. One or more document services may be performed for the selected electronic document based on the one or more document service preferences using the document service application.Type: GrantFiled: June 7, 2006Date of Patent: September 30, 2014Assignee: Xerox CorporationInventors: Barry G. Gombert, Frank M. Goetz, George L. Eldridge
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Patent number: 8850078Abstract: In a computing system, a method and system for a thin client and blade architecture are provided. A blade may generate video, audio, and peripheral control information that may be transmitted to a thin client (TC) by utilizing a video encoder, an audio bridge, and a peripheral bridge. Communication between the blade and the TC may occur based on a communication protocol that may operate independently of an operating system and/or applications running on the blade. The video encoder may dynamically compress the video information according to network capacity and/or video content and may dynamically select from various compression algorithms. The blade may configure and manage operations that interface with the TC. The TC may comprise a video decoder, a transceiver, a processor, a video display bridge, an audio bridge, and a peripheral bridge and may be adapted to communicate with peripheral devices.Type: GrantFiled: April 5, 2012Date of Patent: September 30, 2014Assignee: Broadcom CorporationInventors: Alexander MacInnis, Uri El Zur
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Patent number: 8850079Abstract: A method of setting an address of a component that includes determining a characterization value associated with a consumable, calculating a number of address change operations based upon the characterization value, and setting a last address generated from the number of address change operations as the new address of the component, wherein the characterization value is determined based upon a usage of the consumable.Type: GrantFiled: October 7, 2013Date of Patent: September 30, 2014Assignee: Lexmark International, Inc.Inventors: Zachary Nathan Fister, Gregory Scott Woods
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Patent number: 8850080Abstract: Disclosed is a method and apparatus system to identify mobile media magazine for use with a storage device. The system comprises a random access memory magazine capable of comprising a plurality of random access memory devices. The magazine further comprising a magazine identifier label disposed to be externally viewable. The magazine also comprises at least one storage element cooperating with the magazine adapted to store an electronic magazine identifier that represents the magazine identifier label in non-volatile memory. Each of the random access memory devices can further comprise an individual random access memory device label. The storage device can be adapted to identify the magazine by the magazine identifier label, the electronic magazine identifier or both.Type: GrantFiled: January 21, 2005Date of Patent: September 30, 2014Assignee: Spectra Logic CorporationInventors: Matthew Thomas Starr, Richard Douglas Rector
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Patent number: 8850081Abstract: In one aspect, the issues of events that may impact one or more partitions of sub-socket partitioning in one or more sockets can be handled. Specifically, events for partitions can be handled in a socket with sub-socket partitioning, wherein the events may include reset, interrupts, errors and reliability, availability, and serviceability (RAS) management.Type: GrantFiled: September 27, 2013Date of Patent: September 30, 2014Assignee: Intel CorporationInventors: Ajay Harikumar, Tessil Thomas, Biju Puther Simon
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Patent number: 8850082Abstract: A system for implementing a virtual Universal Serial Bus (USB) compound device with a simulated hub enables a single physical USB device, such as a USB peripheral device, to expose multiple stand-alone functions on the USB bus. Logical functions on the single physical USB device can be added and removed dynamically without re-enumerating the entire device and without affecting the state of other functions. Logical functions can also be independently implemented on any of a number of processors in a system that has access to the USB hardware. Each processor can enumerate as one or more USB devices via the virtual hub. Initialization of logical functions can be performed via the virtual USB hub to maintain a charging current level from a USB host in a device having a discharged battery.Type: GrantFiled: August 22, 2011Date of Patent: September 30, 2014Assignee: QUALCOMM IncorporatedInventors: Igor Malamant, Thomas E. Virgil
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Patent number: 8850083Abstract: A data management system includes a data gathering device and a host device. The data gathering device is configured to gather data regarding a target object and to transmit the data to the host device. The host device operates on the data to produce an output and transmits the output back to the data gathering device. Subsequent action, including the gathering of further data, may be taken on the target object in response to and upon receipt of the output. The data gathering device and host device may communicate via wire or wirelessly. The host device may also exchange information with a network.Type: GrantFiled: July 26, 2006Date of Patent: September 30, 2014Assignee: Bosch Automotive Service Solutions, LLCInventors: Kurt Raichle, Scott Krampitz, Garret Miller
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Patent number: 8850084Abstract: A data processing system includes an audio processor with a main memory for storing data, first and second buffers for temporarily storing the data to input/output an audio signal, and a data input/output (I/O) unit for outputting the stored data. A direct memory access (DMA) controller is provided for transmitting data between the main memory and the first and second buffers according to a DMA transmission process. If transmission of the data stored in the first buffer ends and an interrupt signal is thus generated, the DMA controller increases sizes of the first and second buffers during transmission of the data stored in the second buffer.Type: GrantFiled: March 15, 2012Date of Patent: September 30, 2014Assignee: Samsung Electronics Co., Ltd.Inventor: Kil-Yeon Lim
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Patent number: 8850085Abstract: A method for managing bandwidth of a bus connecting a peripheral device to a host system includes sending, over the bus, a first read request to the host system, incrementing a pending read counter by an amount corresponding to the requested data, receiving, in response to sending the first read request, at least a portion of the requested data from the host system, decrementing the pending read counter by an amount corresponding to the at least the portion of the requested data, and comparing the counter and a threshold to obtain a result. Based on the result, a scheme is selected for managing the bandwidth of the bus. The scheme specifies a ratio of read requests and write requests to be sent on the bus. The method further includes sending, based on the scheme, a second request that is a write request or a second read request.Type: GrantFiled: February 26, 2013Date of Patent: September 30, 2014Assignee: Oracle International CorporationInventors: Brian Edward Manula, Haakon Ording Bugge
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Patent number: 8850086Abstract: An SD switch box embedded within a cellular handset, including circuitry for switching access to NAND storage that is embedded within the cellular handset, between a consumer electronic device that is external to and connected to the cellular handset, and between a base band modem that is embedded within the cellular handset, so as to enable shared use of the NAND memory by the consumer electronic device and by the base band modem, thereby enabling the cellular handset to be operational for cellular communication via its internal base band modem while its internal NAND memory is accessible to the external consumer electronics device.Type: GrantFiled: September 13, 2012Date of Patent: September 30, 2014Assignee: Google Inc.Inventors: Itay Sherman, Eyal Bychkov, Yaron Segalov
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Patent number: 8850087Abstract: The present invention provides the function of dynamically switching the allocation of snapshot data in a pool according to the use status of the pool. More specifically, the present invention provides the function of dynamically switching a storage mode to be applied to the pool from a storage mode in which the snapshot data is aggregated in a specific pool volume to a storage mode in which the snapshot data is distributed to plural pool volumes, or from the storage mode in which the snapshot data is distributed to the plural pool volumes to the storage mode in which the snapshot data is aggregated in the specific pool volume, according to the use status of the pool.Type: GrantFiled: December 5, 2012Date of Patent: September 30, 2014Assignee: Hitachi, Ltd.Inventors: Ran Ogata, Naoyuki Masuda, Yoichi Mizuno, Yutaka Takata
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Patent number: 8850088Abstract: A computer system includes a server using a virtual volume (virtual logical volume) shared by a plurality of storage apparatuses. A management system managing the computer system accepts a selection of a first storage apparatus to be a determination target from among the storage apparatuses, performs a first determination of whether a first access path including the first storage apparatus exists or not. If the first access path exists, the management system performs a second determination of whether or not the first access path is an active access path used by the server for accessing the storage area (the storage area of the storage apparatus) assigned to a part of the virtual volume used by the server, and determines whether the first storage apparatus can be stopped or not on the basis of a result of the first determination or a result of the second determination. The access path is a path from the server to one of the storage apparatuses.Type: GrantFiled: April 18, 2012Date of Patent: September 30, 2014Assignee: Hitachi, Ltd.Inventors: Yuuki Miyamoto, Katsutoshi Asaki
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Patent number: 8850089Abstract: A method and apparatus for unified final buffer with pointer-based and page-based scheme for traffic optimization have been disclosed.Type: GrantFiled: June 18, 2010Date of Patent: September 30, 2014Assignee: Integrated Device Technology, Inc.Inventors: Chi-Lie Wang, Jason Z. Mo
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Patent number: 8850090Abstract: Methods and systems for conducting a transaction between a virtual USB device driver and a USB device are provided. A virtual USB manager of a hypervisor receives a one or more data packets from a client. The virtual USB manager stores of the one or more data packets in a buffer. The virtual USB manager dequeues a data packet from the buffer. The virtual USB manager transmits the data packet to the virtual USB device driver for processing.Type: GrantFiled: November 23, 2011Date of Patent: September 30, 2014Assignee: Red Hat, Inc.Inventor: Hans de Goede
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Patent number: 8850091Abstract: In one embodiment of the invention, a memory apparatus for improved write performance is disclosed. The memory apparatus includes a base printed circuit board (PCB) having an edge connector for plugging into a host server system; a card level power source to provide card level power during a power failure; a memory controller coupled to the card level power source and having one or more memory channels; and one or more non-volatile memory devices (NVMDs) coupled to the card level power source and organized to respectively couple to the memory channels controlled by the memory controller. Each memory controller provides queuing and scheduling of memory operations on a channel for each NVMD in the memory channels. Responsive to power failure, the memory controller receives card level power and changes the scheduling of memory operations to the NVMDs in each memory channel.Type: GrantFiled: January 20, 2013Date of Patent: September 30, 2014Assignee: Virident Systems, Inc.Inventors: Vijay Karamcheti, Ashwin Narasimha
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Patent number: 8850092Abstract: An input module for an industrial controller is configurable to simplify setup and commissioning. The input module includes input terminals configurable, for example, as a counter input. Still other input terminals may be configured to trigger events as a function of the input signals present at the terminals. Time signals corresponding to transitions in state of the input terminals, triggering of events, or operation of the counters may be recorded. The input module is further configurable to transmit data back to the processor or to transmit data directly to another module in the industrial control network.Type: GrantFiled: April 10, 2012Date of Patent: September 30, 2014Assignee: Rockwell Automation Technologies, Inc.Inventors: Bret S. Hildebran, Eric D. Decker, Duwayne D. Mulhall, Peter M. Delic, Kenwood Hall, Harsh Shah, Andreas P. Frischknecht, Mark Chaffee, Scott A. Pierce, Terence S. Tenorio
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Patent number: 8850093Abstract: A mouse with a replaceable sensing unit comprises a main body, a processor unit and a sensing unit. The main body has a containing slot and a first electrical interface. The first electrical interface is disposed in the containing slot. The processor unit is disposed in the main body, and coupled to the first electrical interface. The sensing unit is replaceably disposed in the containing slot of the main body, and the sensing unit is coupled to the first electrical interface when the sensing unit is disposed in the containing slot. The processor unit gets via the first electrical interface an input signal generated when the sensing unit senses the movement of the main body, and then relatively outputs a cursor control signal to a computer apparatus.Type: GrantFiled: May 11, 2013Date of Patent: September 30, 2014Assignee: Dexin CorporationInventor: Yuan-Jung Chang
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Patent number: 8850094Abstract: Disclosed is a method for sharing input/output ports among inverters. A sharing method by a master inverter according to the present disclosure is such that data to be outputted to an output port of a slave inverter is transmitted to the slave inverter where data inputted to input port of the slave inverter is received. Furthermore, a sharing method by the slave inverter is such that data transmitted along with a request frame is outputted to an output port in case of receiving the request frame requesting use of the output port from the master inverter, where data used by the master inverter among data received from input port is transmitted to the master inverter.Type: GrantFiled: January 13, 2012Date of Patent: September 30, 2014Assignee: LSIS Co., Ltd.Inventor: Jong Wook Jeon
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Patent number: 8850095Abstract: A novel and useful cost effective mechanism for detecting the livelock/starvation of transactions in a ring shaped interconnect that utilizes minimal logic resources. Rather than monitor all transactions concurrently in the ring, the mechanism monitors only a single transaction in the ring. A sampling point is located at a point in the ring which contains a set of N latches. If the monitored transaction is not being starved, it is released and the detection logic moves on the next candidate transaction in round robin fashion. If the monitored transaction passes the sampling point a threshold number of times, it is deemed to be starved and a starvation prevention handling procedure is activated. By traversing the entire ring a single transaction at a time, all starving transactions will eventually be detected with an upper limit on the detection time of O(N2).Type: GrantFiled: February 8, 2011Date of Patent: September 30, 2014Assignee: International Business Machines CorporationInventors: Amit Golander, Omer Heymann, Nadav Levison, Eric F. Robinson
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Patent number: 8850096Abstract: A method is provided for using a wireless data card individually to access a network, and a wireless access terminal is provided. The wireless access terminal includes a data line switching module and a power line switching module. The method includes, when the wireless access terminal detects that the wireless data card is connected with a terminal through a universal serial bus (USB) cable, the power line and the data line of the wireless data card are respectively switched to connect the data line and the power line of the external USB interface thereon. A user can still freely connect the 3G network at anytime and anywhere by connecting a common USB cable between the laptop and the wireless data card in the wireless access terminal in the case without the mains supply.Type: GrantFiled: June 22, 2010Date of Patent: September 30, 2014Assignee: ZTE CorporationInventors: Ruijuan Zhang, Hongyu Chen
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Patent number: 8850097Abstract: USB apparatus suitable for interconnection with a USB host having a D? bus coupled to ground via a pull-down resistance, the USB apparatus including a microcontroller having a first port and a second port, the first port being coupled via a resistance to a voltage source and a switch, operated by the microcontroller via the second port, selectably interconnecting the first port and the bus of the USB host.Type: GrantFiled: July 16, 2012Date of Patent: September 30, 2014Assignee: Verifone, Inc.Inventors: Yuan Fuat Chin, Kian Tiong Yeo, Song Gee Lim
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Patent number: 8850098Abstract: A method and apparatus is described herein for supporting direct memory accesses between peer I/O devices. It is determined whether a guest physical address (GPA) referenced by an access generated from an I/O device, is within a range of GPAs associated with local I/O devices based at least in part on a GPA base and a GPA window size. If the GPA is within the window, then the GPA is translated to an HPA based at least in part on a base HPA associated with a local device and then forwarded to that local device. However, if the GPA is not within the window, then the access is forwarded upstream.Type: GrantFiled: December 22, 2009Date of Patent: September 30, 2014Assignee: Intel CorporationInventors: Rajesh Madukkarumukumana, James A. Sutton, II, Ioannis Schoinas, Richard Uhlig
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Patent number: 8850099Abstract: There are configured a first transmission path, along which data is transmitted/received between a controller and a first microcomputer through a first driver, and a second transmission path, along which data is transmitted/received between the controller and the first microcomputer through a second driver. The controller transmits an operation check signal to the first microcomputer through the first or second transmission path, and receives a response signal from the first microcomputer through the first or second transmission path.Type: GrantFiled: January 17, 2012Date of Patent: September 30, 2014Assignee: Seiko Epson CorporationInventor: Yoshinobu Monbetsu
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Patent number: 8850100Abstract: A system, a method and a non-transitory computer readable medium are disclosed. The non-transitory computer readable medium may store instructions for: (I) interleaving at least two portions of a first codeword of a group of codewords between at least two flash memory planes while violating at least one ordering rule out of (a) an even odd ordering rule, (b) a programming type ordering rule, and (c) a codeword portions ordering rule; and (II) interleaving different portions of other codewords of the group of codewords between multiple flash memory planes while maintaining the even odd ordering rule, the programming type ordering rule and the codeword portions ordering rule. The at least two portions may be programmed to rows in different flash memory blocks, and the flash memory planes may belong to the same or multiple flash memory dies. The programming type ordering may define different decoupling sequence steps with sizes set for different programming types according to sensitivity to noise.Type: GrantFiled: November 17, 2011Date of Patent: September 30, 2014Assignee: Densbits Technologies Ltd.Inventors: Avi Steiner, Hanan Weingarten, Guy Azrad, Avigdor Segal
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Patent number: 8850101Abstract: In one embodiment, a system comprises a plurality of memory ports. The memory ports are distributed into a plurality of subsets, where each subset is identified by a subset index. The system further comprises a first address hashing unit configured to receive a request including at least one virtual memory address. Each virtual memory address is associated with a replication factor, and the virtual memory address refers to graph data. The first address hashing unit translates the replication factor into a corresponding subset index based on the virtual memory address, and converts the virtual memory address to a hardware based memory address. The hardware based address refers to data in the memory ports within a subset indicated by the corresponding subset index.Type: GrantFiled: September 11, 2013Date of Patent: September 30, 2014Assignee: Cavium, Inc.Inventors: Jeffrey A. Pangborn, Gregg A. Bouchard, Rajan Goyal, Richard E. Kessler
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Patent number: 8850102Abstract: A method comprises receiving a request to access a memory array having one or more memory erase units with a data area of flash array and with a specific amount of memory which offers small data programming capability, the specific amount of memory configured to be erased simultaneously or sequentially with a main memory block of the memory array; and if the memory access request includes programming small data, then providing access to the specific amount of memory, or if the memory access request does not include programming small data, then providing access to the data area of flash array. The size of the specific amount of memory may be pre-defined, and the specific amount of memory may be a different memory technology.Type: GrantFiled: August 23, 2007Date of Patent: September 30, 2014Assignee: Nokia CorporationInventors: Petteri Hanhimäki, Ilpo Jarvinen
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Patent number: 8850103Abstract: A NAND flash memory logical unit. The NAND flash memory logical unit includes a control circuit that responds to commands and permits program and/or erase commands to be interruptible by read commands. The control circuit includes a set of internal registers for performing the current command, and a set of external registers for receiving commands. The control circuit also includes a set of supplemental registers that allow the NAND flash memory logical unit to have redundancy to properly hold state of an interrupted program or erase command. When the interrupted program or erase command is to resume, the NAND flash memory logical unit thus can quickly resume the paused program or erase operation. This provides significant improvement to read response times in the context of a NAND flash memory logical unit.Type: GrantFiled: August 28, 2009Date of Patent: September 30, 2014Assignee: Microsoft CorporationInventor: John G. Bennett
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Patent number: 8850104Abstract: A data storage method includes identifying, in a set of data items associated with respective logical addresses for storage in a memory, a first subset of the logical addresses associated with the data items containing application data, and a second subset of the logical addresses associated with the data items containing parity information that has been calculated over the application data. The data items associated with the first identified subset are stored in one or more first physical memory areas of the memory, and the data items associated with the second identified subset are stored in one or more second physical memory areas of the memory, different from the first physical memory areas. A memory management task is performed independently in the first physical memory areas and in the second physical memory areas.Type: GrantFiled: March 14, 2012Date of Patent: September 30, 2014Assignee: Apple Inc.Inventors: Avraham Meir, Oren Golov, Naftali Sommer, Moshe Neerman
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Patent number: 8850105Abstract: A method, to be executed by an application program according to an embodiment, for controlling a memory system provided with a nonvolatile memory includes: acquiring an unused memory area from an operating system installed in an information processing apparatus provided with the memory system; prohibiting the acquired unused memory area from being used by any application program other than the above application program; acquiring the address of the acquired unused memory area; and notifying the address of the acquired unused memory area to the memory system. In the method according to an embodiment for controlling a memory system, prohibition state put by the prohibiting is preserved until receiving a change instruction.Type: GrantFiled: March 14, 2012Date of Patent: September 30, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Toshikatsu Hida, Michiko Noguchi
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Patent number: 8850106Abstract: Provided are a computer program product, system, and method for populating strides of tracks to demote from a first cache to a second cache. A first cache maintains modified and unmodified tracks from a storage system subject to Input/Output (I/O) requests. A determination is made to demote tracks from the first cache. A determination is made as to whether there are enough tracks ready to demote to form a stride, wherein tracks are written to a second cache in strides defined for a Redundant Array of Independent Disk (RAID) configuration. A stride is populated with tracks ready to demote in response to determining that there are enough tracks ready to demote to form the stride. The stride of tracks, to demote from the first cache, are promoted to the second cache. The tracks in the second cache that are modified are destaged to the storage system.Type: GrantFiled: May 7, 2012Date of Patent: September 30, 2014Assignee: International Business Machines CorporationInventors: Michael T. Benhase, Lokesh M. Gupta, Matthew J. Kalos
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Patent number: 8850107Abstract: A memory system includes a management-information restoring unit. The management-information restoring unit determines whether a short break has occurred referring to a pre-log or a post-log in a NAND memory. The management-information restoring unit determines that a short break has occurred when the pre-log or the post-log is present in the NAND memory. In that case, the management-information restoring unit determines timing of occurrence of the short break, and, after selecting a pre-log or a post-log used for restoration, performs restoration of the management information reflecting these logs on a snapshot. Thereafter, the management-information restoring unit applies recovery processing to all write-once blocks in the NAND memory, takes the snapshot again, and opens the snapshot and the logs in the past.Type: GrantFiled: April 9, 2013Date of Patent: September 30, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Junji Yano, Hidenori Matsuzaki, Kosuke Hatsuda
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Patent number: 8850108Abstract: A plurality of storage nodes in a single chassis is provided. The plurality of storage nodes in the single chassis is configured to communicate together as a storage cluster. Each of the plurality of storage nodes includes nonvolatile solid-state memory for user data storage. The plurality of storage nodes is configured to distribute the user data and metadata associated with the user data throughout the plurality of storage nodes such that the plurality of storage nodes maintain the ability to read the user data, using erasure coding, despite a loss of two of the plurality of storage nodes. The chassis includes power distribution, a high speed communication bus and the ability to install one or more storage nodes which may use the power distribution and communication bus. A method for accessing user data in a plurality of storage nodes having nonvolatile solid-state memory is also provided.Type: GrantFiled: June 4, 2014Date of Patent: September 30, 2014Assignee: Pure Storage, Inc.Inventors: John Hayes, John Colgrove, Robert Lee, Peter Vajgel, Par Botes
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Patent number: 8850109Abstract: An apparatus having a first circuit and a second circuit. The first circuit may be configured to (i) parse a first data word into a first data portion and a second data portion and (ii) parse a first address into a first address portion and a second address portion. The second circuit generally has a plurality of memory blocks. The second circuit may be configured to store the second data portion in a particular one of the memory blocks using (i) the first data portion to determine the particular memory block and (ii) the first address portion to determine a particular one of a plurality of locations within the particular memory block. The data portion may not be stored in the memory blocks. The particular location may be determined independently of the second address portion.Type: GrantFiled: December 22, 2011Date of Patent: September 30, 2014Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.Inventors: David B. Grover, Richard J. Stephani, Gordon W. Priebe
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Patent number: 8850110Abstract: A virtual tape device includes a storage unit, an instruction unit, and a reading unit. The storage unit stores a plurality of logical volumes. The instruction unit receives a request for mounting a specified logical volume from an information processing apparatus. The instruction unit issues a mount instruction to both a physical tape device communicated to the virtual tape device and a virtual device communicated to the virtual tape device when the specified logical volume is not stored in the storage unit. The mount instruction instructs to mount the specified logical volume. The reading unit reads data of the specified logical volume to the storage unit from a device which outputs a mount completion notification first among both of the devices which have received the mount instruction.Type: GrantFiled: November 15, 2012Date of Patent: September 30, 2014Assignee: Fujitsu LimitedInventors: Fumio Matsuo, Katsuo Enohara, Takaaki Yamato, Nobuyuki Hirashima, Takashi Murayama
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Patent number: 8850111Abstract: An information storage medium includes: a user data area for recording user data; a spare area including spare blocks each for replacing a defective block occurring in the user data area; and a defect management area in which information about the defective block occurring in the user data area is recorded, wherein the spare blocks of the spare area include usable spare blocks with replacement blocks existing in forward parts of the usable spare blocks in a usage order, and usable spare blocks without replacement blocks existing in forward parts of the usable spare blocks in the usage order, wherein a next available position pointer of the spare area is recorded in the defect management area, and the next available position pointer of the spare area indicates a first usable spare block from among the usable spare blocks without the replacement blocks existing in the forward parts of the usable spare blocks in the usage order.Type: GrantFiled: May 27, 2010Date of Patent: September 30, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Sung-hee Hwang, Kyung-geun Lee, In-ho Hwang
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Patent number: 8850112Abstract: A non-volatile hard disk drive cache system is coupled between a processor and a hard disk drive. The cache system includes a control circuit, a non-volatile memory and a volatile memory. The control circuit causes a subset of the data stored in the hard disk drive to be written to the non-volatile memory. In response to a request to read data from the hard disk drive, the control circuit first determines if the requested read data are stored in the non-volatile memory. If so, the requested read data are provided from the non-volatile memory. Otherwise, the requested read data are provided from the hard disk drive. The volatile memory is used as a write buffer and to store disk access statistics, such as the disk drive locations that are most frequently read, which are used by the control circuit to determine which data to store in the non-volatile memory.Type: GrantFiled: May 16, 2011Date of Patent: September 30, 2014Assignee: Round Rock Research, LLCInventor: Dean A. Klein
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Patent number: 8850113Abstract: A method begins by a processing module determining whether to convert data between a redundant array of independent disks (RAID) format and a dispersed storage network (DSN) format. The method continues with the processing module retrieving the data from a RAID memory to produce retrieved RAID data when the data is to be converted from the RAID format to the DSN format. The method continues with the processing module converting stripe-block data of the retrieved RAID data into a plurality of sets of encoded data slices and outputting the plurality of sets of encoded data slices to at least one of the RAID memory and a DSN memory for storage therein.Type: GrantFiled: December 31, 2010Date of Patent: September 30, 2014Assignee: Cleversafe, Inc.Inventors: Andrew Baptist, Gary W. Grube, Timothy W. Markison, Jason K. Resch
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Patent number: 8850114Abstract: The invention is an improved storage array controller that adds a level of indirection between host system and storage array. The storage array controller controls a storage array comprising at least one solid-state storage device. The storage array controller improvements include: garbage collection, sequentialization of writes, combining of writes, aggregation of writes, increased reliability, improved performance, and addition of resources and functions to a computer system with a storage subsystem.Type: GrantFiled: January 3, 2011Date of Patent: September 30, 2014Inventors: Daniel L Rosenband, Michael John Sebastian Smith
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Patent number: 8850115Abstract: A memory package and methods for writing data to and reading data from the memory package are presented. The memory package includes a volatile memory and a high-density memory. Data is written to the memory package at a bandwidth and latency associated with the volatile memory. A directory map associates a volatile memory address with data in the high-density memory. A copy of the directory map is stored in the high-density memory. The methods allow writing to and reading from the memory package using a first memory read/write interface (e.g. DRAM interface, etc.), though data is stored in a device of a different memory type (e.g. FLASH, etc.).Type: GrantFiled: April 3, 2012Date of Patent: September 30, 2014Assignee: International Business Machines CorporationInventor: Robert B. Tremaine
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Patent number: 8850116Abstract: A method for communication between an initiator system and a storage cluster. The method comprises receiving an initial I/O request from the initiator system to a first storage system; providing a referral response from the first storage system to the initiator system, the referral response providing information for directing the initiator system to a second storage system; notifying the second storage system regarding the referral response via a prefetch notice, the prefetch notice including an operation type and address information for accessing requested data; when the initial I/O request is a read request, prefetching at least a portion of the requested data stored in the second storage system in to a cache; receiving a second I/O request from the initiator system to the second storage system; and providing to the initiator system the portion of the prefetched data from the cache of the second storage system.Type: GrantFiled: March 10, 2010Date of Patent: September 30, 2014Assignee: LSI CorporationInventor: Andrew J. Spry
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Patent number: 8850117Abstract: A storage system includes a plurality of storage devices connected together, where the plurality of storage devices include a copy-source storage device having data to be copied and copy-target storage devices capable of receiving the copied data. The copy-source storage device includes a copy-source controller for checking parameters contained in a buffer newly setting command to determine a group of storage devices to be subjected to a newly setting of a buffer and a copy-target storage device in the group and transmitting the parameters to the specified copy-target storage device. The copy-target storage device includes a copy-target controller for performing a buffer newly setting process in the specified copy-target storage device on the basis of the parameters received from the copy-source storage device and notifying the copy-source storage device of a result of the buffer newly setting process.Type: GrantFiled: March 12, 2010Date of Patent: September 30, 2014Assignee: Fujitsu LimitedInventor: Naruhiro Oogai
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Patent number: 8850118Abstract: A memory access determination circuit includes a counter that switches between a first reference value and a second reference value in accordance with a control signal to generate a count value based on the first reference value or the second reference value. A controller performs a cache determination based on an address that corresponds to the count value and outputs the control signal in accordance with the cache determination. A changing unit changes the second reference value in accordance with the cache determination.Type: GrantFiled: September 14, 2011Date of Patent: September 30, 2014Assignee: Fujitsu Semiconductor LimitedInventor: Kazuhiko Okada
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Patent number: 8850119Abstract: Embodiments are provided for operating a memory device by issuing certain instructions to the memory device that specify a cache and/or memory array address where an operation is to occur. One such method may include loading data into a specified address of a cache of the memory device, in which the specified address of the cache of the memory device may be specified by a first program sequence received at an interface of the memory device from a host external to the memory device. The method may also include writing the data from the specified address of the cache of the memory device to a specified address of a memory array of the memory device, in which the specified address of the memory array of the memory device may be specified by a second program sequence received at the interface from the host.Type: GrantFiled: April 22, 2013Date of Patent: September 30, 2014Assignee: Micron Technology, Inc.Inventors: Theodore T. Pekny, Jeff Yu
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Patent number: 8850120Abstract: Some embodiments of the present invention provide a system that performs stores in a memory system. During operation, the system performs a store for a first thread, which involves creating an entry for the store in a store queue for the first thread. It also involves attempting to store-mark a corresponding cache line for the first thread by sending a store-mark request for the first thread to the memory system, wherein a store-mark on the cache line indicates that one or more store queue entries are waiting to be committed to the cache line. If the attempt to store-mark the cache line fails because a second thread holds a store-mark on the cache line, and if obtaining the store-mark will ensure forward progress for the first thread, the system forces the second thread to release the store-mark, so the first thread can acquire a store-mark for the cache line.Type: GrantFiled: December 15, 2008Date of Patent: September 30, 2014Assignee: Oracle America, Inc.Inventors: Robert E. Cypher, Haakan E. Zeffer