Abstract: A load/store unit with an outstanding load miss buffer and a load miss result buffer is configured to read data from a memory system having a level one cache. Missed load instructions are stored in the outstanding load miss buffer. The load/store unit retrieves data for multiple dependent missed load instructions using a single cache access and stores the data in the load miss result buffer. The outstanding load miss buffer stores a first missed load instruction in a first primary entry. Additional missed load instructions that are dependent on the first missed load instructions are stored in dependent entries of the first primary entry or in shared entries. If a shared entry is used for a missed load instruction the shared entry is associated with the primary entry.

Abstract: Systems and methods for cache optimization, the method comprising monitoring cache access rate for one or more cache tenants in a computing environment, wherein a first cache tenant is allocated a first cache having a first cache size which may be adjusted; determining a cache profile for at least the first cache over one or more time intervals according to data collected during the monitoring, analyzing the cache profile for the first cache to determine an expected cache usage model for the first cache; and analyzing the cache usage model and factors related to cache efficiency for the one or more cache tenants to dictate one or more constraints that define boundaries for the first cache size.

Abstract: An apparatus generally having a processor, a cache and a circuit is disclosed. The processor may be configured to generate (i) a plurality of access addresses and (ii) a plurality of program counter values corresponding to the access addresses. The cache may be configured to present in response to the access addresses (i) a plurality of data words and (ii) a plurality of address information corresponding to the data words. The circuit may be configured to record a plurality of events in a file in response to a plurality of cache misses. A first of the events in the file due to a first of the cache misses generally includes (i) a first of the program counter values, (ii) a first of the address information and (iii) a first time to prefetch a first of the data word from a memory to the cache.

Abstract: A method, system, apparatus, and computer-readable medium are provided for performing read-ahead operations for sequential read operations. A method includes maintaining a bitmap including a plurality of bits, each bit corresponding to a sector of the disk cache and containing data indicating whether the corresponding sector is valid and can be used to satisfy read requests. The method includes receiving a request to read a sector of the disk cache, and in response, identifying a bit in the bitmap that corresponds to the requested sector. Further, the method includes determining whether the disk cache contains valid data for a sector previous to the requested sector by examining a bit in the bitmap previous to the bit that corresponds to the requested sector, and in response, reading sequentially into the disk cache sectors of the disk cache corresponding to bits in the bitmap following the bit corresponding to the requested sector.

Abstract: In one embodiment, a system comprises a memory and a memory controller that provides a cache access path to the memory and a bypass-cache access path to the memory, receives requests to read graph data from the memory on the bypass-cache access path and receives requests to read non-graph data from the memory on the cache access path. A method comprises receiving a request at a memory controller to read graph data from a memory on a bypass-cache access path, receiving a request at the memory controller to read non-graph data from the memory through a cache access path, and arbitrating, in the memory controller, among the requests using arbitration.

Abstract: A method, apparatus, and system of exclusive access during a critical sub-operation to enable simultaneous operations are disclosed. In one embodiment, a method of a host device includes identifying a critical sub-operation of an operation associated with a storage system, applying a lock associated with the critical sub-operation based on a type of the sub-operation, providing exclusive access of the critical sub-operation to a first instance requiring the critical sub-operation, denying other instances access to the critical sub-operation during an interval comprising a period when the first instance executes the critical sub-operation, and releasing the lock when the critical sub-operation is no longer required by the first instance. The first instance and the other instances may originate on different host devices.

Abstract: Various embodiments of the present invention allow concurrent accesses to a cache. A request to update an object stored in a cache is received. A first data structure comprising a new value for the object is created in response to receiving the request. A cache pointer is atomically modified to point to the first data structure. A second data structure comprising an old value for the cached object is maintained until a process, which holds a pointer to the old value of the cached object, at least one of one of ends and indicates that the old value is no longer needed.

Abstract: A method for implementing data storage and a dual port, dual element storage device are provided. A storage device includes a predefined form factor including a first port and a second port, and a first storage element and a second storage element. A controller coupled between the first port and second port, and the first storage element and second storage element controls access and provides two separate data paths to the first storage element and second storage element.

Abstract: A system and computer implemented method for storing of data in the memory of a computer system in order at a fast rate is provided. The method includes launching a first store to memory. A wait counter is initiated. A second store to memory is speculatively launched when the wait counter expires. The second store to memory is cancelled when the second store achieves coherency prior to the first store to memory.

Abstract: Disclosed is an improved approach for using advanced metadata to implement an architecture for managing I/O operations and storage devices for a virtualization environment. According to some embodiments, a Service VM is employed to control and manage any type of storage device, including directly attached storage in addition to networked and cloud storage. The advanced metadata is used to track data within the storage devices. A lock-free approach is implemented in some embodiments to access and modify the metadata.

Abstract: A method includes scheduling a memory request requested by a thread executing on a processing system. The scheduling is based on at least one of a number of critical sections being executed on the processing system by the thread and a number of other threads executing on the processing system being blocked from execution on the processing system by execution of the thread. In at least one embodiment of the invention, the thread is associated with a first application of a plurality of applications executing on the processing system and the scheduling is further based on an indicator of application priority.

Abstract: A method and system for providing a shared data resource coordinator within a storage virtualizing data processing system is disclosed. According to one embodiment of the present invention, a first node of a plurality of nodes is configured to process requests to access a shared data resource on behalf of the plurality of nodes, where the plurality of nodes includes a logical volume configuration server configured to present a logical volume to one or more logical volume configuration clients. A second node is then selected from the plurality of nodes and configured to process requests to access the shared data resource on behalf of the plurality of nodes.

Abstract: Dynamically adjusting a block size in a data transfer operation is disclosed. An indication that a data transfer operation has commenced is received. A first portion of data is read using a first read block size. A first throughput associated with the first read block size is determined. A second portion of data that is different from the first portion of data is read using a second block size that is different from the first read block size. One of the first and second read block sizes is used to complete the data transfer operation based on a comparison of the first throughput and a throughput of the second read block size. This process can be repeated several times as necessary.

Abstract: A system and method in accordance with the present invention provides for a solution benefiting from providing for non-duplicative access to data located in a system memory via the alignment of transaction sub-command breaking points with memory burst boundaries associated with the system memory, by creating a plurality of sub-commands for a transaction each having breaking points, identifying a plurality of memory burst boundaries for the system memory each having burst boundary points, and aligning a plurality of breaking points with a plurality of burst boundary points to provide single access to data located in the system memory.

Abstract: Embodiments of the present disclosure provide methods and systems for securely installing software on a computing device, such as a mobile device. In one embodiment, the device executes an installer that securely installs the software. In order to perform installations securely, the installer configures one or more secure containers for the software and installs the software exclusively in these containers. In some embodiments, the installer randomly determines the identifiers for the containers. These identifiers remain unknown to the software to be installed. Instead, an installation framework maintains the correspondence between an application and its container. Other methods and apparatuses are also described.

Abstract: The transmission of buffered data is coordinated between a storage medium and a host in response to a request from the host. One or more blocks of data are transferred from the storage medium to a buffer memory. One or more frames of data are transmitted from the buffer memory to the host, wherein the number of blocks ending in the frame is recorded in a blocks/frame register, and possibly also in a block count accumulator register. Buffer release pulses for releasing buffer space in memory are sent to the buffer memory, based on the number of blocks in the blocks/frame register, or the number of blocks accumulated in the block count accumulator register when a signal is received from the host. A pointer which points to the last block of data successfully transferred is updated in accordance with the buffer release pulses.

Abstract: A memory device and related techniques are provided to modify data stored in the memory device without the need to send the data to an external device. A command is received at the memory device to modify data stored at a memory location in a memory array of the memory device. The command includes a value to be used for modifying the data. The memory device reads data from the memory location. The data read from the memory location is modified with modify circuit in the memory device based on the value obtained form the command to produce results data. The results data produced by the modify circuit is written back to the memory location. Since the memory device does not need to send the data read from the memory array off-chip to another device, referred to herein as a host device, to update the data, the input/output bandwidth of the bandwidth is substantially reduced, allowing for lower power memory device operation and reduced latency.

Abstract: Embodiments disclosed herein provide a high performance content delivery system in which versions of content are cached for servicing web site requests containing the same uniform resource locator (URL). When a page is cached, certain metadata is also stored along with the page. That metadata includes a description of what extra attributes, if any, must be consulted to determine what version of content to serve in response to a request. When a request is fielded, a cache reader consults this metadata at a primary cache address, then extracts the values of attributes, if any are specified, and uses them in conjunction with the URL to search for an appropriate response at a secondary cache address. These attributes may include HTTP request headers, cookies, query string, and session variables. If no entry exists at the secondary address, the request is forwarded to a page generator at the back-end.

Abstract: Exemplary system, and computer program product embodiments for changing ownership of cartridges, such as virtual cartridges between remotely located virtual tape libraries, are provided. In one embodiment, by way of example only, processes and protocols for the changing ownership of the cartridges are controlled from a primary location to a secondary location. The production site is moved for the cartridges. The ownership of the cartridges is waived. Access is allowed to the cartridges. Additional data is written and replicated using resources of the cartridges.

Abstract: Improved techniques and apparatus for managing data between a host device (e.g., host computer) and a media device are disclosed. The data being managed can, for example, pertain to media data for media assets. The managing of the media data thus can involve transfer of media assets between the host device and the media device. In one embodiment, the transfer of media assets between a host device and a media device can be referred to as data backup.

Abstract: Disclosed is a data processing and/or storage system. The data processing and/or storage system may include at least two interfaces, wherein each of the at least two interfaces includes a non-dedicated communication port for communicating data to and form external data systems or clients based on a rule base.

Abstract: Systems and methods of enhanced virtual storage replication are disclosed. An exemplary method comprises moving a virtual tape from a local virtual library to a remote virtual library. The method also comprises ejecting the virtual tape moved to the remote virtual library. The method also comprises recycling the ejected virtual tape at the local virtual library based on a remote retention policy.

Abstract: A method, system, and computer product for accessing a point in time in a replication based environment with a journal, the replication environment having a production site and a replication site, the replication site having a journal, comprising, receiving a request for a point in time, rolling the replication site to the point in time, determining if applications running in the replication environment are dependant on the LUN size, and presenting, based on a positive determination, a faked LUN size to the applications.

Abstract: A method, system, and program product for transparently shifting between using a virtual service layer (VSL) performing active-active replication which presents the volume of the first site and the volume of the second site as a single volume and a second replication technique for replicating the volume of the first site and the volume of the second site without use of the VSL.

Abstract: A method is used in managing consistency groups in storage systems. A consistency group is created from a set of snapshot mount points. A snapshot mount point is a logical object accessible for using a replica of a logical volume. An operation is performed on the consistency group.

Abstract: A virtual machine may use a first one or more volumes in which one or more virtual disk image files are stored. The virtual machine may also use data stored in a second one or more volumes, where the virtual machine is configured to bypass a hypervisor to access the second one or more volumes. A time consistent backup of the virtual machine, including both the virtual disk image files of the first one or more volumes and the data of the second one or more volumes, may be created.

Abstract: A method for deleting a relation between a source and a target in a multi-target architecture is described. The multi-target architecture includes a source and multiple targets mapped thereto. In one embodiment, such a method includes initially identifying a relation for deletion from the multi-target architecture. A target associated with the relation is then identified. The method then identifies a sibling target that inherits data from the target. Once the target and the sibling target are identified, the method copies the data from the target to the sibling target. The relation between the source and the target is then deleted. A corresponding computer program product is also disclosed and claimed herein.

Abstract: Multiple copy sets of data are maintained on one or more storage devices. Each copy set includes at least some of the same data units as other sets. Different sets optionally have data units stored in different orders on the storage device(s). A particular one of the sets of data is selected as the set to be accessed in response to detecting a particular scenario.

Abstract: An apparatus includes a first storage unit, a second storage unit, a setting unit configured to set a level of data deletion used for executing a job, an identification unit configured to identify a storage unit to be used for the job, and a control unit configured to, if the set level is a predetermined level and the identified storage unit is the first storage unit, store data of the job into the first storage unit and overwrite the stored data when the job is executed, and configured to, if the set level is the predetermined level and the identified storage unit is the second storage unit, encrypt data of the job and store the encrypted data into the second storage unit when the job is executed.

Abstract: A computing device and method for managing security of a memory or storage device without the need for administer privileges. To access the secure memory, a host provides a data block containing a control command and authentication data to the memory device. The memory device includes a controller for controlling access to a secure memory in the memory device. The memory device identifies the control command in the data block, authenticates the control command bused on the authentication data, and executes the control command to allow the host device to access the secure memory.

Abstract: A hybrid storage device that includes a hard-disk drive (HDD) and a flash memory is described. When control logic in the hybrid storage device receives a request from an external device to write a block of data to a logical address in a first portion of an address space that maps to the HDD, the control logic writes the block of data to the HDD. However, if there is a change in environmental state information of the hybrid storage device during the write operation, the control logic writes at least a portion of the block of data to a logical address for the block of data in a second portion of the address space which maps to the flash memory. Note that the address space may be common to the external device and the hybrid storage device.

Abstract: An example of the invention is a method of data migration from a source volume including storage areas of a plurality of source storage tiers different in performance capability to a destination volume including storage areas of a plurality of destination storage tiers different in performance capability, data relocation being performed among the plurality of source storage tiers in accordance with accesses to the source volume during the data migration. The method includes: starting the data migration between volumes from the source volume to the destination volume; acquiring information on a data arrangement in the source volume determined based on an access history to the source volume during the data migration between volumes from the source volume to the destination volume; and determining a data arrangement in the destination volume during the data migration between volumes based on the data arrangement indicated by the acquired information.

Abstract: A mechanism is provided for enabling throttling on average write throughput instead of peak write throughput for solid-state storage devices. The mechanism assures an average write throughput within a range but allows excursions of high throughput with periods of low throughput offsetting against those of heavy usage. The mechanism periodically determines average throughput and determines whether average throughput exceeds a high throughput threshold for a certain amount of time without being offset by periods of low throughput.

Abstract: Memory resource partitioning code allocates a memory partition in response to a process requesting access to memory storage. Memory partition rules may define attributes of the memory partition. The attributes may include a minimum memory allocation and a maximum memory allocation for the memory partition.

Abstract: A method is provided for performing memory operations in response to instructions to perform a double data rate (DDR) memory reference voltage training in the voltage domain by a processing device and determining a DDR memory reference voltage and a DDR memory delay time based upon the memory operation. Computer readable storage media are also provided. A circuit is provided that includes a communication interface portion coupled to a memory and to a processing device. The circuit also includes a circuit portion, coupled to the communication interface portion that has a hardware state machine or an algorithm. The state machine or algorithm provides instructions to the processing device to perform a double data rate (DDR) reference voltage training in the voltage domain.

Abstract: A method for managing Virtual Machine (VM) storage space is provided. In the method, a Storage Balloon Agent (SBA) module deployed in a VM is adopted to directly acquire virtual storage free block information and deliver the acquired virtual storage free block information to a Storage Balloon Daemon (SBD) module deployed in a Virtual Machine Monitor (VMM) layer; and the SBD module releases a part or all of physical storage space corresponding to the virtual storage free block information, and marks virtual storage blocks corresponding to the released physical storage space as unavailable. A corresponding system and a physical host are further provided in the present invention. Through the method of an embodiment of the present invention, use condition of virtual storage space can be acquired in real time, and a large number of read and write operations of a storage system can be avoided.

Abstract: It is made possible to update information registered in a database of iSNS, SLP and the like in response to a configurational change in a storage device, and for a host computer to discover a disk volume. In response to changes in contents of operation to alter a storage configuration such as in creating or deleting a volume or LUN, contents of the alteration are reflected in the database of iSNS or SLP. Also, in response to a change in setting of LUN masking, a discovery domain of iSNS or attribute values of SLP are updated so that the host computer can discover the disk volume. Also, objects and services are reregistered periodically according to a registration period of iSNS or lifetime of SLP to prevent registered contents from expiring.

Abstract: Disclosed is an apparatus for processing a remote page fault included in an optional local node within a cluster system configuring a large integration memory (CVM) by integrating individual memories of a plurality of nodes. The apparatus includes a memory including a CVM-map, a node memory information table, a virtual memory area, and a CVM page table, and a main controller mapping the large integration memory to an address space of a process when a user process requests memory allocation.

Abstract: Methods and systems for latency optimized ATS usage are disclosed. Aspects of one method may include communicating a memory access request using an untranslated address and also an address translation request using the same untranslated address, where the translation request may be sent without waiting for a result of the memory access request. The memory access request and the address translation request may be made in either order. A translation agent may be used to translate the untranslated address, and the translated address may be communicated to the device that made the memory access request. The translated address may also be used to make the memory access. Accordingly, by communicating the translated address without having to wait for completion of the memory access, or vice versa, the requesting device may reduce latency for memory accesses when using untranslated addresses.

Abstract: Systems and methods are disclosed for adaptive writing behavior for a system having non-volatile memory (“NVM”). A memory interface of a system can be configured to determine whether a write preference of the system is skip-sequential. In response to determining that the write preference is skip-sequential, the memory interface can sequentially program data to a first set of pages of a block of the NVM. In addition, the memory interface can sequentially pre-merge gaps between the first set of pages with one or more pages of a data block. Moreover, the memory interface can be configured to switch to an alternative programming state in response to determining that at least one condition has been satisfied. For example, the memory interface can stop programming data sequentially, and instead program data in the order that the data is received from a file system.

Abstract: Methods are provided for efficiently storing data to a data storage device or subsystem. The data storage device may be a Solid-State Device (SSD), and may be implemented as part of a RAID (Redundant Array of Independent Disks) or other subsystem. When existing data is read and updated, and must be re-stored, the data is assembled and stored as if it were new data, and is written in a sequential manner, instead of being written to the same storage location. A newer generation number distinguishes it from the previous version. If the storage subsystem employs data striping, stripe size may be matched with the size of a logical collection of data (e.g., an extent), so that each such logical collection of data is wholly stored on just device in the storage subsystem. Concurrent device access may be supported by concurrently writing substripes of data to each device/extent.

Abstract: A method and system for implementing vector prefetch with streaming access detection is contemplated in which an execution unit such as a vector execution unit, for example, executes a vector memory access instruction that references an associated vector of effective addresses. The vector of effective addresses includes a number of elements, each of which includes a memory pointer. The vector memory access instruction is executable to perform multiple independent memory access operations using at least some of the memory pointers of the vector of effective addresses. A prefetch unit, for example, may detect a memory access streaming pattern based upon the vector of effective addresses, and in response to detecting the memory access streaming pattern, the prefetch unit may calculate one or more prefetch memory addresses based upon the memory access streaming pattern. Lastly, the prefetch unit may prefetch the one or more prefetch memory addresses into a memory.

Abstract: A mechanism is provided for automatically routing network interconnects in a data processing system. A processor in a node of a plurality of nodes receives network topology from neighboring nodes in the plurality of nodes within the data processing system. The processor constructs a system node map that identifies a physical connectivity between the node and the neighboring nodes. The processor programs a switch in the node with a connectivity map that indicates a set of point-to-point connections with the neighboring nodes. The set of point-to-point connections comprise locally-connected connections and pass-through connections.

Abstract: A microprocessor receives first, second, and third program-adjacent macroinstructions. The first macroinstruction moves a first operand to a first register from a second register. The second macroinstruction performs an arithmetic/logic operation using the first operand in the second register and a second operand in a third register to generate a result, loads the result back into the first register, and updates condition codes based on the result. The third macroinstruction conditionally jumps to a target address. An instruction translator simultaneously translates the first, second, and third program-adjacent macroinstructions into a single micro-operation for execution by an execution unit. The micro-operation performs the arithmetic/logic operation using the first operand in the second register and the second operand in third register to generate the result, loads the result back into the first register, updates the condition codes based on the result, and conditionally jumps to the target address.

Abstract: In a multi-threaded processor, thread priority variables are set up in memory. The actual assignment of thread priority is based on the expiration of a thread precedence counter. To further augment, the effectiveness of the thread precedence counters, starting counters are associated with each thread that serve as a multiplier for the value to be used in the thread precedence counter. The value in the starting counters are manipulated so as to prevent one thread from getting undue priority to the resources of the multi-threaded processor.

Abstract: A Load/Store Disjoint instruction, when executed by a CPU, accesses operands from two disjoint memory locations and sets condition code indicators to indicate whether or not the two operands appeared to be accessed atomically by means of block-concurrent interlocked fetch with no intervening stores to the operands from other CPUs. In a Load Pair Disjoint form of the instruction, the accesses are loads and the disjoint data is stored in general registers.

Abstract: Provided is a processor including an instruction issue unit that issues a vector load instruction read from a main memory based on branch target prediction of a branch target in a branch instruction, a data acquisition unit that starts issue of a plurality of acquisition requests for acquiring a plurality of vector data based on the issued vector load instruction from the main memory, a determination unit that determines a success or a failure of the branch target prediction after the branch target is determined, and a vector load management unit that, when the branch target prediction is determined to be a success, acquires all vector data based on the plurality of acquisition requests and then transfers all the vector data to a vector register, and, when the branch target prediction is determined to be a failure, discards the vector data acquired by the issued acquisition requests.

Abstract: A processor apparatus according to the present invention is a processor apparatus which shares hardware resources between a plurality of processors, and includes: a first determination unit which determines whether or not a register in each of the hardware resources holds extension context data of a program that is currently executed; a second determination unit which determines to which processor the extension context data in the hardware resource corresponds; a first transfer unit which saves and restores the extension context data between programs in the processor; and a second transfer unit which saves and restores the extension context data between programs between different processors.

Abstract: A system, apparatus and method for multithread handling on a multithread processing device are described herein. Embodiments of the present invention provide a multithread processing device for multithread handling including a plurality of registers operatively coupled to an instruction dispatch block, including thread-control registers for selectively disabling threads. In various embodiments, the multithread processing device may include a thread-operation register for selectively providing a lock to a first thread to prevent a second thread from disabling the first thread while the first thread has the lock. In still further embodiments, the multithread processing device may be configured to atomically disable and release a lock held by a thread. Other embodiments may be described and claimed.

Abstract: An apparatus and method for dynamically determining the execution mode of a reconfigurable array are provided. Performance information of a loop may be obtained before and/or during the execution of the loop. The performance information may be used to determine whether to operate the apparatus in a very long instruction word (VLIW) mode or in a coarse grained array (CGA) mode.