Patents Issued in September 30, 2014
  • Patent number: 8850221
    Abstract: The invention relates to a method for protecting a sensitive operation by checking the integrity of at least a subset of the data manipulated by the sensitive operation. Data to be checked are divided into blocks, an intermediate integrity check value being computed for each block, the intermediate integrity check values being computed in random order. The invention also relates to a cryptographic device wherein at least one sensitive operation of the cryptographic device is protected by a method according to the invention.
    Type: Grant
    Filed: April 22, 2013
    Date of Patent: September 30, 2014
    Assignee: Gemalto SA
    Inventors: Stephanie Salgado, David Vigilant, Guillaume Fumaroli
  • Patent number: 8850222
    Abstract: A digital content display method adaptable to an electronic apparatus is provided. The electronic apparatus includes a display interface and a display driving apparatus. The digital content display method includes following steps. An encrypted digital content is received by the display driving apparatus. The encrypted digital content is decrypted by the display driving apparatus according to an algorithm. The display interface of the electronic apparatus is driven by the display driving apparatus according to the decrypted digital content so that the display interface displays the digital content. Additionally, an electronic apparatus and a display driving apparatus thereof are also provided.
    Type: Grant
    Filed: July 28, 2010
    Date of Patent: September 30, 2014
    Assignee: Novatek Microelectronics Corp.
    Inventor: Tzung-Yuan Lee
  • Patent number: 8850223
    Abstract: An inventive apparatus that integrates the operation of a hard disk emulator and a cryptographic accelerator on a single blade server card. An application with cryptographic operations can off load computationally intensive calculations to the cryptographic accelerator so that the speed at which the application performs actions can be increased significantly. Typically, the hard disk emulator is a flash memory component and the accelerator can perform at least modular exponentiation calculations. One bus is employed for communication between the hard disk emulator and the accelerator. Another bus is employed to communicate with other resources off the card. Often, the card is configured to operate as one of a several blade servers in a chassis.
    Type: Grant
    Filed: December 20, 2002
    Date of Patent: September 30, 2014
    Assignee: F5 Networks, Inc.
    Inventors: Brett Helsel, Ryan C. Kearny, Greg Davis, David D. Schmitt
  • Patent number: 8850224
    Abstract: Example articles of manufacture, methods, and systems facilitate having encryption policy follow an article of manufacture like a tape cartridge. One example article of manufacture includes a media portion (e.g., tape) and a non-media portion (e.g., housing). The media portion is configured to store machine readable information. The article of manufacture could be a tape, a disk, a memory, and other computer readable media. The article of manufacture also includes an encryption policy information indicator. The encryption policy information indicator can be configured to store information that controls an encryption policy associated with the article of manufacture. Therefore, encryption policy can, for example, follow a tape cartridge rather than be resident solely in a controlling application (e.g., tape library).
    Type: Grant
    Filed: December 23, 2009
    Date of Patent: September 30, 2014
    Inventors: Robert A. Yang, Roderick B. Wideman
  • Patent number: 8850225
    Abstract: A combination firmware and hardware cryptographic core architecture is provided for encrypting, decrypting and authenticating data. The core provides flexibility to change and add new cryptographic protocols, while providing increased performance by loading new firmware into a microcontroller that programs behavior of various components in the core. The core combines a microcontroller programmable by firmware, and flexible aligner, insertion and removal controllers programmed by the microcontroller that process, manage and manipulate an incoming data stream as it moves through the core. The firmware may be reprogrammed upon an enhancement or change to a protocol while still realizing performance benefits of the hardware. Reprogramming the microcontroller allows it to change the way the aligner, insertion and removal controllers manipulate the data stream as it enters various components.
    Type: Grant
    Filed: April 16, 2010
    Date of Patent: September 30, 2014
    Assignee: Exelis Inc.
    Inventors: Lee Noehring, Kevin Osugi, Darren Parker, Nhu-Ha Yup
  • Patent number: 8850226
    Abstract: A test comment is transmitted by a test unit in the form of a data transmission via a mains supply to one or more electric components of a network. Each electric component that receives a transmitted test command transmits a test response that characterizes each electric component, in the form of a data transmission via the mains supply back to the test unit, the transmitted response being then evaluated in the test unit.
    Type: Grant
    Filed: November 29, 2010
    Date of Patent: September 30, 2014
    Assignee: Siemens Aktiengesellschaft
    Inventors: Rainer Falk, Steffen Fries, Milos Svoboda
  • Patent number: 8850227
    Abstract: Aspects of the subject technology relate to systems, methods, and machine-readable media for performing a cryptographic operation. A system can be configured to submit a request, to a security device, for a decrypted user encryption key, wherein the security device is configured to decrypt the user encryption key by unbinding the user encryption key using a user authorization key. The system can receive, in response to the submitted request, the decrypted user encryption key and decrypt authorization data for a cryptographic key using the decrypted user encryption key. The system can submit a request for the security device to load the cryptographic key, wherein authorization data is used to authorize the request, and submit a request for the security device to perform a cryptographic operation using the loaded cryptographic key.
    Type: Grant
    Filed: September 5, 2012
    Date of Patent: September 30, 2014
    Assignee: Google Inc.
    Inventors: Darren Krahn, Sumit Gwalani
  • Patent number: 8850228
    Abstract: A computing device and a method for controlling access to driver programs obtains a first system time at the time that an application uses a CTL_CODE to access a driver program. The first system time and the CTL_CODE is encrypted to generate an encrypted CTL_CODE which is then sent to the driver program. The encrypted CTL_CODE is decrypted to obtain the first system time and the CTL_CODE therein. A second system time at the time that the driver program receives the encrypted CTL_CODE is obtained and compared with the first system time. Access to the driver program is allowed if a difference between the first system time and the second system time falls within a predetermined range, and access to the driver program is forbidden if the difference is beyond the predetermined range.
    Type: Grant
    Filed: April 17, 2012
    Date of Patent: September 30, 2014
    Assignees: Hong Fu Jin Precision Industry (ShenZhen) Co., Ltd., Hon Hai Precision Industry Co., Ltd.
    Inventors: Guang-Jian Wang, Jin-Rong Zhao, Xiao-Mei Liu
  • Patent number: 8850229
    Abstract: An apparatus for generating a decryption key for use to decrypt a block of encrypted instruction data being fetched from an instruction cache in a microprocessor at a fetch address includes a first multiplexer that selects a first key value from a plurality of key values based on a first portion of the fetch address. A second multiplexer selects a second key value from the plurality of key values based on the first portion of the fetch address. A rotater rotates the first key value based on a second portion of the fetch address. An arithmetic unit selectively adds or subtracts the rotated first key value to or from the second key value based on a third portion of the fetch address to generate the decryption key.
    Type: Grant
    Filed: October 29, 2013
    Date of Patent: September 30, 2014
    Assignee: VIA Technologies, Inc.
    Inventors: G. Glenn Henry, Terry Parks, Brent Bean, Thomas A. Crispin
  • Patent number: 8850230
    Abstract: This document describes tools capable of enabling cloud-based movable-component binding. The tools, in some embodiments, bind protected media content to a movable component in a mobile computing device in a cryptographically secure manner without requiring the movable component to perform a complex cryptographic function. By so doing the mobile computing device may request access to content and receive permission to use the content quickly and in a cryptographically robust way.
    Type: Grant
    Filed: January 14, 2008
    Date of Patent: September 30, 2014
    Assignee: Microsoft Corporation
    Inventors: Patrik Schnell, Alexandre V Grigorovitch, Kedarnath A Dubhashi
  • Patent number: 8850231
    Abstract: Disclosed are a method and apparatus for a data storage library comprising a plurality of drives and a combination bridge controller device adapted to direct and make compatible communication traffic between a client and the plurality of drives. The combination bridge controller device is further adapted to encrypt a first data package received from the client. The combination bridge controller device is further adapted to transmit the encrypted first data package, a first moniker and a first message authentication code to one of the plurality of drives for storage to a cooperating mobile storage medium. The combination bridge controller device is further adapted to decrypt the first data package when used in combination with a first key associated with the first moniker and guarantee the decryption of the first data package was successfully accomplished with authentication of the first message authentication code.
    Type: Grant
    Filed: December 18, 2009
    Date of Patent: September 30, 2014
    Assignee: Spectra Logic Corporation
    Inventors: Matthew Thomas Starr, Jeff Robert Boyton, Nathan Christopher Thompson
  • Patent number: 8850232
    Abstract: A device and a method for protecting a cryptographic module of which the method includes: estimating a functionality of a circuit that is adapted to malfunction when a physical parameter has a first value different from a nominal parameter value at which the cryptographic module functions correctly. The cryptographic module malfunctions when the physical parameter has a second value different from the nominal parameter value and a difference between the first value and the nominal parameter value being smaller than a difference between the second value and the nominal parameter value. A cryptographic module protective measure is applied if estimating that the circuit malfunctions.
    Type: Grant
    Filed: March 19, 2008
    Date of Patent: September 30, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Michael Priel, Asaf Ashkenazi, Dan Kuzmin, Anton Rozen
  • Patent number: 8850233
    Abstract: A multi-phase voltage regulator module system includes a VRM and a phase control circuit. The VRM is capable of outputting a load detecting voltage which is direct proportion to the load of the CPU. The phase control circuit outputs a first level phase switching signal to the VRM, and a core voltage outputted by the VRM to the CPU is changed from N phases to M phases when the load detecting voltage increases to a first voltage. The phase control circuit a second level phase switching signal to the VRM, and the core voltage outputted by the VRM to the CPU from M phases to N phases when the load detecting voltage decreases to a second voltage. The first voltage is higher than the second voltage. M is larger than N.
    Type: Grant
    Filed: January 5, 2010
    Date of Patent: September 30, 2014
    Assignee: ASUSTeK Computer Inc.
    Inventors: Sheng-Chieh Su, Jung-Tai Chen
  • Patent number: 8850234
    Abstract: An information processing apparatus and method include measuring power consumptions of devices and outputting power consumption data, receiving operational conditions of the devices for measuring the power consumptions of the devices, setting the operational conditions of the devices according to application-setting conditions, and executing an application program to measure reference power consumptions for executing the application program. The information processing apparatus includes a power consumption data-transmitting section transmitting power consumption data, a normalized power consumption-calculating section receiving normalized reference power consumption calculated from reference power consumptions of information processing apparatuses, and calculating normalized power consumption from the normalized reference power consumption and the reference power consumptions.
    Type: Grant
    Filed: June 21, 2010
    Date of Patent: September 30, 2014
    Assignee: Fujitsu Limited
    Inventors: Satoshi Kazama, Yoshiyasu Nakashima, Isamu Yamada, Masatomo Yasaki
  • Patent number: 8850235
    Abstract: A system and method for enabling power over Ethernet (PoE) for legacy devices. Legacy devices often represent a large installed base of devices. This installed base of devices (e.g., mobile computing devices) may have little or no PoE functionality. It is a feature of the present invention that an external device (e.g., dongle) can be used to retrofit such an installed base of devices for use with state of the art PoE functionality.
    Type: Grant
    Filed: June 17, 2011
    Date of Patent: September 30, 2014
    Assignee: Broadcom Corporation
    Inventors: Wael William Diab, Stephen Bailey
  • Patent number: 8850236
    Abstract: A method for power gating a core by a SoC is provided. Instruction Pointer information, state of the core, core access information and wake up latency information of the core are used in power gating or un-gating of the core. A change in state of the core is detected by a device driver and is provided to a power management unit. As the state of the core changes from active to passive, the wake up latency information and the core access information of the core are retrieved by the SoC from a database to perform either the power gating or the un-gating of the core. The database is prepared by analyzing code blocks statically.
    Type: Grant
    Filed: June 17, 2011
    Date of Patent: September 30, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Rudrajit Sengupta
  • Patent number: 8850237
    Abstract: Some embodiments of the inventive subject matter provide a power distribution system for a data processing system. The power distribution system includes a plurality of uninterruptible power supply (UPS) units, respective ones of which are configured to be coupled to respective loads via respective load busses, at least one reserve bus, a switching circuit configured to selectively couple and decouple the UPS units and the load busses to and from the at least one reserve bus and a control circuit configured to control the switching circuit responsive to a state of the data processing system. The control circuit may be configured to cause the switching circuit to couple the first UPS unit to the at least one reserve bus concurrent with the first UPS unit being coupled to a first load via a first load bus.
    Type: Grant
    Filed: September 24, 2011
    Date of Patent: September 30, 2014
    Assignee: Eaton Corporation
    Inventors: Yakov Lvovich Familiant, Luis Rafael Pereira, Kevin Lee, Michael P. Nowak
  • Patent number: 8850238
    Abstract: A server rack system includes a first network switch, a second network switch, servers, a rack internal device, and an integrated management module (IMM). Management network ports of baseboard management controllers (BMCs) of the servers are connected to the first network switch. A management network port of the rack internal device is connected to the second network switch. A first management network port and a second management network port of the IMM are respectively connected to the first network switch and the second network switch. The IMM communicates with the BMCs of the servers through the first network switch, so as to obtain operation states of the servers, or control operations of the servers. The IMM communicates with the rack internal device through the second network switch, so as to obtain an operation state of the rack internal device, or control an operation of the rack internal device.
    Type: Grant
    Filed: February 13, 2012
    Date of Patent: September 30, 2014
    Assignee: Inventec Corporation
    Inventor: Hao-Hao Wang
  • Patent number: 8850239
    Abstract: The network computing cluster includes one or more network computing stations and one or more power autarkic network computing stations supplied by one or more associated local power generators. The power autarkic network computing stations and the local power generators are connected with a local power network. A control signal is sent to a resource managing unit of the network computing cluster via a communication network. The control signal indicates the ability of the power autarkic network computing stations to process IT-services. The resource managing unit receives the control signal via the communication network. Triggered by the control signal, the resource managing unit sends a signal for transferring an IT-service processed by a network computing station of the network computing stations to the network computing station via the communication network. The processed IT-service is transferred to one of the power autarkic network computing stations via the communication network.
    Type: Grant
    Filed: June 18, 2010
    Date of Patent: September 30, 2014
    Assignee: Alcatel Lucent
    Inventors: Stefan Wahl, Markus Bauer
  • Patent number: 8850240
    Abstract: A method for relating a data processing system with a power branch circuit is provided in the illustrative embodiments. A second signal is combined with a power signal to form a combination signal, the power signal including a first power usage by the data processing system and a second power usage by a modulating signal. The second signal is synchronized with the modulating signal in the power signal. A determination is made whether an amplitude of a frequency of the second signal is increasing in the combined signal over a period. Responsive to the determining being affirmative, the data processing system is related with the power branch circuit.
    Type: Grant
    Filed: April 30, 2012
    Date of Patent: September 30, 2014
    Assignee: International Business Machines Corporation
    Inventors: Malcolm Scott Allen-Ware, Wael R El-Essawy, Alexandre Peixoto Ferreira, Thomas Walter Keller, Jr., Juan Carlos Rubio
  • Patent number: 8850241
    Abstract: Multi-stage power adapter techniques are described in which a power adapter for a device is configured to selectively switch between a relatively low power supply and a relatively high power supply. The low power supply may be employed upon initial connection of the adapter to a host device to ensure that the adapter is safe when disconnected and does not supply full power before the device is ready to receive the high power supply. The low power supply may supply enough power for the host device to detect the connection of the adapter and establish initial communication with the adapter. A switch to the high power supply by the adapter may then occur in response to a notification from the host device that indicates the host device is ready for the high power supply. The switch to high power supply enables normal operation of the host device.
    Type: Grant
    Filed: October 12, 2012
    Date of Patent: September 30, 2014
    Assignee: Microsoft Corporation
    Inventors: Van Winston Oler, Hiroo Umeno
  • Patent number: 8850242
    Abstract: The self-powered device is configured to be powered by energy collected from a surrounding environment. The self-powered device includes an energy collector, and a memory having instructions for selecting one of a plurality of modes of operation. The energy collector is configured to collect energy to power the self-powered device from a surrounding environment in which the self-powered device is located. The plurality of modes of operation include: (i) a low-power mode of operation in which the self-powered device consumes less than a pre-determined or adaptively-determined amount of power and the self-powered device uses less than its full capabilities, and (ii) and a high-power mode of operation in which self-powered device consumes more than the pre-determined or adaptively-determined amount of power and the self-powered device uses its full capabilities.
    Type: Grant
    Filed: July 19, 2013
    Date of Patent: September 30, 2014
    Assignee: Invent.ly, LLC
    Inventors: Holden D. Jessup, Daylyn M. Meade, Timothy P. Flood, Clive A. Hallatt
  • Patent number: 8850243
    Abstract: A method and system for managing power consumption of a pool of computing devices that are logically grouped to provide a common set of functionality is disclosed. One aspect of certain embodiments includes predicting resource utilization for each device without installing customized software, firmware or hardware on the device.
    Type: Grant
    Filed: March 2, 2011
    Date of Patent: September 30, 2014
    Assignee: Tso Logic Inc.
    Inventor: Aaron J Rallo
  • Patent number: 8850244
    Abstract: Embodiments described herein achieve Wake-on-LAN to allow optical modules the ability to wake up link partners instantaneously when there is data to be transmitted or received. As such, Wake-on-LAN features are provided for a side-band handshaking protocol and channel that is independent from the normal data traffic path.
    Type: Grant
    Filed: June 21, 2011
    Date of Patent: September 30, 2014
    Assignee: Cisco Technology, Inc.
    Inventors: Norman Tang, Nick Peng, Anthony Nguyen, David Lai
  • Patent number: 8850245
    Abstract: A method for the switching of participants of a bus system from a first state with reduced energy consumption to a second state with increased energy consumption relative to the first state, wherein, for communication between the participants of the bus system, data frames are transmitted which comprise, inter alia, a message identification field (e.g. CAN message) and a useful-data field (e.g. CAN payload), wherein, according to said method, each participant, for switching from the first state to the second state, reacts on data frames with respectively predetermined data contents in the message identification field as well as in the useful-data field. Further, in the bus system, for selective switching of a participant from the first state to the second state, those data frames will be transmitted on whose message-identification-field contents and useful data-field-contents the selectively addressable participant reacts.
    Type: Grant
    Filed: August 29, 2011
    Date of Patent: September 30, 2014
    Assignee: ELMOS Semiconductor AG
    Inventors: Radoslaw Watroba, Rainer Kraly, Christian Schmitz
  • Patent number: 8850246
    Abstract: A display apparatus and a method thereof including: a display unit which displays an image based on a video signal; a battery unit which supplies battery power; and a controller which controls adjusts brightness of the image based on residual quantity of the battery unit when the battery power is supplied.
    Type: Grant
    Filed: February 17, 2012
    Date of Patent: September 30, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-hoon Lee, Myoung-jun Lee, Tac-hoon Kim
  • Patent number: 8850247
    Abstract: In one embodiment, the present invention includes a method for sending a first link handshake signal between a first subsystem and a power management unit (PMU) of a system on a chip (SoC) to request entry into a power saving state for the first subsystem, sending a second link handshake signal between the first subsystem and the PMU to acknowledge the request, and placing the first subsystem into the power saving state without further signaling between the PMU and the first subsystem. Other embodiments are described and claimed.
    Type: Grant
    Filed: June 25, 2013
    Date of Patent: September 30, 2014
    Assignee: Intel Corporation
    Inventors: Woojong Han, Madhu Athreya, Ken Shoemaker, Arvind Mandhani, Mahesh Wagh, Ticky Thakkar
  • Patent number: 8850248
    Abstract: A multi-core electronic system for accessing a data storage device includes a plurality of processors, a data transmission interface and a rate adjustment module. The processors respectively provide a bandwidth requirement, and communicate with the data storage device via the shared data transmission interface. The rate adjustment module receives the bandwidth requirements, and determines a transmission rate of the data transmission interface according to the bandwidth requirements.
    Type: Grant
    Filed: July 26, 2011
    Date of Patent: September 30, 2014
    Assignee: MStar Semiconductor, Inc.
    Inventors: Ping-Cheng Hou, Cheng-Yu Lu, Chieh-Wen Shih, Jen-Shi Wu, Chung-Ching Chen
  • Patent number: 8850249
    Abstract: In one embodiment, the present invention includes a method for receiving an information packet in a first port from an interconnect while an agent associated with the first port is in an idle low power state, transmitting a first signal from the first port along the interconnect to request re-transmission of the information packet, and sending a second signal from the first port to the agent to cause the agent to enter a fully active power state. Other embodiments are described and claimed.
    Type: Grant
    Filed: April 26, 2010
    Date of Patent: September 30, 2014
    Assignee: Intel Corporation
    Inventors: Eric Dahlen, Jimbo Alexander, Parthipan Satchi
  • Patent number: 8850250
    Abstract: Methods and apparatus for integration of a processor and an input/output hub are described. In one embodiment, a sideband signal may cause change in a power management state of a processor or an integrated I/O logic. A single integrated circuit die may include both the processor and the integrated I/O logic. Other embodiments are also disclosed.
    Type: Grant
    Filed: June 1, 2010
    Date of Patent: September 30, 2014
    Assignee: Intel Corporation
    Inventors: Lily Pao Looi, Stephan J. Jourdan, Selim Bilgin, Sin S. Tan, Anant S. Deval, Srikanth T. Srinivasan
  • Patent number: 8850251
    Abstract: An application may receive a request to control a power mode. The power mode may be controlled based on the request and the operational status of the application. In one example, the power mode may be disabled until termination of the application. In another example, the power mode may be disabled for a specified amount of time or according to operational status of multiple applications and/or electronic pages. In yet another example, the power mode may be controlled according to an operating system power management configuration.
    Type: Grant
    Filed: January 19, 2011
    Date of Patent: September 30, 2014
    Assignee: Intellectual Ventures Fund 79 LLC
    Inventor: Joon Maeng
  • Patent number: 8850252
    Abstract: A USB host for wakeup from a sleep state includes a hold memory, a USB host controller, and a USB driver. When going to sleep, the USB driver sends a suspend command to the USB host controller in response to receiving a sleep command. The USB driver also reads a controller context from the USB host controller and saves the controller context in the hold memory. Thereafter, the USB driver turns off one or more supply potentials and one or more clocks in the host controller, and returns a sleep acknowledgement. While in sleep, the interface pins are placed in a hold state and notification to the operating system are disabled.
    Type: Grant
    Filed: November 3, 2011
    Date of Patent: September 30, 2014
    Assignee: Nvidia Corporation
    Inventors: Hemalkumar Chandrkant Doshi, Rajkumar Jayaraman, Seshendra Gadagottu, Narendra Damahe
  • Patent number: 8850253
    Abstract: An information processing unit having an auto power-off function includes a mode setting means for setting one mode from a plurality of pre-prepared modes. The pre-prepared modes include a first power-saving mode and a second power-saving mode. Also included are a processing execution means for executing game application or contents replay as internal processing, and a power controlling means for controlling power of the information processing unit. The power controlling means continues power-on in the first power-saving mode and changes to power-off in the second power-saving mode when a non-operated state in which no input operation has been carried out by the user has continued for a predetermined time or longer during execution of the internal processing.
    Type: Grant
    Filed: January 25, 2013
    Date of Patent: September 30, 2014
    Assignee: Sony Computer Entertainment Inc.
    Inventors: Yasuhiro Yamanaka, Fumiaki Hisamatsu
  • Patent number: 8850254
    Abstract: A method includes detecting a trigger condition, and in response to detecting the trigger condition, reducing a voltage applied to a graphics controller component of a memory controller. The reduction in voltage may cause the voltage to be reduced below a voltage level required to maintain context information in the graphics controller component.
    Type: Grant
    Filed: July 11, 2013
    Date of Patent: September 30, 2014
    Assignee: Intel Corporation
    Inventors: Eric C. Samson, Aditya Navale
  • Patent number: 8850255
    Abstract: A storage system includes a storage and control units. In each of the control units: a relay unit relays access to the storage; an access controller accesses the storage through one of the relay unit in the control unit and the relay unit in another of the control units; and an operational-state controller determines whether or not the relay unit in the above-mentioned another control unit is usable when the operational-state controller detects occurrence of an abnormality in the above-mentioned another control unit, and makes the above-mentioned another control unit transition to a partially-operational state when the relay unit in the above-mentioned another control unit is usable. In the partially-operational state, at least the access controller in the above-mentioned another control unit is not in operation and the access controller in the control unit can access the storage through the relay unit in the above-mentioned another control unit.
    Type: Grant
    Filed: July 22, 2011
    Date of Patent: September 30, 2014
    Assignee: Fujitsu Limited
    Inventors: Kazuo Nakashima, Ryohei Nishimiya, Fumio Hanzawa, Masanori Ito, Kazuhiro Hara
  • Patent number: 8850256
    Abstract: Provided is a communication circuit (10) connected with a plurality of function blocks (A, B) that perform processing based on a first clock signal, and mediates communication between the function blocks (A, B). The communication circuit (10) includes N number of communication means, where N is a positive integer, having the same data width as communication data output from the function blocks, and each of the N number of communication means performs communication processing based on N number of second clock signals specified by 1/N of a frequency of the first clock signal, respectively corresponding to the N number of communication means and having a phase difference of 360/N degrees from each other. This makes it possible to provide a communication circuit between function blocks in which the amount of necessary hardware and power consumption is small, the timing design is easy, and the communication latency is low.
    Type: Grant
    Filed: March 26, 2010
    Date of Patent: September 30, 2014
    Assignee: Nec Corporation
    Inventor: Atsufumi Shibayama
  • Patent number: 8850257
    Abstract: A method and device for preventing a defect in a CDR circuit from hindering synchronization between connection nodes and for preventing connection failures. The CDR circuit generates a synchronization clock from received data. A connection failure processor performs a connection failure process if synchronization based on the synchronization clock between connection nodes is not established when a first predetermined time from when the reception of the received data is started elapses. A correction processor corrects operation of the CDR circuit if synchronization based on the synchronization clock between connection nodes is not established when a second predetermined time, which is shorter than the first predetermined time, from when the reception of the received data is started elapses.
    Type: Grant
    Filed: June 26, 2013
    Date of Patent: September 30, 2014
    Assignee: Spansion LLC
    Inventor: Masato Tomita
  • Patent number: 8850258
    Abstract: Embodiments provide bus synchronization system including a source module, a plurality of destination modules, and a data alignment controller. The source module is configured to synchronize a plurality of data segments of a data bus with a source clock signal, and transmit respective synchronized data segments to individual destination modules. The source module is further configured to transmit the source clock signal to the destination modules contemporaneously with the synchronized data segments. The source module thereafter receives feedback clock signals from the individual destination modules, the feedback clock signals being delayed versions of the source clock signal. The data alignment controller adjusts an output delay time for the individual destination modules, based on the received feedback clock signals, to temporally align output signals of the destination modules.
    Type: Grant
    Filed: June 20, 2012
    Date of Patent: September 30, 2014
    Assignee: Intel Corporation
    Inventors: Yoav Lossin, Aviad Wertheimer
  • Patent number: 8850259
    Abstract: Systems and methods are disclosed for precise generation of phase variation in digital signals. The disclosed signal generation embodiments generate a pattern of information bits that represents a digital signal with desired phase variations and transmit this digital pattern at high speed utilizing a serializer to generate a high speed bit stream. The high speed bit stream can be used to generate one or more digital signals, such as clock signals, having desired rates and desired phase variations. In certain embodiments, the desired phase variation can be introduced into the resulting digital signal by removing and/or inserting bits in a digital pattern thereby moving logic transitions (e.g., rising edge transitions, falling edge transitions) as desired within the resulting digital signal. In addition to clock signals, the resulting digital signals generated can be control signals, data signals and/or any other desired digital signal.
    Type: Grant
    Filed: January 7, 2011
    Date of Patent: September 30, 2014
    Assignee: Anue Systems, Inc.
    Inventor: Charles A. Webb, III
  • Patent number: 8850260
    Abstract: A data storage device having different operating modes is disclosed. The data storage device comprises a processor, a command execution module, and an error response module. The command execution module is configured to receive commands from the processor, execute the commands, and report status information to the processor. The error response module comprises a programmable register configured to store one of a plurality of different error response types for each of a plurality of errors, wherein the error response module is configured to receive a report of one of the errors, and to output an error response signal to the command execution module based on the error response type in the register corresponding to the reported error. The processor is configured to reprogram at least one of the error response types in the register for at least one of the errors when the data storage device switches operating modes.
    Type: Grant
    Filed: August 10, 2011
    Date of Patent: September 30, 2014
    Assignee: Western Digital Technologies, Inc.
    Inventor: Randy Fuller
  • Patent number: 8850261
    Abstract: Jobs submitted to a primary location of a service within a period of time before and/or after a fail-over event are determined and are resubmitted to a secondary location of the service. For example, jobs that are submitted fifteen minutes before the fail-over event and jobs that are submitted to the primary network before the fail-over to the second location is completed are resubmitted at the secondary location. After the fail-over event occurs, the jobs are updated with the secondary network that is taking the place of the primary location of the service. A mapping of job input parameters (e.g. identifiers and/or secrets) from the primary location to the secondary location are used by the jobs when they are resubmitted to the secondary location. Each job determines what changes are to be made to the job request based on the job being resubmitted.
    Type: Grant
    Filed: June 1, 2011
    Date of Patent: September 30, 2014
    Assignee: Microsoft Corporation
    Inventors: Daniel Blood, Alexander Hopmann, Siddharth Rajendra Shah, Viktoriya Taranov, Tarkan Sevilmis, Nikita Voronkov
  • Patent number: 8850262
    Abstract: An approach to detecting processor failure in a multi-processor environment is disclosed. The approach may include having each CPU in the system responsible for monitoring another CPU in the system. A CPUn reads a timestampn+1 created by CPUn+1 which CPUn is monitoring from a shared memory location. The CPUn reads its own timestampn and compares the two timestamps to calculate a delta value. If the delta value is above a threshold, the CPUn determines that CPUn+1 has failed and initiates error handling for the CPUs in the system. One CPU may be designated a master CPU, and be responsible for beginning the error handling process. In such embodiments, the CPUn may initiate error handling by notifying the master CPU that CPUn+1 has failed. If CPUn+1 is the master CPU, the CPUn may take additional steps to initiate error handling, and may broadcast a non-critical interrupt to all CPUs, triggering error handling.
    Type: Grant
    Filed: October 12, 2010
    Date of Patent: September 30, 2014
    Assignee: International Business Machines Corporation
    Inventors: Charles S. Cardinell, Roger G. Hathorn, Bernhard Laubli, Timothy J. Van Patten
  • Patent number: 8850263
    Abstract: Technologies are described herein for incorporating streaming and/or sampling in real-time log analysis. Representative samples of log data are extracted from the log files on a number of monitored hosts and streamed in real-time to log processors for processing. The log processors accumulate and process the representative samples of log data, and track a data completeness value representing an indication of a proportion of total log data represented by the representative samples received. The representative samples of log data are merged and collated. Estimated metrics are calculated from the merged and collated representative samples and the data completeness, and the estimated metrics are published to consumers in near real-time.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: September 30, 2014
    Assignee: Amazon Technologies, Inc.
    Inventors: Kendra A. Yourtee, Amos Dylan Vance, Muhammad Ali Siddiqui, Alexander S. Borst, Miles C. Kaufmann
  • Patent number: 8850264
    Abstract: An information terminal includes a start processing unit of a central processing unit which executes restart processing and a notification unit which outputs reason information indicating a reason for executing the restart processing.
    Type: Grant
    Filed: June 23, 2011
    Date of Patent: September 30, 2014
    Assignee: Fujitsu Limited
    Inventor: Yasuhiro Nozuki
  • Patent number: 8850265
    Abstract: The present invention discloses a method and system for processing test cases for applications to be tested. The method includes evaluating two applications to be tested; obtaining test cases for the two applications to be tested and determining resources and execution times needed by the test cases for the two applications to be tested. According to the compatibility relationship between the two applications to be tested, and the resources and execution times needed by the test cases for the two applications to be tested, the test cases for the two applications to be tested are clustered to a virtual machine instance to test the test cases for the two applications to be tested on the virtual machine instance.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: September 30, 2014
    Assignee: International Business Machines Corporation
    Inventors: Le He, Zhong J. Li, Yong G. Pan, Chunhua Tian, Rui Xiong Tian, Qing Bo Wang, Jun Zhu
  • Patent number: 8850266
    Abstract: A mechanism is provided for effectively validating execution units within a processor. A branch test pattern is generated for execution by an execution unit that is under validation testing. An execution pattern is selected from a set of execution patterns thereby forming a selected execution pattern. The selected execution pattern is loaded into a condition register. The branch test pattern is executed by an execution unit based on the selected execution pattern in the condition register. Responsive to the branch test pattern ending, values output from the execution unit during execution of the branch test pattern are compared to a set of expected results. Responsive to a match of the comparison, the process is repeated for each execution pattern in the set of execution patterns. Responsive to a match of the comparison for the execution patterns in the set of execution patterns, the execution unit is validated.
    Type: Grant
    Filed: June 14, 2011
    Date of Patent: September 30, 2014
    Assignee: International Business Machines Corporation
    Inventors: Sangram Alapati, Prathiba Kumar, Varun Mallikarjunan, Satish K. Sadasivam
  • Patent number: 8850267
    Abstract: An apparatus having a memory and multiple processors coupled to the memory is disclosed. The memory may be configured to store middleware. One or more processors may be configured to (a) generate initial test vectors to test one or more software modules executed on the processors and (b) generate modified test vectors by translating the initial test vectors in the middleware to a format that matches multiple hardware dependencies of the processors and multiple software dependencies of multiple operating systems. The test vectors generally have another format that is independent of (a) the hardware dependencies of the processors and (b) the software dependencies of the operating systems executed by the processors. The processors may be configured to generate a plurality of test results by exercising the software modules with the modified test vectors.
    Type: Grant
    Filed: August 2, 2012
    Date of Patent: September 30, 2014
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Manish K. Aggarwal, Ravi K. Singh, Anuradha S. Rao
  • Patent number: 8850268
    Abstract: The present invention relates to a method of determining an analyzing level for analyzing a system test procedure for testing a modular system having functional modules, comprising acquiring dependency data comprising dependency information describing at least one functional dependency of at least one functional module, acquiring change data comprising change information describing a change in a module test procedure for testing at least part of the at least one functional module located at a first system test level, acquiring impact data comprising impact information describing an impact of the change in the module test procedure on testing a functionality of the at least one functional module based on the dependency information and the change information, determining, based on the impact information, analyzing level data comprising analyzing level information describing an analyzing level being the system test level at which the system test procedure is analyzed.
    Type: Grant
    Filed: November 23, 2011
    Date of Patent: September 30, 2014
    Assignee: Brainlab AG
    Inventors: Stephan Froehlich, Jan Schormann, Joern Simon, Valentin Elefteriu, Alexander Urban
  • Patent number: 8850269
    Abstract: Techniques for managing a fused processing element are described. Embodiments receive streaming data to be processed by a plurality of processing elements. Additionally, an operator graph of the plurality of processing elements is established. The operator graph defines at least one execution path and wherein at least one of the processing elements of the operator graph is configured to receive data from at least one upstream processing element and transmit data to at least one downstream processing element. Embodiments detect an error condition has been satisfied at a first one of the plurality of processing elements, wherein the first processing element contains a plurality of fused operators. At least one of the plurality of fused operators is selected for removal from the first processing element. Embodiments then remove the selected at least one fused operator from the first processing element.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: September 30, 2014
    Assignee: International Business Machines Corporation
    Inventors: Michael J. Branson, John M. Santosuosso, Brandon W. Schulz
  • Patent number: 8850270
    Abstract: Computer-implemented method, computerized apparatus and a computer program product for test selection. The computer-implemented method comprising: obtaining a test suite comprising a plurality of tests for a Software Under Test (SUT); and selecting a subset of the test suite, wherein the subset provides coverage of the SUT that correlates to a coverage by a workload of the SUT, wherein the workload defines a set of input events to the SUT thereby defining portions of the SUT that are to be invoked during execution.
    Type: Grant
    Filed: July 19, 2012
    Date of Patent: September 30, 2014
    Assignee: International Business Machines Corporation
    Inventors: Andre Heiper, Aharon Kupershtok, Yaakov Yaari